ppc476 sections that end exactly on a page boundary need the
workaround applied when a function ends in "bctr", or when pasting
together code from multiple sections. The space allocated for the
patch area didn't allow for this case, while the code in
relocate_section performing the patches did, leading to an assertion
failure.
* elf32-ppc.c (ppc_elf_relax_section): Fix off by one error.
This probably could be fixed by making changes in relocate_section for
ifunc, but it's simpler to disable the optimisation for ifunc.
* elf64-ppc.c (ppc64_elf_adjust_dynamic_symbol): Don't attempt to
use dynrelocs for ifunc.
* elf32-ppc.c (ppc_elf_adjust_dynamic_symbol): Similarly.
doesn't always mean you need to define a function symbol on plt code.
If all references are in read-write sections, then using dynamic relocs
is OK.
bfd/
* elf32-ppc.c (ppc_elf_adjust_dynamic_symbol): Clear
pointer_equality_needed when !readonly_dynrelocs.
* elf64-ppc.c (ppc64_elf_adjust_dynamic_symbol): Likewise.
ld/testsuite/
* ld-powerpc/ambiguousv1.d: Match symbol table too.
* ld-powerpc/ambiguousv2.d: Likewise.
* ld-powerpc/ambiguousv1b.d: New.
* ld-powerpc/ambiguousv2b.d: New.
* ld-powerpc/powerpc.exp: Run new tests.
If we can dlopen an object then DF_STATIC_TLS is relevant.
* elf32-ppc.c (ppc_elf_check_relocs): Set DF_STATIC_TLS for PIEs too.
* elf64-ppc.c (ppc64_elf_check_relocs): Likewise.
Prior to 93d1b056 _SDA_BASE_ used to be defined in a linker script
output section. Now _SDA_BASE_ is defined in an input section that is
subject to being stripped. If the section is stripped we don't output
the symbol, which results in --emit-relocs trying to emit relocs with
dangling references to _SDA_BASE_.
* elf32-ppc.c (ppc_elf_size_dynamic_sections): Arrange to keep
.sdata/.sdata2 when _SDA_BASE_/_SDA2_BASE_ should be output
for --emit-relocs.
There are legitimate reasons to allow a signed value in a cmpli insn
field, for example to test for a "stw r1,lock@sdarel(r13)" instruction
in user code, a kernel might use
subis r3,r3,STW_R1_0R13@ha # subtract off high part
cmplwi r3,lock@sdarel # is low part accessing lock?
Since the lock@sdarel may take a range of -32768 to 32767,
the allowed range of cmpli immediate must be at least [-32768,65535].
bfd/
* elf32-ppc.c (ppc_elf_relocate_section): Treat field of cmpli
insn as a bitfield; Use complain_overflow_bitfield.
* elf64-ppc.c (ppc64_elf_relocate_section): Likewise.
opcodes/
* ppc-opc.c (UISIGNOPT): Define and use with cmpli.
gas/
* config/tc-ppc.c (ppc_insert_operand): Handle PPC_OPERAND_SIGNOPT
on unsigned fields. Comment on PPC_OPERAND_SIGNOPT signed fields
in 64-bit mode.
gold/
* powerpc.cc (relocate): Treat field of cmpli insn as a bitfield.
1) _SDA_BASE_ and _SDA2_BASE_ and defined automatically, in a similar
manner to the way _GLOBAL_OFFSET_TABLE_ is handled. It's a little
more complicated to remove the symbols because _SDA_BASE_ needs to
be there if either .sdata or .sbss is present, and similarly for
_SDA2_BASE.
2) The linker created .sdata and .sdata2 sections used for
R_PPC_EMB_SDAI16 and R_PPC_EMB_SDA2I16 pointers are created early.
Nowadays we strip unneeded sections from the output, so it isn't
necessary to delay creating the sections.
3) The output section for targets of various SDA relocs is now checked
as per the ABI(s). We previously allowed .sdata.foo and similar,
most likely because at some stage we were checking input sections.
Also, the patch fixes a long-standing bug in size_input_sections
that affects the values of symbols defined in stripped input
sections.
PR 16952
bfd/
* elf32-ppc.c (ppc_elf_create_linker_section): Move earlier.
Remove redundant setting of htab->elf.dynobj. Don't align.
Define .sdata symbols using _bfd_elf_define_linkage_sym.
(ppc_elf_create_glink): Call ppc_elf_create_linker_section.
(create_sdata_sym): Delete.
(elf_allocate_pointer_linker_section): Rename from
elf_create_pointer_linker_section. Align section.
(ppc_elf_check_relocs): Don't call ppc_elf_creat_linker_section
directly here, or create_sdata_sym. Set ref_regular on _SDA_BASE_
and _SDA2_BASE_.
(ppc_elf_size_dynamic_sections): Remove ATTRIBUTE_UNUSED on param.
Remove unnecessary tests on _SDA_BASE_ sym.
(maybe_strip_sdasym, ppc_elf_maybe_strip_sdata_syms): New functions.
(ppc_elf_relocate_section): Tighten SDA reloc symbol section checks.
* elf32-ppc.h (ppc_elf_set_sdata_syms): Delete.
(ppc_elf_maybe_strip_sdata_syms): Declare.
ld/
* emulparams/elf32ppccommon.sh (_SDA_BASE_, _SDA2_BASE_): Delete.
* emultempl/ppc32elf.em (ppc_before_allocation): Call
ppc_elf_maybe_strip_sdata_syms.
* ldlang.c (size_input_section): Correct output_offset value
for excluded input sections.
Fuss over bctr in call stubs.
* elf32-ppc.c (BA): Define
(ppc_elf_link_hash_table_create): Correct default_params.
(write_glink_stub): Pad small plt call stub with "ba 0" rather
than "nop" for ppc476_workaround.
(ppc_elf_finish_dynamic_sections): Likewise for branch table
and __glink_PLTresolve. Ensure plt call stub at end of page
doesn't allow fall-thru prefetch.
I got the ppc476 workaround wrong. bctr (and bctrl) as the last
instruction in a page can hit the icache bug if the preceding mtctr
insn is close by, and the destination is in the first few instructions
on the next page. This scenario can occur with code generated by gcc
to implement switch statements, or in code generated to call by
function pointer.
To prevent the bctr problem it is also necessary to remove other
instructions that otherwise would be safe.
bfd/
* elf32-ppc.c (ppc_elf_relocate_section): Remove bctr from list
of safe ppc476 insns at end of page. Also remove non-branch insns.
Expand comments.
ld/
* emultempl/ppc32elf.em (no_zero_padding, ppc_finish): New functions.
(LDEMUL_FINISH): Define.
Similar to the powerpc64 patch, this improves overflow checking in
elf32-ppc.c. Many reloc "howto" entries needed fixes, some just
cosmetic.
The patch also fixes the R_PPC_VLE_SDA21 reloc application code, which
was horribly broken. In fact, it may still be broken since Power ISA
2.07 says e_li behaves as
RT <- EXTS(li20 1:4 || li20 5:8 || li20 0 || li20 9:19)
where li20 is a field taken from bits 17..20, 11..15, 21..31 of the
instruction. Freescale VLEPEM says differently, and I assume
correctly, that
RT <- EXTS(li20 0:3 || li20 4:8 || li20 9:19)
The VLE_SDA21 relocation description matches this too.
Now the VLE_SDA21 relocation specifies in the case where e_addi16 is
converted to e_li for symbols in .PPC.EMB.sdata0 or .PPC.EMB.sbss0
(no base register), that the field is restricted to 16 bits, with the
sign bit being propagated to the top 4 bits. I don't see the sense in
restricting the value like this, so have allowed the full 20 bit
signed value. This of course is compatible with the reloc description
in that values in the 16 bit signed range will result in exactly the
same insn field as when the reloc description is followed to the
letter.
* elf32-ppc.c (ppc_elf_howto_raw): Correct overflow check for
many relocations. Correct bitsize and rightshift too for a number
of VLE relocs. Describe R_PPC_VLE_SDA21 and R_PPC_VLE_SDA21_LO.
Correct dst_mask on R_PPC_VLE_SDA21_LO.
(ppc_elf_vle_split16): Tidy, delete unnecessary prototype.
(ppc_elf_relocate_section): Modify overflow test for 16-bit
fields in instructions to signed/unsigned according to whether
the field takes a signed or unsigned value. Tidy vle split16 code.
Correct R_PPC_VLE_SDA21 and R_PPC_VLE_SDA21_LO handling.
5446cbdf82 broke powerpc-lynxos,
powerpc-netware, powerpc-windiss and powerpc-vxworks.
bfd/
* elf32-ppc.c (ppc_elf_link_hash_table_create): Provide default
params for targets that don't use ppc32elf.em.
ld/
* emulparams/elf32ppcvxworks.sh: Source plt_unwind.sh and
use ppc32elf.em.
* emultempl/ppc32elf.em (ppc_after_open): Don't compile for
vxworks.
(LDEMUL_AFTER_OPEN): Don't set for vxworks.
(PARSE_AND_LIST_LONGOPTS, PARSE_AND_LIST_OPTIONS): Exclude
-secure-plt, -bss-plt and -sdata-got when vxworks.
This fixes the glaring error that the ppc476 workaround wasn't
actually enabled for ld -r, and adjusts relocations to match moved
code.
bfd/
* elf32-ppc.c (ppc_elf_relocate_section): Move relocs on insns
patched for ppc476 workaround. Reapply branch taken/not taken
relocs.
ld/
* emultempl/ppc32elf.em (ppc_after_open_output): Really enable
ppc476 workaround for ld -r.
Adding long-branch stubs for __tls_get_addr calls that are optimised
away is silly. It also causes assertion failures on newer object files
that use R_PPC_TLSGD and R_PPC_TLSLD marker relocs, and half-optimised
(ie. broken) code for older object files.
PR 16546
* elf32-ppc.c (ppc_elf_relax_section): Don't build long-branch
stubs for calls to __tls_get_addr that we know will later be
optimised away.
The Linux kernel builds modules using ld -r. These might need the
ppc476 workaround, so enable it for ld -r if sections have sufficient
alignment to tell location within a page.
bfd/
* elf32-ppc.c (ppc_elf_relax_section): Enable ppc476 workaround
for ld -r, when code sections are sufficiently aligned.
* elf32-ppc.h (struct ppc_elf_params): Delete pagesize. Add
pagesize_p2.
ld/
* emultempl/ppc32elf.em (pagesize): New static var.
(ppc_after_open_output): Set params.pagesize_p2 from pagesize.
(PARSE_AND_LIST_ARGS_CASES): Adjust to use pagesize.
This patch provides a means for backend relax_section support to
increase the size of a section without needing to reallocate
section contents. This helps reduce memory usage when the added space
does not need to be written in relax_section, as is the case for
powerpc. Writing the stubs later means a few tweaks are needed in the
powerpc relocate_section function, but also removes some code
duplication since the extra ld -r relocs can be written there too.
* elf-bfd.h (struct elf_backend_data): Add caches_rawsize.
* elfxx-target.h (elf_backend_caches_rawsize): Define.
(elfNN_bed): Init new field.
* elflink.c (elf_link_input_bfd): Handle caches_rawsize.
* elf32-ppc.c (shared_stub_entry): Zero addi offset.
(ppc_elf_relax_section): Don't reallocate section here, write
stubs, or write out relocs for ld -r here..
(ppc_elf_relocate_section): ..instead write stubs here, and use
existing code to write out relocs for ld -r. Fix offset
adjustment on reloc for little-endian.
(elf_backend_caches_rawsize): Define.
This implements a work-around for an icache bug on 476 that can cause
execution of stale instructions when control falls through from one
page to the next. The idea is to prevent such fall-through by
replacing the last instruction on a page with a branch to a patch
area containing the instruction, then branch to the next page.
The patch also fixes a number of bugs in the existing support for long
branch trampolines.
bfd/
* elf32-ppc.c (struct ppc_elf_link_hash_table): Add params.
Delete emit_stub_syms, no_tls_get_addr_opt. Update all uses.
(ppc_elf_link_params): New function.
(ppc_elf_create_glink): Align .glink to 64 bytes for ppc476
workaround.
(ppc_elf_select_plt_layout): Remove plt_style and emit_stub_syms
parameters. Use htab->params instead.
(ppc_elf_tls_setup): Remove no_tls_get_addr_opt parameter.
(ppc_elf_size_dynamic_sections): Align __glink_PLTresolve to
64 bytes for ppc476 workaround.
(struct ppc_elf_relax_info): New.
(ppc_elf_relax_section): Exclude linker created sections and
those too small to hold one instruction. Don't add another
branch around trampolines on later relax passes. Don't
generate trampolines for undefined symbols when !relocatable,
nor for plugin symbols. Allocate space for ppc476 workaround
patch area. Free fixups on error return path.
(ppc_elf_relocate_section): Handle ppc476 workaround patching.
* elf32-ppc.h (struct ppc_elf_params): New.
(ppc_elf_select_plt_layout, ppc_elf_tls_setup): Update prototype.
(ppc_elf_link_params): Declare.
* section.c (SEC_INFO_TYPE_TARGET): Define.
* bfd-in2.h: Regenerate.
ld/
* emultempl/ppc32elf.em (no_tls_get_addr_opt, emit_stub_syms)
plt_style): Delete. Adjust all refs to instead use..
(params): ..this. New variable.
(ppc_after_open_output): New function. Tweak params and pass to
ppc_elf_link_params.
(ppc_after_open): Adjust ppc_elf_select_plt_layout call.
(ppc_before_allocation): Adjust ppc_elf_tls_setup call. Enable
relaxation for ppc476 workaround.
(PARSE_AND_LIST_*): Add --{no-,}ppc476-workaround support.
(LDEMUL_CREATE_OUTPUT_SECTION_STATEMENTS): Define.
On powerpc32, making ifuncs have non-default visibility in shared
libraries or pies can result in runtime failures. The problem is that
if gcc is told that a given function has non-default visibility, then
calls to that function are assumed to be local (which is true) and
thus need not go via a plt call stub (which is false for ifunc). If
the caller has no other reason to set up the got pointer (r30), code
won't be emitted to do so. However, a pic plt call stub makes use of
r30 to load the plt entry. So a call to an ifunc, which always needs
a plt entry, will fail.
This patch makes ld emit an error for the problem case, and allows
calls to non-default visibility ifuncs to work in normal executables.
I also fix some cases where ifuncs fail when using the old bss-plt.
* elf32-ppc.c (ppc_elf_check_relocs): For @local call to ifunc,
error when shared and force a plt call otherwise.
(ppc_elf_size_dynamic_sections): Don't emit DT_PPC_GOT unless
plt_type == PLT_NEW.
(ppc_elf_relocate_section): Add missing test to resolve ifuncs to
the appropriate call stub.
This removes the DT_PPC_TLSOPT/DT_PPC64_TLSOPT dynamic tag and replaces
it with DT_PPC_OPT/DT_PPC64_OPT tag to provide the same functionality
and more. This isn't backwards compatible, but the TLSOPT tag hasn't
been used since the tls optimisation support was never submitted to
glibc.
/include/elf/
* ppc.h (DT_PPC_TLSOPT): Delete.
(DT_PPC_OPT, PPC_OPT_TLS): Define.
* ppc64.h (DT_PPC64_TLSOPT): Delete.
(DT_PPC64_OPT, PPC64_OPT_TLS, PPC64_OPT_MULTI_TOC): Define.
bfd/
* elf32-ppc.c (ppc_elf_size_dynamic_sections): Use new DT_PPC_OPT
tag to specify tls optimisation.
* elf64-ppc.c (ppc64_elf_size_dynamic_sections): Likewise.
(ppc64_elf_finish_dynamic_sections): Specify whether multiple
toc pointers are used via DT_PPC64_OPT.
binutils/
* readelf.c (get_ppc_dynamic_type): Replace PPC_TLSOPT with PPC_OPT.
(get_ppc64_dynamic_type): Replace PPC64_TLSOPT with PPC64_OPT.
(ppc_elf_check_relocs): Separate dynrel counts for local syms
into ifunc and non-ifunc.
(allocate_dynrelocs): Always put ifunc relocs into reliplt.
(ppc_elf_size_dynamic_sections): Likewise.
(ppc_elf_relocate_section): Likewise.
masks for all local ifunc syms.
(allocate_dynrelocs): Don't use htab->relgot for ifunc.
(ppc_elf_size_dynamic_sections): Likewise.
(ppc_elf_relocate_section): Likewise.
Pedro Alves <palves@redhat.com>
* Makefile.in (SOURCE_HFILES): Add `elf-linux-psinfo.h'.
* elf-bfd.h (elf_internal_linux_prpsinfo): New structure
declaration.
(elfcore_write_linux_prpsinfo32, elfcore_write_linux_prpsinfo64)
(elfcore_write_ppc32_linux_prpsinfo32): New declarations.
* elf-linux-psinfo.h: New file.
* elf.c: Include elf-linux-psinfo.h.
(elfcore_write_linux_prpsinfo32, elfcore_write_linux_prpsinfo64):
New functions.
* elf32-ppc.c: Include `elf-linux-psinfo.h'.
(elf_external_ppc_linux_prpsinfo32): New structure declaration.
(PPC_LINUX_PRPSINFO32_SWAP_FIELDS): New macro.
(elfcore_write_ppc_linux_prpsinfo32): New function.
bfd/
* elf32-ppc.c (ppc_elf_reloc_type_lookup): Decode ppc64 _DS
bfd_reloc values. Map to corresponding D-form relocs.
(is_insn_ds_form, is_insn_qs_form): New functions.
(ppc_elf_relocate_section): Validate insn with DS-form or DQ-form
fields using D-form reloc.
gas/
* config/tc-ppc.c (ppc_setup_opcodes): Fix comment.
(md_assemble): Translate to _DS relocs for ppc32 as well as ppc64.
(tc_gen_reloc): Handle _DS relocs in ppc32 mode.
first one is zero size or discarded.
* elf32-ppc.c (ppc_elf_size_dynamic_sections): Set most of
glink_eh_frame contents here..
(ppc_elf_finish_dynamic_sections): ..rather than here. Just set
offset to .glink.
bfd_get_section_lma, bfd_get_section_alignment,
bfd_get_section_flags, bfd_get_section_userdata): Rewrite macros
in order to use the `bfd' argument.
* bfd-in2.h: Regenerate.
* elf-vxworks.c (elf_vxworks_finish_dynamic_entry): Pass proper `bfd'
as the first argument for `bfd_get_section_alignment'.
* elf32-arm.c (create_ifunc_sections): Likewise, for
`bfd_set_section_alignment'.
* elf32-m32r.c (m32r_elf_relocate_section): Likewise, for
`bfd_get_section_name'.
* elf32-microblaze.c (microblaze_elf_relocate_section): Likewise.
* elf32-ppc.c (ppc_elf_size_dynamic_sections): Likewise.
(ppc_elf_relocate_section): Likewise.
* elf64-mmix.c (mmix_final_link_relocate): Likewise, for
`bfd_get_section_vma'.
* elf64-ppc.c (create_linkage_sections): Likewise, for
`bfd_set_section_alignment'.
* emultempl/m68hc1xelf.em (hook_in_stub): Pass proper `bfd'
as the first argument for `bfd_get_section_name'.
* config/tc-alpha.c (maybe_set_gp): Pass proper `bfd'
as the first argument for `bfd_get_section_vma'.
