* Makefile.am (BFD32_BACKENDS, BFD32_BACKENDS_CFILES): Move MIPS ELF
files to...
(BFD64_BACKENDS, BFD64_BACKENDS_CFILES): ...here.
* Makefile.in: Regenerate.
* config.bfd: Enclose all MIPS ELF targets in #ifdef BFD64.
Set want64 to true for them at the end.
* targets.c (_bfd_target_vector): Protect MIPS ELF targets with
#ifdef BFD64.
gas/
* config/tc-mips.c: Assert that offsetT and valueT are at least
8 bytes in size.
(GPR_SMIN, GPR_SMAX): New macros.
(macro, mips_ip): Remove code for 4-byte valueT and offsetT.
ld/
* Makefile.am (ALL_EMULATION_SOURCES): Move MIPS ELF emulations to...
(ALL_64_EMULATION_SOURCES): ...here.
* Makefile.in: Regenerate.
* gas/mips/mips.exp: Remove "LOSE" comments.
(run_dump_test_arch): Remove format selector support.
(run_dump_test_arches): Remove associated upvars.
(elf, ecoff, aout, no_mips16, no_micromips): Remove variables.
Remove all conditions based on them, on the assumption that $elf
is true and the others are false. Rename "elf-jal" to "jal".
(tmips): Set to "t" for *bsd targets.
* gas/mips/elf-jal.d: Rename to...
* gas/mips/jal.d: ...this, replacing the old file.
* gas/mips/micromips@elf-jal.d: Rename to...
* gas/mips/micromips@jal.d: ...this.
* gas/mips/at-1.d, gas/mips/ld.d, gas/mips/l_d.d, gas/mips/lui.d,
gas/mips/mips1@l_d.d, gas/mips/mips1@ld-forward.d, gas/mips/mips1@ld.d,
gas/mips/mips1@s_d.d, gas/mips/s_d.d, gas/mips/sd.d: Remove ECOFF
relocation names. Do not allow any offset on the symbol.
* config/tc-mips.c: Remove OBJ_ELF, OBJ_MAYBE_ELF and IS_ELF
conditions. Remove any code deselected by them.
(s_mips_frame, s_mips_mask): Handle ECOFF_DEBUGGING case first.
* doc/as.texinfo: Use MIPS rather than @sc{mips} throughout.
Use "CPU" instead of "cpu".
* doc/c-mips.texi: Likewise.
(MIPS Opts): Rename to MIPS Options.
(MIPS option stack): Rename to MIPS Option Stack.
(MIPS ASE instruction generation overrides): Rename to
MIPS ASE Instruction Generation Overrides (for now).
(MIPS floating-point): Rename to MIPS Floating-Point.
* config/tc-mips.c (ISA_SUPPORTS_SMARTMIPS, ISA_SUPPORTS_DSP_ASE)
(ISA_SUPPORTS_DSP64_ASE, ISA_SUPPORTS_DSPR2_ASE, ISA_SUPPORTS_EVA_ASE)
(ISA_SUPPORTS_MT_ASE, ISA_SUPPORTS_MCU_ASE, ISA_SUPPORTS_VIRT_ASE)
(ISA_SUPPORTS_VIRT64_ASE): Delete.
(mips_ase): New structure.
(mips_ases): New table.
(FP64_ASES): New macro.
(mips_ase_groups): New array.
(mips_isa_rev, mips_ase_mask, mips_check_isa_supports_ase)
(mips_check_isa_supports_ases, mips_set_ase, mips_lookup_ase): New
functions.
(is_opcode_valid): Use mips_ases to get the 64-bit ASE flags.
(md_parse_option): Use mips_ases and mips_set_ase instead of
separate case statements for each ASE option.
(mips_after_parse_args): Use FP64_ASES. Use
mips_check_isa_supports_ases to check the ASEs against
other options.
(s_mipsset): Use mips_ases and mips_set_ase instead of
separate if statements for each ASE option. Use
mips_check_isa_supports_ases, even when a non-ASE option
is specified.
gas/testsuite/
* gas/mips/ase-errors-1.s, gas/mips/ase-errors-1.l,
gas/mips/ase-errors-2.s, gas/mips/ase-errors-2.l,
gas/mips/ase-errors-3.s, gas/mips/ase-errors-3.l,
gas/mips/ase-errors-4.s, gas/mips/ase-errors-4.l: New tests.
* gas/mips/mips.exp: Run them.
* config/tc-mips.c (mips_set_options): Replace separate "ase_*" fields
with a single "ase" bitmask.
(mips_opts): Update accordingly.
(file_ase, file_ase_explicit): New variables.
(file_ase_mips3d, file_ase_mdmx, file_ase_smartmips, file_ase_dsp)
(file_ase_dspr2, file_ase_eva, file_ase_mt, file_ase_virt): Delete.
(ISA_HAS_ROR): Adjust for mips_set_options change.
(is_opcode_valid): Take the base ase mask directly from mips_opts.
(mips_ip): Adjust for mips_set_options change.
(md_parse_option): Likewise. Update file_ase_explicit.
(mips_after_parse_args): Adjust for mips_set_options change.
Use bitmask operations to select the default ASEs. Set file_ase
rather than individual per-ASE variables.
(s_mipsset): Adjust for mips_set_options change.
(mips_elf_final_processing): Test file_ase rather than
file_ase_mdmx. Remove commented-out code.
* config/tc-mips.c (mips_cpu_info): Add an "ase" field.
(MIPS_CPU_ASE_SMARTMIPS, MIPS_CPU_ASE_DSP, MIPS_CPU_ASE_MT)
(MIPS_CPU_ASE_MIPS3D, MIPS_CPU_ASE_MDMX, MIPS_CPU_ASE_DSPR2)
(MIPS_CPU_ASE_MCU, MIPS_CPU_ASE_VIRT, MIPS_CPU_ASE_EVA): Delete.
(mips_after_parse_args): Use the new "ase" field to choose
the default ASEs.
(mips_cpu_info_table): Move ASEs from the "flags" field to the
"ase" field.
* config/tc-m68k.h (TC_CHECK_ADJUSTED_BROKEN_DOT_WORD): Define.
* config/tc-m68k.c (tc_m68k_check_adjusted_broken_word): New
function. Generates an error if the adjusted offset is out of a
16-bit range.
gas/
* config/tc-nios2.c (md_apply_fix): Mask constant
BFD_RELOC_NIOS2_HIADJ16 value to 16 bits.
gas/testsuite/
* gas/nios2/movia.s: Add additional test case with negative
constant value.
* gas/nios2/movia.d: Likewise.
* config/tc-mips.c (append_insn): Don't do branch relaxation for
MIPS-3D instructions either.
(md_convert_frag): Update the COPx branch mask accordingly.
* config/tc-mips.c (md_show_usage): Document --[no-]relax-branch
option.
* doc/as.texinfo (Overview): Add --relax-branch and
--no-relax-branch.
* doc/c-mips.texi (MIPS Opts): Document --relax-branch and
--no-relax-branch.
gas/testsuite/
* gas/mips/relax-bc1any.l: New test.
* gas/mips/relax-bc1any.s: New test source.
* gas/mips/mips.exp: Run the new test.
2013-06-08 Catherine Moore <clm@codesourcery.com>
* config/tc-mips.c (is_opcode_valid): Build ASE mask.
(is_opcode_valid_16): Pass ase value to opcode_is_member.
(append_insn): Change INSN_xxxx to ASE_xxxx.
include/
2013-06-08 Catherine Moore <clm@codesourcery.com>
* opcode/mips.h (mips_opcode): Add ase field.
(INSN_ASE_MASK): Delete.
(INSN_DSP): Rename to ASE_DSP. Provide new value.
(INSN_DSPR2): Rename to ASE_DSPR2. Provide new value.
(INSN_MCU): Rename to ASE_MCU. Provide new value.
(INSN_MDMX): Rename to ASE_MDMX. Provide new value.
(INSN_MIPS3d): Rename to ASE_MIPS3D. Provide new value.
(INSN_MT): Rename to ASE_MT. Provide new value.
(INSN_SMARTMIPS): Rename to ASE_SMARTMIPS. Provide new value.
(INSN_VIRT): Rename to ASE_VIRT. Provide new value.
(INSN_VIRT64): Rename to ASE_VIRT64. Provide new value.
(opcode_is_member): Add ase argument. Check ase.
opcodes/
2013-06-08 Catherine Moore <clm@codesourcery.com>
Richard Sandiford <rdsandiford@googlemail.com>
* micromips-opc.c (D32, D33, MC): Update definitions.
(micromips_opcodes): Initialize ase field.
* mips-dis.c (mips_arch_choice): Add ase field.
(mips_arch_choices): Initialize ase field.
(set_default_mips_dis_options): Declare and setup mips_ase.
* mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64,
MT32, MC): Update definitions.
(mips_builtin_opcodes): Initialize ase field.
* write.c (resolve_reloc_expr_symbols): On REL targets don't
convert relocs who have no relocatable field either. Rephrase
the conditional so that the PC-relative check is only applied
for REL targets.
gas/testsuite/
* gas/mips/jalr3.d: New test.
* gas/mips/jalr3-n32.d: New test.
* gas/mips/jalr3-n64.d: New test.
* gas/mips/jalr3.s: New test source.
* gas/mips/mips.exp: Run the new tests.
ld/testsuite/
* ld-mips-elf/jalr3.dd: New test.
* ld-mips-elf/jalr3.ld: New test linker script.
* ld-mips-elf/mips-elf.exp: Run the new test.
* config/tc-mips.c (macro) <ld>: Don't use $zero for address
calculation.
gas/testsuite/
* gas/mips/ld-zero.d: New test.
* gas/mips/ld-zero-2.d: New test.
* gas/mips/ld-zero-3.d: New test.
* gas/mips/ld-zero-q.d: New test.
* gas/mips/ld-zero-u.d: New test.
* gas/mips/ecoff@ld-zero-3.d: New test.
* gas/mips/micromips@ld-zero-2.d: New test.
* gas/mips/micromips@ld-zero-3.d: New test.
* gas/mips/ld-zero.s: New test source.
* gas/mips/ld-zero-2.s: New test source.
* gas/mips/ld-zero-3.s: New test source.
* gas/mips/ld-zero-q.s: New test source.
* gas/mips/ld-zero-u.s: New test source.
* gas/mips/mips.exp: Run the new tests.
2013-05-28 Marcus Shawcroft <marcus.shawcroft@arm.com>
* config/tc-aarch64.c (md_apply_fix): Move value range checking
inside fx_done condition.
2013-05-28 Marcus Shawcroft <marcus.shawcroft@arm.com>
* gas/aarch64/adr_1.d: New file.
* gas/aarch64/adr_1.s: New file.
* gas/aarch64/b_1.d: New file.
* gas/aarch64/b_1.s: New file.
* gas/aarch64/beq_1.d: New file.
* gas/aarch64/beq_1.s: New file.
* gas/aarch64/ldr_1.d: New file.
* gas/aarch64/ldr_1.s: New file.
* gas/aarch64/tbz_1.d: New file.
* gas/aarch64/tbz_1.s: New file.
* s390-opc.txt (flogr): Require a register pair destination.
gas/testsuite/
* gas/s390/zarch-z9-109-err.s, gas/s390/zarch-z9-109-err.l: New test.
* gas/s390/s390.exp: Run it.
and data fixups performing shift/high adjust/sign extension on
fieldval. Sink fx_pcrel handling and checks. Use fixP->fx_size
when writing data fixups rather than recalculating size.
Add -mcpu command to specify core type.
* doc/c-msp430.c: Update documentation.
* gas/msp430/opcodes.s: Use correct value for .arch pseudo.
* gas/msp430/msp430x.d: Use correct value for -mcpu option.
* doc/binutils.texi: Document -Mvirt disassembler option.
gas/ChangeLog:
* config/tc-mips.c (struct mips_set_options): New ase_virt field.
(mips_opts): Update for the new field.
(file_ase_virt): New variable.
(ISA_SUPPORTS_VIRT_ASE): New macro.
(ISA_SUPPORTS_VIRT64_ASE): New macro.
(MIPS_CPU_ASE_VIRT): New define.
(is_opcode_valid): Handle ase_virt.
(macro_build): Handle "+J".
(validate_mips_insn): Likewise.
(mips_ip): Likewise.
(enum options): Add OPTION_VIRT and OPTION_NO_VIRT.
(md_longopts): Add mvirt and mnovirt
(md_parse_option): Handle OPTION_VIRT and OPTION_NO_VIRT.
(mips_after_parse_args): Handle ase_virt field.
(s_mipsset): Handle "virt" and "novirt".
(mips_elf_final_processing): Add a comment about virt ASE might need a new flag.
(md_show_usage): Print out the usage of -mvirt and mno-virt options.
* doc/c-mips.texi: Document -mvirt and -mno-virt.
Document ".set virt" and ".set novirt".
gas/testsuite/ChangeLog:
* gas/mips/mips.exp: Run virt and virt64 testcases.
* gas/mips/virt.d: New file.
* gas/mips/virt.s: New file.
* gas/mips/virt64.d: New file.
* gas/mips/virt64.s: New file.
include/opcode/ChangeLog:
* mips.h (OP_MASK_CODE10): Correct definition.
(OP_SH_CODE10): Likewise.
Add a comment that "+J" is used now for OP_*CODE10.
(INSN_ASE_MASK): Update.
(INSN_VIRT): New macro.
(INSN_VIRT64): New macro
opcodes/ChangeLog:
* mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2 .
Add INSN_VIRT and INSN_VIRT64 to mips64r2.
(parse_mips_dis_option): Handle the virt option.
(print_insn_args): Handle "+J".
(print_mips_disassembler_options): Print out message about virt64.
* mips-opc.c (IVIRT): New define.
(IVIRT64): New define.
(mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
Move rfe to the bottom as it conflicts with tlbgp.
(PPC_VLE_SPLIT16D, PPC_VLE_LO16A, PPC_VLE_LO16D): Likewise.
(PPC_VLE_HI16A, PPC_VLE_HI16D): Likewise.
(PPC_VLE_HA16A, PPC_VLE_HA16D): Likewise.
(md_apply_fix): Set fx_no_overflow for assorted relocations.
Shift and sign-extend fieldval for use by some VLE reloc
operand->insert functions.
* config/tc-mips.c (mips_pseudo_table): Add stabd and stabs entries.
(s_mips_stab): Do not restrict to stabn only.
gas/testsuite/
* gas/mips/mips16-stabs.s, gas/mips/mips16-stabs.d: New test.
* gas/mips/mips.exp: Run it.
* config.bfd (msp430): Define targ_selvecs.
* configure.in: Add bfd_elf32_msp430_ti_vec.
* cpu-msp430.c: Add some more MSP430 machine numbers.
* elf32-msp430.c Add support for MSP430X relocations.
Add support for TI compiler generated relocations.
Add support for sym_diff relocations.
Add support for relaxing out of range short branches into long
branches.
Add support for MSP430 attribute section.
* reloc.c: Add MSP430X relocations.
* targets.c: Add bfd_elf32_msp430_ti_vec.
* bfd-in2.h: Regenerate.
* configure: Regenerate.
* libbfd.h: Regenerate.
* readelf.c: Add support for MSP430X architecture.
* readelf.exp: Expect -wi test to fail for the MSP430.
* config/tc-msp430.c: Add support for the MSP430X architecture.
Add code to insert a NOP instruction after any instruction that
might change the interrupt state.
Add support for the LARGE memory model.
Add code to initialise the .MSP430.attributes section.
* config/tc-msp430.h: Add support for the MSP430X architecture.
* doc/c-msp430.texi: Document the new -mL and -mN command line
options.
* NEWS: Mention support for the MSP430X architecture.
* gas/all/gas.exp: Skip the DIFF1 test for the MSP430.
Expect the FORWARD test to pass for the MSP430.
Skip the REDEF tests for the MSP430.
Expect the 930509A test to fail for the MSP430.
* gas/all/sleb128-4.d: Skip for the MSP430.
* gas/elf/elf.exp: Set target_machine to msp430 for the MSP430.
Skip the EHOPT0 test for the MSP430.
Skip the REDEF and EQU-RELOC tests for the MSP430.
* gas/elf/section2.e-msp430: New file.
* gas/lns/lns-big-delta.d: Remove expectation of 20-bit
addresses.
* gas/lns/lns.exp: Use alternate LNS COMMON test for the MSP430.
* gas/msp430/msp430x.s: New test.
* gas/msp430/msp430x.d: Expected disassembly.
* gas/msp430/msp430.exp: Run new test.
* gas/msp430/opcode.d: Update expected disassembly.
* msp430.h: Add MSP430X relocs.
Add some more MSP430 machine numbers.
Add values used by .MSP430.attributes section.
* msp430.h: Add patterns for MSP430X instructions.
* Makefile.am: Add emsp430X.c
* Makefine.in: Regenerate.
* configure.tgt (msp430): Add msp430X emulation.
* ldmain.c (multiple_definition): Only disable relaxation if it
was enabled by the user.
* ldmain.h (RELAXATION_ENABLED_BY_USER): New macro.
* emulparams/msp430all.sh: Add support for MSP430X.
* emultempl/generic.em: (before_parse): Enable relaxation for the
MSP430.
* scripttempl/msp430.sc: Reorganize sections. Add .rodata
section.
* scripttempl/msp430_3.sc: Likewise.
* NEWS: Mention support for MSP430X.
* ld-elf/flags1.d: Expect this test to pass on the MSP430.
* ld-elf/init-fini-arrays.d: Expect this test to fail on the
MSP430.
* ld-elf/merge.d: Expect this test to pass on the MSP430.
* ld-elf/sec64k.exp: Skip these tests for the MSP430.
* ld-gc/pr13683.d: Expect this test to fail on the MSP430.
* ld-srec/srec.exp: Expect these tests to fail on the MSP430.
* ld-undefined/undefined.exp: Expect the UNDEFINED LINE test to
fail on the MSP430.
* msp430-dis.c: Add support for MSP430X instructions.
* config.bfd: Replace alpha*-*-linuxecoff* pattern with
alpha*-*-linux*ecoff*.
binutils/testsuite/
* lib/binutils-common.exp (is_elf_format): Also exclude
*-*-linux*ecoff*.
gas/
* configure.tgt: Replace alpha*-*-linuxecoff* pattern with
alpha*-*-linux*ecoff*.
ld/
* configure.tgt: Replace alpha*-*-linuxecoff* pattern with
alpha*-*-linux*ecoff*. Update the `sed' pattern used to convert
from alpha*-*-linux-* to alpha*-*-linux*ecoff*.
according to the target parameter. Don't call s_segm since s_segm
calls bfd_set_arch_mach using stdoutput, but stdoutput isn't
initialized yet.
(md_begin): Call s_segm according to target parameter from command
line.
gas/
* config/tc-nios2.c (nios2_control_register_arg_p): Rename
"fstatus" control register to "eccinj".
opcodes/
* nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
to "eccinj".
This patch enables x32 for x86_64-*-elf* for embedded target and disables
rex tests since it uses '/' as prefix separator which is `\' for
x86_64-*-elf*.
bfd/
* config.bfd (targ_selvecs): Add bfd_elf32_x86_64_vec for
x86_64-*-elf*.
gas/testsuite/
* gas/i386/rex.d: Skip x86_64-*-elf*.
* gas/i386/ilp32/rex.d: Likewise.
ld/
* configure.tgt (targ_extra_emuls): Adds elf32_x86_64 for
x86_64-*-elf*.
(targ_extra_libpath): Likewise.
(tdir_elf_i386): Replace x86_64 with i386 for x86_64-*-elf*.
2013-04-10 Jan Beulich <jbeulich@suse.com>
* gas/config/tc-arm.c (encode_arm_addr_mode_3): Only reject base
register being PC when is_t or writeback, and use distinct
diagnostic for the latter case.
gas/testsuite/
2013-04-10 Jan Beulich <jbeulich@suse.com>
* gas/testsuite/gas/arm/ldst-pc.s: Add index, non-writeback
forms of various loads and stores with PC as base.
* gas/testsuite/gas/arm/ldst-pc.d: Update accordingly.
2013-04-10 Jan Beulich <jbeulich@suse.com>
* gas/config/tc-arm.c (parse_operands): Re-write
po_barrier_or_imm().
(do_barrier): Remove bogus constraint().
(do_t_barrier): Remove.
gas/testsuite/
2013-04-10 Jan Beulich <jbeulich@suse.com>
* gas/arm/barrier-bad.d: Change title.
* gas/arm/barrier-bad.s: Add immediate form of ISB and DSB as
well as one symbolic form of DSB.
* gas/arm/barrier-bad.l: Update accordingly.
* gas/arm/barrier-bad-thumb.d: Adjust title. Use barrier-bad.s as
source. Pass -mthumb to gas.
* gas/arm/barrier-bad-thumb.l: Remove.
* gas/arm/barrier-bad-thumb.s: Remove.
* gas/arm/barrier-thumb.d: Adjust title. Use barrier.s as source.
Pass -mthumb to gas.
* gas/arm/barrier-thumb.s: Remove.
2013-04-09 Jan Beulich <jbeulich@suse.com>
* gas/config/tc-arm.c (do_vmrs): Accept all control registers.
Use local variable Rt in more places.
(do_vmsr): Accept all control registers.
gas/testsuite/
2013-04-09 Jan Beulich <jbeulich@suse.com>
* gas/arm/vfp1xD.s: Add VMRS/VMSR tests with FPINST, FPINST2,
and C15.
* gas/arm/vfp1xD.d: Update accordingly.
2013-04-09 Jan Beulich <jbeulich@suse.com>
* gas/config/tc-arm.c (do_neon_mov): Fake an instruction suffix
if there was none specified for moves between scalar and core
register.
gas/testsuite/
2013-04-09 Jan Beulich <jbeulich@suse.com>
* gas/arm/neon-omit.s: Add tests for suffix less VMOV.
* gas/arm/neon-omit.d: Update accordingly.
2013-04-09 Jan Beulich <jbeulich@suse.com>
* gas/config/tc-arm.c (do_neon_ldx_stx): Reject VSTn in the
NEON_ALL_LANES case.
gas/testsuite/
2013-04-09 Jan Beulich <jbeulich@suse.com>
* gas/arm/neon-addressing-bad.s: Add test for further invalid VST
operands.
* gas/arm/neon-addressing-bad.l: Update accordingly.
Make current with UA2011 specification.
Add an F_PREFERRED opcode flag that indicates a preferred alias
when multiple aliases for the same opcode exists.
For 'lzd':
Add 'lzcnt' as primary instruction, and make 'lzd' an alias.
Add 'ldtw', 'ldtwa', 'sttw', 'sttwa':
The modern opcode for for 'ldd', 'ldda', 'std', and 'stda' on
integer registers. Mark the latter now as aliases.
For 'flush':
Support "[address]" syntax as well as plain "address".
Rework 'mov' aliases for 'wr':
Eliminate bogus three operand moves, and encode the
instructions properly for the "mov REG, %ASR" cases,
specifically we should encode the register in rs2 not rs1 as
per The SPARC V8 Architecture Manual.
Add missing cbcond aliases:
c{w,x}bz, c{w,x}blu, c{w,x}bnz, c{w,x}bgeu
Add 'd' suffix VIS logical ops:
The primary opcode for 'fzero' is now 'fzerod' (compare with
'fzeros'), for example. And thus 'fzero' is now an alias.
Add modern opcodes for condition code setting edge instructions:
They are now edgeN{,l}cc instead of plain edgeN{,l}.
Add modern opcodes for VIS comparisons:
All VIS comparisons now start with prefix "fp", retain the
older variants as aliases.
The signed variants for equal and not-equal have "u" aliases
to show that these comparisons are equally suited for unsigned
compares.
Update existing test cases as needed, and add several new ones.
include/opcode/
* sparc.h (F_PREFERRED): Define.
(F_PREF_ALIAS): Define.
opcodes/
* sparc-dis.c (compare_opcodes): When encountering multiple aliases
of an opcode, prefer the one with F_PREFERRED set.
* sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
ops. Make 64-bit VIS logical ops have "d" suffix in their names,
mark existing mnenomics as aliases. Add "cc" suffix to edge
instructions generating condition codes, mark existing mnenomics
as aliases. Add "fp" prefix to VIS compare instructions, mark
existing mnenomics as aliases.
gas/testsuite/
* gas/sparc/cbcond.s: Add tests for new opcode aliases.
* gas/sparc/cbcond.d: Updated.
* gas/sparc/hpcvis3.s: Add tests for new opcode aliases.
* gas/sparc/hpcvis3.d: Updated.
* gas/sparc/v8-movwr-imm.d: Fix expected disassembly.
* gas/sparc/edge.s: New test.
* gas/sparc/edge.d: Expected disassembly.
* gas/sparc/flush.s: New test.
* gas/sparc/flush.d: Expected disassembly.
* gas/sparc/ldd_std.s: New test.
* gas/sparc/ldd_std.d: Expected disassembly.
* gas/sparc/ldtw_sttw.s: New test.
* gas/sparc/ldtw_sttw.d: Expected disassembly.
* gas/sparc/sparc.exp: Run new tests.
* tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
* gas/tic6x/insns16-lsd-unit.s: Correct bit patterns for mvk, add
and xor.
* gas/tic6x/insns16-lsd-unit.d: Update expected output.
2013-03-26 Douglas B Rupp <rupp@gnat.com>
* config/tc-ia64.c (emit_one_bundle): Move last_slot adjustment
after fixup.
gas/testsuite/
2013-03-26 Douglas B Rupp <rupp@adacore.com
* gas/ia64/ia64.exp: Add new test reloc-mlx
* gas/ia64/reloc-mlx.[sd]: New test for X-unit reloc.
* gas/ia64/pcrel.d: Fix output for X-unit reloc.
2013-03-21 Will Newton <will.newton@linaro.org>
* config/tc-arm.c (encode_thumb32_addr_mode): Emit an error for all
pc-relative str instructions in Thumb mode.
gas/testsuite/ChangeLog:
2013-03-21 Will Newton <will.newton@linaro.org>
* gas/arm/thumb2_relax.d: Strip out invalid pc-relative strs.
* gas/arm/thumb2_relax.s: Likewise.
* gas/arm/thumb32.d: Likewise.
* gas/arm/thumb32.l: Likewise.
* gas/arm/thumb32.s: Likewise.
* gas/arm/thumb2_str-bad.d: New file.
* gas/arm/thumb2_str-bad.l: Likewise.
* gas/arm/thumb2_str-bad.s: Likewise.
* tic6x-opcode-table.h: Rename mpydp's specific operand type macro
from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
tic6x_operand_xregpair operand coding type.
Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
opcode field, usu ORXREGD1324 for the src2 operand and remove the
TIC6X_FLAG_NO_CROSS.
* gas/tic6x/insns-bad-1.s: Remove test-case for mpydp with
cross-path.
* gas/tic6x/insns-bad-1.l: Update expected output.
* gas/tic6x/insns-c674x.s: Add a test-case for mpydp with
cross-path.
* gas/tic6x/insns-c674x.d: Update expected output.
order to encode separately the msb and lsb of a register pair ; this will be
needed to encode the opcodes the same
way as Ti assembler does.
* gas/config/tc-tic6x.c: handle tic6x_coding_dreg_(msb|lsb) field coding types
and use it to encode register pair numbers when required.
* opcodes/tic6x-dis.c: decodes opcodes that have individual msb and lsb halves
in src1 & src2 fields ; discard the src1 (lsb) value and only use src2 (msb),
discarding bit 0, to follow what Ti SDK does in that case as any value in the
src1 field yields the same output with SDK disassembler.
* include/opcode/tic6x-opcode-table.h: modify absdp, dpint, dpsp, dptrunc,
rcpdp and rsqrdp opcodes to use the new field coding types.
* gas/testsuite/gas/tic6x/insns-c674x.d, gas/testsuite/gas/tic6x/insns-c674x.s
: add test case for the newly generated opcode but keep the old ones as they
seem legit as per Ti disassembler output.
