darkkirb/old-cross-binutils
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23 commits

Author SHA1 Message Date
Nick Clifton
c5ea1d538f Add support for v850e1 instructions 2003-09-05 17:46:52 +00:00
Nick Clifton
ebc115b7bb * simops.c (OP_40): Delete. Move code to... 
* v850-igen.c (): ...Here. Sign extend the first operand.
* simops.h (OP_40): Remove prototype.
 2003-04-06 08:51:04 +00:00
Nick Clifton
5d6a173dca Remove v850ea references 2002-09-19 07:52:02 +00:00
Nick Clifton
896ad91016 Remove illegal instruciton pattern, since it is the same as the breakpoint 
pattern.
 2000-05-30 18:36:57 +00:00
Frank Ch. Eigler
b9791fcdd6 * merge from internal tree 
2000-04-14  Gary Thomas  <gthomas@redhat.com>

	* v850.igen: Define 'br *' as illegal since this is the only
	way to provide a breakpoint on some v850 family processors.
 2000-05-08 23:07:39 +00:00
Frank Ch. Eigler
de616bc738 * more compatibility with v850 hardware 
2000-03-24  Frank Ch. Eigler  <fche@redhat.com>

	* v850.igen (ilgop): New insn pattern for four-byte breakpoints.
 2000-03-25 00:17:21 +00:00
Stan Shebs
c906108c21 Initial creation of sourceware repository 1999-04-16 01:35:26 +00:00
Stan Shebs
071ea11e85 Initial creation of sourceware repository 1999-04-16 01:34:07 +00:00
Nick Clifton
22c39e1487 Reverrt BREAK value back to its old value 1997-12-05 17:27:34 +00:00
Nick Clifton
b65b4d8b06 Fixed sanitization, 
Changed pattern for break insn.
 1997-12-04 01:29:25 +00:00
Andrew Cagney
a276b6f057 Clean up tracing for Bcond & jmp insns. 
Fix computation of disp16 and disp22.
Clean up tracing of sld* insns.
 1997-09-19 06:39:21 +00:00
Andrew Cagney
bd4c35cc6d Fix cmov immed. 1997-09-19 02:20:02 +00:00
Andrew Cagney
60fe0e06a8 Fix cmov insn. 1997-09-19 00:50:19 +00:00
Andrew Cagney
a72f8fb439 Clean up more tracing. 
FIX interrupt delivery - was zapping PSW before it had been saved.
FIX interrupt return, was one instruction out.
 1997-09-17 08:14:23 +00:00
Andrew Cagney
6aead89a5f Fix tracing for: "ctret", "bsw", "hsw" 
Fix bugs in: "bsh", "callt", "stsr".
 1997-09-17 05:31:00 +00:00
Andrew Cagney
fb1fd47514 Smooth some of ALU tracing's rough edges. 
Fix switch insn.
 1997-09-16 14:00:15 +00:00
Andrew Cagney
c7db488f71 Restrict ldsr (load system register) to modifying just non-reserved PSW bits. 
For v850eq, include PSW[US] in bits that can be modified.
 1997-09-16 04:49:24 +00:00
Andrew Cagney
721478d51b Add v850e version of breakpoint instruction. 1997-09-16 02:15:55 +00:00
Andrew Cagney
4dda50b052 For instructions moved into v850.igen was computing (wrong) NIA when 
this wasn't needed.
 1997-09-15 23:09:26 +00:00
Andrew Cagney
bda6163995 Fix sanitization for v850 V v850e V v850eq 1997-09-15 14:42:51 +00:00
Andrew Cagney
658303f7d4 For v850eq start up with US bit set. 
Let sim_analyze_program determine the architecture.
Fix various sanitizations.
 1997-09-15 08:18:20 +00:00
Andrew Cagney
410230cf6d Check reserved bits before executing instructions. 
Make v850[eq] the the default simulator.
Report illegal instructions.
Include v850e instructions in v850eq.
 1997-09-12 05:56:38 +00:00
Andrew Cagney
5d37a07bc5 Add multi-sim support to v850/v850e/v850eq simulators. 1997-09-08 17:42:48 +00:00