Commit graph

2926 commits

Author SHA1 Message Date
Jan Beulich
248feb2f9e x86-64/MPX: relax no-RIP-relative-addressing testcase
... for COFF targets.
2016-07-01 11:17:30 +02:00
Jan Beulich
8178be5b0c x86-64/MPX: bndmk, bndldx, and bndstx don't allow RIP-relative addressing
Additionally warn about scaling factors other than 1 for the latter
two, as those get ignored by the hardware.
2016-07-01 09:07:15 +02:00
Jan Beulich
327e8c421b x86/MPX: fix address size handling
While address overrides are ignored in 64-bit mode (and hence shouldn't
really result in an error, but upon v1 converting this to a warning I
was told otherwise), trying to use 16-bit addressing is documented to
result in #UD, and hence the assembler should reject the attempt. (The
added test case at once also checks that bndc{l,n,u} won't accept
16-bit register operands.)
2016-07-01 09:06:16 +02:00
Jan Beulich
83b16ac694 x86/Intel: don't accept bogus instructions
... due to their last byte looking like a suffix, when after its
stripping a matching instruction can be found. Since memory operand
size specifiers in Intel mode get converted into suffix representation
internally, we need to keep track of the actual mnemonic suffix which
may have got trimmed off, and check its validity while looking for a
matching template. I tripper over this quite some time again after
support for AMD's SSE5 instructions got removed, as at that point some
of the SSE5 mnemonics, other than expected, didn't fail to assemble.
But the problem affects many more instructions, namely (almost) all
MMX, SSE, and AVX ones as it looks. I don't think it makes sense to
add a testcase covering all of them, nor do I think it makes sense to
pick out some random examples for a new test case.
2016-07-01 09:03:02 +02:00
Jan Beulich
c07315e0c6 x86: allow suffix-less movzw and 64-bit movzb
... just like is already the case for 16- and 32-bit movzb: I can't see
why omitting suffixes on this (and movs{b,w,l}) is not allowed, when it
is allowed for all other instructions where the suffix is redundant
with (one of) the operands.
2016-07-01 09:01:41 +02:00
Jan Beulich
8325cc6398 x86/Intel: fix operand checking for MOVSD
The dual purpose mnemonic (string move vs scalar double move) breaks
the assumption that the isstring flag would be set on both the first
and last entry in the current set of templates, which results in bogus
or missing diagnostics for the string move variant of the mnemonic.
Short of mostly rewriting i386_index_check() and its interaction with
the rest of the code, simply shrink the template set to just string
instructions when encountering the second memory operand, and run
i386_index_check() a second time for the first memory operand after
that reduction.
2016-07-01 08:56:13 +02:00
Matthew Fortune
99e7978bd2 MIPS16/GAS: Fix delay slot filling across frags
Fix an assertion failure like:

test.s: Assembler messages:
test.s:3: Internal error!
Assertion failure in append_insn at .../gas/config/tc-mips.c:7523.
Please report this bug.

triggered by assembling MIPS16 code like:

hello:
	addiu	$4, $4, 4
	jr	$31

with the generation of a listing file enabled, e.g.:

$ as -mips16 -O2 -aln=test.lst

The cause of the problem is the lack of support for moving instructions
across frags in MIPS16 jump swapping, which triggers more easily with
listing enabled as in that case every instruction gets placed in its own
frag.  It would trigger even with listing disabled though if the
instruction to swap a MIPS16 jump with was unfortunately enough placed
as last in a frag that became full.

This scenario is already handled correctly with branch swapping in
regular MIPS and microMIPS code, so reuse it for MIPS16 code as well,
and now that all MIPS16 handling has become the same as the regular MIPS
and microMIPS cases remove MIPS16 special casing altogether.

This effectively complements:

commit 464ab0e55a
Author: Maciej W. Rozycki <macro@linux-mips.org>
Date:   Mon Aug 6 20:33:00 2012 +0000

<https://sourceware.org/ml/binutils/2012-08/msg00043.html>, ("MIPS/GAS:
Correct microMIPS branch swapping assertion") for the MIPS16 case.

The assertion itself was introduced with:

commit 1e91584932
Author: Richard Sandiford <rdsandiford@googlemail.com>
Date:   Wed Mar 9 09:17:02 2005 +0000

<https://sourceware.org/ml/binutils/2005-03/msg00217.html>, ("Rework
MIPS nop-insertion code, add -mfix-vr4130 [5/11]"), but its introduction
merely noted our existing lack of support for MIPS16 jump swapping
across frags.

	gas/
	* config/tc-mips.c (append_insn) <APPEND_SWAP>: Do not special
	case MIPS16 handling.
	* testsuite/gas/mips/branch-swap-3.d: New test.
	* testsuite/gas/mips/branch-swap-4.d: New test.
	* testsuite/gas/mips/mips16@branch-swap-3.d: New test.
	* testsuite/gas/mips/mips16@branch-swap-4.d: New test.
	* testsuite/gas/mips/micromips@branch-swap-3.d: New test.
	* testsuite/gas/mips/micromips@branch-swap-4.d: New test.
	* testsuite/gas/mips/branch-swap-3.s: New test source.
	* testsuite/gas/mips/mips.exp: Run the new tests.
2016-06-30 15:11:23 +01:00
Maciej W. Rozycki
93a24ba79b PR gas/20312: Do not pad sections to alignment on failed assembly
Correct a regression from commit 85024cd8bc ("Run write_object_file
after errors") causing unsuccessful assembly, which may be due to any
reason, such as supplying a valid source like this:

	.text
	.byte	0
	.err

to terminate with an assertion failure like:

test.s: Assembler messages:
test.s:3: Error: .err encountered
../as-new: BFD (GNU Binutils) 2.24.51.20140628 internal error, aborting at .../gas/write.c line 608 in size_seg
../as-new: Please report this bug.

on targets whose default text section alignment is above 0, typically
RISC machines.

This is due to an attempt to set last text section's frag alignment to
0, requested from `subsegs_finish_section' where `frag_align_code
(alignment, 0)' is called with `alignment' set to 0 rather than the
section alignment if `had_errors' has returned true.  The call to
`subsegs_finish_section' is made from `subsegs_finish' from
`write_object_file' at unsuccessful completion, which previously wasn't
made.

Always set last section's frag alignment from the section alignment
then, forcing no section padding instead if completing unsuccessfully,
so that in that case alignment padding is still suppressed from any
listing generated, fixing assertion failures for these targets:

alpha-linuxecoff  -FAIL: all pr20312
arm-aout  -FAIL: all pr20312
mips-freebsd  -FAIL: all pr20312
mips-img-linux  -FAIL: all pr20312
mips-linux  -FAIL: all pr20312
mips-mti-linux  -FAIL: all pr20312
mips-netbsd  -FAIL: all pr20312
mips-sgi-irix5  -FAIL: all pr20312
mips-sgi-irix6  -FAIL: all pr20312
mips-vxworks  -FAIL: all pr20312
mips64-freebsd  -FAIL: all pr20312
mips64-img-linux  -FAIL: all pr20312
mips64-linux  -FAIL: all pr20312
mips64-mti-linux  -FAIL: all pr20312
mips64-openbsd  -FAIL: all pr20312
mips64el-freebsd  -FAIL: all pr20312
mips64el-img-linux  -FAIL: all pr20312
mips64el-linux  -FAIL: all pr20312
mips64el-mti-linux  -FAIL: all pr20312
mips64el-openbsd  -FAIL: all pr20312
mipsel-freebsd  -FAIL: all pr20312
mipsel-img-linux  -FAIL: all pr20312
mipsel-linux  -FAIL: all pr20312
mipsel-mti-linux  -FAIL: all pr20312
mipsel-netbsd  -FAIL: all pr20312
mipsel-vxworks  -FAIL: all pr20312
mipsisa32-linux  -FAIL: all pr20312
mipsisa32el-linux  -FAIL: all pr20312
mipsisa64-linux  -FAIL: all pr20312
mipsisa64el-linux  -FAIL: all pr20312
sh-pe  -FAIL: all pr20312
sparc-aout  -FAIL: all pr20312

	gas/
	PR gas/20312
	* write.c (subsegs_finish_section): Force no section padding to
	alignment on failed assembly, always set last frag's alignment
	from section.
	* testsuite/gas/all/pr20312.l: New list test.
	* testsuite/gas/all/pr20312.s: New test source.
	* testsuite/gas/all/gas.exp: Run the new test
2016-06-30 15:11:23 +01:00
Matthew Wahab
534dbe460e [ARM][GAS] ARMv8.2 should enable ARMv8.1 NEON instructions.
GAS fails to recognize march=armv8.2-a as a superset of march=armv8.1-a
when assembling NEON instructions. The patch corrects this, making
-march=armv8.2-a -mfpu=neon-fp-armv8 enable the NEON intructions
introduced with ARMv8.1-A.

include/
2016-06-30  Matthew Wahab  <matthew.wahab@arm.com>

	* opcode/arm.h (ARM_ARCH_V8_2a): Add FPU_NEON_EXT_RDMA to the set
	of enabled FPU features.

gas/
2016-06-30  Matthew Wahab  <matthew.wahab@arm.com>

	* testsuite/gas/arm/armv8_2+rdma.d: New.
2016-06-30 10:46:51 +01:00
Maciej W. Rozycki
eb9bb5b4ec Use supports_gnu_unique' with the unique_symbol' and `type' tests
Complement commit a43942db49 ("LD/ELF: Unify STB_GNU_UNIQUE handling")
and use `supports_gnu_unique' with the `unique_symbol' and `type' tests,
fixing failures like:

.../binutils/testsuite/binutils-all/unique.s: Assembler messages:
.../binutils/testsuite/binutils-all/unique.s:2: Error: symbol type "gnu_unique_object" is supported only by GNU targets

ERROR: .../binutils/testsuite/binutils-all/unique.s: assembly failed
UNRESOLVED: ar unique symbol in archive
.../binutils/ar -s -r -c tmpdir/artest.a tmpdir/unique.o
Executing on host: .../binutils/ar -s -r -c tmpdir/artest.a tmpdir/unique.o   (timeout = 300)
.../binutils/ar: tmpdir/unique.o: No such file or directory

FAIL: ar unique symbol in archive

and:

.../gas/testsuite/gas/elf/type.s: Assembler messages:
.../gas/testsuite/gas/elf/type.s:30: Error: symbol type "gnu_unique_object" is supported only by GNU targets
../as-new: BFD (GNU Binutils) 2.26.51.20160628 internal error, aborting at .../gas/write.c:608 in size_seg

../as-new: Please report this bug.

.../gas/testsuite/../../binutils/readelf -s dump.o | grep "1 *\[FIONTCU\]" > dump.out
Executing on host: sh -c {.../gas/testsuite/../../binutils/readelf -s dump.o >readelf.out 2>gas.stderr}  /dev/null  (timeout = 300)
readelf: Error: dump.o: Failed to read file's magic number
FAIL: elf type list

on MIPS/FreeBSD targets:

mips-freebsd  -FAIL: ar unique symbol in archive
mips-freebsd  -FAIL: elf type list
mips64-freebsd  -FAIL: ar unique symbol in archive
mips64-freebsd  -FAIL: elf type list
mips64el-freebsd  -FAIL: ar unique symbol in archive
mips64el-freebsd  -FAIL: elf type list
mipsel-freebsd  -FAIL: ar unique symbol in archive
mipsel-freebsd  -FAIL: elf type list

	binutils/
	* testsuite/binutils-all/ar.exp: Use `supports_gnu_unique' with
	the `unique_symbol' test.

	gas/
	* testsuite/gas/elf/elf.exp: Use `supports_gnu_unique' with the
	`type' test.
2016-06-28 13:54:00 +01:00
Alan Modra
d48796b505 Fix new testcase for hppa64
Anything in first column is a label on hppa64.

	PR gas/20247
	* testsuite/gas/elf/section11.s: Don't start directives in first column.
2016-06-28 19:09:11 +09:30
Richard Sandiford
dab26bf4e7 [AArch64] Make register indices be full 64-bit values
aarch64_opnd_info used bitfields to hold vector element indices,
but values were stored into those bitfields before their ranges had
been checked.  This meant large invalid indices could be silently
truncated to smaller valid indices.

The two obvious fixes were to do the range checking earlier or use
a full 64-bit field for the index.  I went for the latter for two
reasons:

      - Doing the range checking in operand_general_constraint_met_p
        seems structurally cleaner than doing it while parsing.

      - The bitfields didn't really buy us anything.  The imm field
        of the union is already 128 bits, so we can use a full int64_t
        index without growing the structure.

The patch also adds missing range checks for the elements in a register
list index.

include/
	* opcode/aarch64.h (aarch64_opnd_info): Change index fields to int64_t.

opcodes/
	* aarch64-opc.c (operand_general_constraint_met_p): Check the
	range of ldst_elemlist operands.
	(print_register_list): Use PRIi64 to print the index.
	(aarch64_print_operand): Likewise.

gas/
	* testsuite/gas/aarch64/diagnostic.s,
	testsuite/gas/aarch64/diagnostic.l: Add tests for out-of-range indices.
2016-06-28 09:21:04 +01:00
Maciej W. Rozycki
c9775dde32 MIPS16: Add R_MIPS16_PC16_S1 branch relocation support
For R_MIPS16_PC16_S1 the calculation is `(sign_extend(A) + S - P) >> 1'
and the usual MIPS16 bit shuffling applies to relocated field handling,
as per the encoding of the branch target in the extended form of the
MIPS16 B, BEQZ, BNEZ, BTEQZ and BTNEZ instructions.

	include/
	* elf/mips.h (R_MIPS16_PC16_S1): New relocation.

	bfd/
	* elf32-mips.c (elf_mips16_howto_table_rel): Add
	R_MIPS16_PC16_S1.
	(mips16_reloc_map): Likewise.
	* elf64-mips.c (mips16_elf64_howto_table_rel): Likewise.
	(mips16_elf64_howto_table_rela): Likewise.
	(mips16_reloc_map): Likewise.
	* elfn32-mips.c (elf_mips16_howto_table_rel): Likewise.
	(elf_mips16_howto_table_rela): Likewise.
	(mips16_reloc_map): Likewise.
	* elfxx-mips.c (mips16_branch_reloc_p): New function.
	(mips16_reloc_p): Handle R_MIPS16_PC16_S1.
	(b_reloc_p): Likewise.
	(mips_elf_calculate_relocation): Likewise.
	(_bfd_mips_elf_check_relocs): Likewise.
	* reloc.c (BFD_RELOC_MIPS16_16_PCREL_S1): New relocation.
	* bfd-in2.h: Regenerate.
	* libbfd.h: Regenerate.

	gas/
	* config/tc-mips.c (mips16_reloc_p): Handle
	BFD_RELOC_MIPS16_16_PCREL_S1.
	(b_reloc_p): Likewise.
	(limited_pcrel_reloc_p): Likewise.
	(md_pcrel_from): Likewise.
	(md_apply_fix): Likewise.
	(tc_gen_reloc): Likewise.
	(md_convert_frag): Likewise.
	(mips_fix_adjustable): Update comment.
	* testsuite/gas/mips/mips16-branch-reloc-2.d: Remove error
	output, add dump patterns.
	* testsuite/gas/mips/mips16-branch-reloc-3.d: Remove error
	output, add dump patterns.
	* testsuite/gas/mips/mips16-branch-addend-2.d: Remove error
	output, add dump patterns.
	* testsuite/gas/mips/mips16-branch-addend-3.d: Remove error
	output, add dump patterns.
	* testsuite/gas/mips/mips16-branch-absolute.d: Remove error
	output, add dump patterns.
	* testsuite/gas/mips/mips16-branch-reloc-2.l: Remove file.
	* testsuite/gas/mips/mips16-branch-reloc-3.l: Remove file.
	* testsuite/gas/mips/mips16-branch-addend-2.l: Remove file.
	* testsuite/gas/mips/mips16-branch-addend-3.l: Remove file.
	* testsuite/gas/mips/mips16-branch-absolute.l: Remove file.
	* testsuite/gas/mips/mips16-branch-addend-2.s: Add padding.
	* testsuite/gas/mips/branch-weak.s: Adjust alignment, avoid
	implicit instruction padding, avoid MIPS16 JR->JRC conversion.
	* testsuite/gas/mips/branch-weak-6.d: New test.
	* testsuite/gas/mips/branch-weak-7.d: New test.
	* testsuite/gas/mips/mips.exp: Run the new tests.

	ld/
	* testsuite/ld-mips-elf/mips16-branch-2.d: New test.
	* testsuite/ld-mips-elf/mips16-branch-3.d: New test.
	* testsuite/ld-mips-elf/mips16-branch-addend-2.d: New test.
	* testsuite/ld-mips-elf/mips16-branch-addend-3.d: New test.
	* testsuite/ld-mips-elf/mips16-branch.s: New test source.
	* testsuite/ld-mips-elf/mips-elf.exp: Run the new tests.
2016-06-28 01:29:56 +01:00
Vineet Gupta
45a54ee577 Make the kernel dwarf stack unwinder work for ARC targets.
* config//tc-arc.c (tc_arc_frame_initial_instructions): Use
	cfi_add_CFA_def_cfa to generate default CFA with offset
	* testsuite/gas/cfi/cfi-arc-1.d: Update expected output.
2016-06-27 16:50:29 +01:00
Nick Clifton
2edb36e77f Add command line option to stop the assembler from padding the end of sections to their alignment boundary.
PR gas/20247
	* as.h (do_not_pad_sections_to_alignment): New global variable.
	* as.c (show_usage): Add --no-pad-sections.
	(parse_args): Likewise.
	* write.c (size_seg): Skip padding the end of the section if
	requested from the command line.
	(SUB_SEGMENT_ALIGN): Likewise.
	* doc/as.texinfo: Document the new option.
	* NEWS: Mention the new feature.
	* testsuite/gas/elf/section11.s: New test.
	* testsuite/gas/elf/section11.d: New test driver.
	* testsuite/gas/elf/elf.exp: Run the new test.
2016-06-27 13:51:06 +01:00
Maciej W. Rozycki
88a7ef1689 MIPS16/GAS: Restore unsupported relocation diagnostics
Correct a MIPS16 relocation handling regression in GAS introduced with:

commit 177b4a6ad0
Author: Alexandre Oliva <aoliva@redhat.com>
Date:   Mon Mar 18 18:56:18 2002 +0000

discussed at <https://sourceware.org/ml/binutils/2002-03/msg00345.html>,
which removed a preparatory call to `mips16_extended_frag' previously
made from `md_estimate_size_before_relax'.  As a result the function is
never called with its `sec' parameter non-NULL and consequently all the
unsupported relocation checks within are dead and never trigger, causing
any unhandled relocations to silently resolve to 0.  Unfortunately there
was no sufficient test suite coverage back then to catch this.

Remove all dead code then, and all the associated comments.  Update the
remaining call to `mips16_extended_frag' from `mips_relax_frag' to pass
the relocation section as the `sec' parameter and use it to mark frags
which require an external relocation, as extended.  Finally handle any
outstanding MIPS16 relocations in `md_convert_frag' and report an error
since we don't support any except with percent operators.

	gas/
	* config/tc-mips.c (append_insn): Use any `O_symbol' expression
	unchanged with relaxed MIPS16 instructions.
	(mips16_extended_frag): Adjust accordingly.  Return 1 right
	away if a relocation will be required for the symbol requested.
	Remove dead first relaxation pass code.
	(mips_relax_frag): Pass `sec' down to `mips16_extended_frag'.
	(md_convert_frag): Adjust symbol value calculation.  Raise an
	error if a relocation is required for the symbol requested.
	* testsuite/gas/mips/mips16@relax-swap3.d: Remove dump patterns,
	add error output.
	* testsuite/gas/mips/mips16@relax-swap3.l: New error output.
	* testsuite/gas/mips/mips16-pcrel-relax-0.d: New test.
	* testsuite/gas/mips/mips16-pcrel-relax-1.d: New test.
	* testsuite/gas/mips/mips16-pcrel-relax-2.d: New test.
	* testsuite/gas/mips/mips16-pcrel-relax-3.d: New test.
	* testsuite/gas/mips/mips16-pcrel-reloc-0.d: New test.
	* testsuite/gas/mips/mips16-pcrel-reloc-1.d: New test.
	* testsuite/gas/mips/mips16-pcrel-reloc-2.d: New test.
	* testsuite/gas/mips/mips16-pcrel-reloc-3.d: New test.
	* testsuite/gas/mips/mips16-pcrel-reloc-4.d: New test.
	* testsuite/gas/mips/mips16-pcrel-reloc-5.d: New test.
	* testsuite/gas/mips/mips16-pcrel-reloc-6.d: New test.
	* testsuite/gas/mips/mips16-pcrel-reloc-7.d: New test.
	* testsuite/gas/mips/mips16-pcrel-addend-0.d: New test.
	* testsuite/gas/mips/mips16-pcrel-addend-1.d: New test.
	* testsuite/gas/mips/mips16-pcrel-addend-2.d: New test.
	* testsuite/gas/mips/mips16-pcrel-addend-3.d: New test.
	* testsuite/gas/mips/mips16-pcrel-absolute.d: New test.
	* testsuite/gas/mips/mips16-branch-reloc-0.d: New test.
	* testsuite/gas/mips/mips16-branch-reloc-1.d: New test.
	* testsuite/gas/mips/mips16-branch-reloc-2.d: New test.
	* testsuite/gas/mips/mips16-branch-reloc-3.d: New test.
	* testsuite/gas/mips/mips16-branch-addend-0.d: New test.
	* testsuite/gas/mips/mips16-branch-addend-1.d: New test.
	* testsuite/gas/mips/mips16-branch-addend-2.d: New test.
	* testsuite/gas/mips/mips16-branch-addend-3.d: New test.
	* testsuite/gas/mips/mips16-branch-absolute.d: New test.
	* testsuite/gas/mips/mips16-absolute-reloc-0.d: New test.
	* testsuite/gas/mips/mips16-absolute-reloc-1.d: New test.
	* testsuite/gas/mips/mips16-absolute-reloc-2.d: New test.
	* testsuite/gas/mips/mips16-absolute-reloc-3.d: New test.
	* testsuite/gas/mips/mips16-pcrel-reloc-2.l: New error output.
	* testsuite/gas/mips/mips16-pcrel-reloc-3.l: New error output.
	* testsuite/gas/mips/mips16-pcrel-reloc-6.l: New error output.
	* testsuite/gas/mips/mips16-pcrel-reloc-7.l: New error output.
	* testsuite/gas/mips/mips16-pcrel-addend-2.l: New error output.
	* testsuite/gas/mips/mips16-pcrel-addend-3.l: New error output.
	* testsuite/gas/mips/mips16-pcrel-absolute.l: New error output.
	* testsuite/gas/mips/mips16-branch-reloc-2.l: New error output.
	* testsuite/gas/mips/mips16-branch-reloc-3.l: New error output.
	* testsuite/gas/mips/mips16-branch-addend-2.l: New error output.
	* testsuite/gas/mips/mips16-branch-addend-3.l: New error output.
	* testsuite/gas/mips/mips16-branch-absolute.l: New error output.
	* testsuite/gas/mips/mips16-absolute-reloc-2.l: New error output.
	* testsuite/gas/mips/mips16-absolute-reloc-3.l: New error output.
	* testsuite/gas/mips/mips16-pcrel-relax-0.s: New test source.
	* testsuite/gas/mips/mips16-pcrel-relax-2.s: New test source.
	* testsuite/gas/mips/mips16-pcrel-reloc-0.s: New test source.
	* testsuite/gas/mips/mips16-pcrel-reloc-1.s: New test source.
	* testsuite/gas/mips/mips16-pcrel-reloc-2.s: New test source.
	* testsuite/gas/mips/mips16-pcrel-reloc-3.s: New test source.
	* testsuite/gas/mips/mips16-pcrel-reloc-4.s: New test source.
	* testsuite/gas/mips/mips16-pcrel-reloc-5.s: New test source.
	* testsuite/gas/mips/mips16-pcrel-reloc-6.s: New test source.
	* testsuite/gas/mips/mips16-pcrel-reloc-7.s: New test source.
	* testsuite/gas/mips/mips16-pcrel-addend-0.s: New test source.
	* testsuite/gas/mips/mips16-pcrel-addend-1.s: New test source.
	* testsuite/gas/mips/mips16-pcrel-addend-2.s: New test source.
	* testsuite/gas/mips/mips16-pcrel-addend-3.s: New test source.
	* testsuite/gas/mips/mips16-pcrel-absolute.s: New test source.
	* testsuite/gas/mips/mips16-branch-reloc-0.s: New test source.
	* testsuite/gas/mips/mips16-branch-reloc-1.s: New test source.
	* testsuite/gas/mips/mips16-branch-reloc-2.s: New test source.
	* testsuite/gas/mips/mips16-branch-reloc-3.s: New test source.
	* testsuite/gas/mips/mips16-branch-addend-0.s: New test source.
	* testsuite/gas/mips/mips16-branch-addend-1.s: New test source.
	* testsuite/gas/mips/mips16-branch-addend-2.s: New test source.
	* testsuite/gas/mips/mips16-branch-addend-3.s: New test source.
	* testsuite/gas/mips/mips16-branch-absolute.s: New test source.
	* testsuite/gas/mips/mips16-absolute-reloc-0.s: New test source.
	* testsuite/gas/mips/mips16-absolute-reloc-1.s: New test source.
	* testsuite/gas/mips/mips16-absolute-reloc-2.s: New test source.
	* testsuite/gas/mips/mips16-absolute-reloc-3.s: New test source.
	* testsuite/gas/mips/mips.exp: Run the new tests.
2016-06-25 00:54:59 +01:00
Maciej W. Rozycki
0e9c5a5c99 MIPS/GAS: Keep the original microMIPS symbol reference in branch relocs
Keep original microMIPS symbols in references from branch relocations so
that the ISA bit is retained and can be verified for validity in static
link.  No need to update WRT MIPS16 symbols because we keep them all
anyway for other reasons.

	gas/
	* config/tc-mips.c (b_reloc_p): New function.
	(mips_fix_adjustable): Also keep the original microMIPS symbol
	referred from branch relocations.
	* testsuite/gas/mips/branch-local-1.d: New test.
	* testsuite/gas/mips/branch-local-n32-1.d: New test.
	* testsuite/gas/mips/branch-local-n64-1.d: New test.
	* testsuite/gas/mips/micromips@branch-misc-4-64.d: Update
	relocations.
	* testsuite/gas/mips/branch-local-1.s: New test source.
	* testsuite/gas/mips/mips.exp: Run the new cases.
2016-06-23 12:23:32 +01:00
Peter Bergner
6fd3a02da5 Add support for yet some more new ISA 3.0 instructions.
opcodes/
	* ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
	(powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
	mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
	xor3>: New mnemonics.
	<setb>: Change to a VX form instruction.
	(insert_sh6): Add support for rldixor.
	(extract_sh6): Likewise.

gas/
	* testsuite/gas/ppc/power9.d <brd, brh, brw, mffs, mffs., mffsce,
	mffscdrn, mffscdrni, mffscrn, mffscrni, mffsl, nandxor, rldixor,
	setbool, xor3>: New tests.
	* testsuite/gas/ppc/power9.s: Likewise.
2016-06-22 17:55:17 -05:00
Maciej W. Rozycki
41947d9e38 MIPS/GAS: Handle resolved R6 PC-relative relocations
Complement commit 7361da2c95 ("Add support for MIPS R6.") and fix
internal errors like:

foo.s: Assembler messages:
foo.s: Internal error!
Assertion failure in md_apply_fix at .../gas/config/tc-mips.c:15028.
Please report this bug.

triggered by resolved R6 PC-relative relocations in sources containing
R6 code fragments wrapped into ISA override blocks embedded within code
otherwise assembled for an older ISA.

	gas/
	* config/tc-mips.c (calculate_reloc) <BFD_RELOC_HI16_S_PCREL>
	<BFD_RELOC_LO16_PCREL>: New switch cases.
	(md_apply_fix) <BFD_RELOC_HI16_S_PCREL, BFD_RELOC_LO16_PCREL>:
	Move switch cases along `BFD_RELOC_MIPS_JMP'.
	<BFD_RELOC_MIPS_21_PCREL_S2, BFD_RELOC_MIPS_26_PCREL_S2>
	<BFD_RELOC_MIPS_18_PCREL_S3, BFD_RELOC_MIPS_19_PCREL_S2>: Handle
	the resolved case.
	* testsuite/gas/mips/pcrel-reloc-4.d: New test.
	* testsuite/gas/mips/pcrel-reloc-4-r6.d: New test.
	* testsuite/gas/mips/pcrel-reloc-5.d: New test.
	* testsuite/gas/mips/pcrel-reloc-5-r6.d: New test.
	* testsuite/gas/mips/pcrel-reloc-6.d: New test.
	* testsuite/gas/mips/pcrel-reloc-6.l: New list test.
	* testsuite/gas/mips/pcrel-reloc-4.s: New test source.
	* testsuite/gas/mips/pcrel-reloc-6.s: New test source.
	* testsuite/gas/mips/mips.exp: Run the new tests.
2016-06-21 23:00:20 +01:00
Maciej W. Rozycki
912815f079 MIPS/GAS: Use the module level ISA setting for R6 relaxation
Use the module level ISA setting rather than the last ISA selected with
a `.set' directive in the source file in determination as to whether to
keep PC-relative relocations and then with the original symbol referred,
for the purpose of R6 linker relaxation.

This is so that with e.g. code like this:

	b	foo
	.set	mips32r2
	...

it's the command line options or any `.module' directive that decides
how to encode any relocation for `foo' rather than the presence of `.set
mips32r2'.

	gas/
	* config/tc-mips.c (mips_force_relocation): Use `file_mips_opts'
	rather than `mips_opts' for the R6 ISA check.
	(mips_fix_adjustable): Likewise.
	* testsuite/gas/mips/pcrel-reloc-1.d: New test.
	* testsuite/gas/mips/pcrel-reloc-1-r6.d: New test.
	* testsuite/gas/mips/pcrel-reloc-2.d: New test.
	* testsuite/gas/mips/pcrel-reloc-2-r6.d: New test.
	* testsuite/gas/mips/pcrel-reloc-3.d: New test.
	* testsuite/gas/mips/pcrel-reloc-3-r6.d: New test.
	* testsuite/gas/mips/pcrel-reloc-1.s: New test source.
	* testsuite/gas/mips/mips.exp: Run the new tests.
2016-06-21 18:05:18 +01:00
Graham Markall
bdd582dbf1 Arc assembler: Convert nps400 from a machine type to an extension.
gas	* config/tc-arc.c (check_cpu_feature, md_parse_option):
	Add nps400 option and feature. Add check for nps400
	feature. Refactor existing checks to check subclass before
	feature enablement.
	(md_show_usage): Document flags for NPS-400 and add some other
	undocumented flags.
	(cpu_type): Remove nps400 CPU type entry
	(check_zol): Remove bfd_mach_arc_nps400 case.
	(md_show_usage): Add help on -mcpu=nps400.
	(cpu_types): Add entry for nps400 as arc700 plus nps400 extension
	set.
	* doc/c-arc.texi: Document the -mnps400, -mspfp, -mdpfp, and
	-fpuda flags.  Document -mcpu=nps400.
	* testsuite/gas/arc/nps-400-0.d: Use -mcpu=arc700 -mnps400. Change
	expected flags to match ARC700 instead of NPS400.
	* testsuite/gas/arc/nps-400-1.d: Use -mcpu=arc700 -mnps400.
	* testsuite/gas/arc/nps-400-2.d: Likewise.
	* testsuite/gas/arc/nps-400-3.d: Likewise.
	* testsuite/gas/arc/nps-400-4.d: Likewise.
	* testsuite/gas/arc/nps-400-5.d: Likewise.
	* testsuite/gas/arc/nps-400-6.d: Likewise.
	* testsuite/gas/arc/nps-400-7.d: Likewise.
	* testsuite/gas/arc/textinsn2op01.s: Change opcode of myinsn to
	avoid clash with cbba instruction.
	* testsuite/gas/arc/textinsn2op01.d: Likewise.
	* testsuite/gas/arc/textinsn3op.d: Likewise.
	* testsuite/gas/arc/textinsn3op.s: Likewise.
	* testsuite/gas/arc/nps-400-0.d: Test using NPS-400 using
	-mcpu=nps400 as an alternative to -mcpu=arc700 -mnps400 flags.

binutils* readelf.c (decode_ARC_machine_flags): Remove E_ARC_MACH_NPS400
	case.

ld	* testsuite/ld-arc/nps-1a.d: Use -mcpu=arc700 -mnps400.
	* testsuite/ld-arc/nps-1b.d: Likewise.

include	* opcode/arc.h: Add nps400 extension and instruction
	subclass.
	Remove ARC_OPCODE_NPS400
	* elf/arc.h: Remove E_ARC_MACH_NPS400

opcodes	* arc-dis.c (arc_insn_length): Add comment on instruction length.
	Use same method for determining	instruction length on ARC700 and
	NPS-400.
	(arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
	* arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
	with the NPS400 subclass.
	* arc-opc.c: Likewise.

bfd	* archures.c: Remove bfd_mach_arc_nps400.
	* bfd-in2.h: Likewise.
	* cpu-arc.c (arch_info_struct): Likewise.
	* elf32-arc.c (arc_elf_object_p, arc_elf_final_write_processing):
	Likewise.
2016-06-21 14:03:08 +01:00
Maciej W. Rozycki
ff03d62a82 MIPS/GAS/testsuite: Uniquely identify MIPS64r6 tests
gas/
	* testsuite/gas/mips/r6-64-n32.d: Change the `name' tag.
	* testsuite/gas/mips/r6-64-n64.d: Likewise.
2016-06-20 23:43:24 +01:00
Jose E. Marchesi
96074adc6a opcodes,gas: sparc: fix rdasr,wrasr,rdpr,wrpr,rdhpr,wrhpr insns.
This patch fixes and expands the definition of the read/write
instructions for ancillary-state, privileged and hyperprivileged
registers in opcodes.

It also adds support for three new v9m hyperprivileged registers:
%hmcdper, %hmcddfr and %hva_mask_nz.

Finally, the patch expands existing tests (and adds several new ones) in
order to cover all the read/write instructions in all its variants.

opcodes/ChangeLog:

2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* sparc-opc.c (rdasr): New macro.
	(wrasr): Likewise.
	(rdpr): Likewise.
	(wrpr): Likewise.
	(rdhpr): Likewise.
	(wrhpr): Likewise.
	(sparc_opcodes): Use the macros above to fix and expand the
	definition of read/write instructions from/to
	asr/privileged/hyperprivileged instructions.
	* sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
	%hva_mask_nz.  Prefer softint_set and softint_clear over
	set_softint and clear_softint.
	(print_insn_sparc): Support %ver in Rd.

gas/ChangeLog:

2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* config/tc-sparc.c (hpriv_reg_table): Add registers %hmcdper,
	%hmcddfr and %hva_mask_nz.
	(sparc_ip): New handling of asr/privileged/hyperprivileged
	registers, adapted to the new form of the sparc opcodes table.
	* testsuite/gas/sparc/rdasr.s: New file.
	* testsuite/gas/sparc/rdasr.d: Likewise.
	* testsuite/gas/sparc/wrasr.s: Likewise.
	* testsuite/gas/sparc/wrasr.d: Likewise.
	* testsuite/gas/sparc/sparc.exp (sparc_elf_setup): Add rdasr and
	wrasr tests.
	* testsuite/gas/sparc/rdpr.d: Use -Av9m, as some privileged
	registers require it.
	* testsuite/gas/sparc/wrpr.s: Complete to cover all privileged
	registers and write instruction modalities.
	* testsuite/gas/sparc/wrpr.d: Likewise.
	* testsuite/gas/sparc/rdhpr.s: Likewise for hyperprivileged
	registers.
	* testsuite/gas/sparc/rdhpr.d: Likewise.
	* testsuite/gas/sparc/wrhpr.s: Likewise.
	* testsuite/gas/sparc/wrhpr.d: Likewise.
2016-06-17 02:15:43 -07:00
Jose E. Marchesi
7a10c22feb opcodes,gas: adjust sparc insns and make GAS aware of it
This patch marks the SPARC instructions in the opcodes table with their
proper opcode architectures, and makes the assembler aware of them.
This allows the assembler to properly realize when a new instruction
needs a higher architecture (after v9b) and to react accordingly
emitting an error message or bumping the architecture.

It also expands architecture mismatch tests to cover architectures
higher than v9b, and fixes a couple of minor bugs in the GAS testsuite.

opcodes/ChangeLog:

2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* sparc-opc.c (sparc_opcodes): Adjust instructions opcode
	architecture according to the hardware capabilities they require.
	(sparc_priv_regs): New table.
	(sparc_hpriv_regs): Likewise.
	(sparc_asr_regs): Likewise.
	(v9anotv9m): Define.

gas/ChangeLog:

2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* config/tc-sparc.c (sparc_arch_table): adjust the GAS
	architectures to use the right opcode architecture.
	(sparc_md_end): Handle v9{c,d,e,v,m}.
	(sparc_ip): Fix some comments.
	* testsuite/gas/sparc/ldx_efsr.d: Fix the architecture of this
	instruction, which is v9d.
	* testsuite/gas/sparc/mwait.s: Remove the `rd %mwait,%g1'
	instruction from the test, as %mwait is not readable.
	* testsuite/gas/sparc/mwait.d: Likewise.
	* testsuite/gas/sparc/mism-1.s: Expand to check v9b and v9e
	mismatch architecture errors.
	* testsuite/gas/sparc/mism-2.s: New file.
2016-06-17 02:14:18 -07:00
Nick Clifton
3ee6e4fbec Fix simple gas testsuite failures.
binutils* readelf.c (is_24bit_abs_reloc): Add support for R_FT32_20
	reloc.

gas	* config/tc-ft32.c (md_assemble): Call dwarf2_emit_insn with the
	instruction size.
	* config/tc-mcore.c (md_assemble): Likewise.
	* config/tc-mn10200.c (md_assemble): Likewise.
	* config/tc-moxie.c (md_assemble): Likewise.
	* config/tc-pj.c (md_apply_fix): Handle BFD_RELOC_PJ_CODE_REL32.
	* testsuite/gas/all/gas.exp (diff1 test): Alpha sort list of
	exception targets.  Add alpha, hppa, microblaze and rl78 to list
	of exceptions.
	(forward): Add microblaze to list of exceptions.
	(fwdexp): Add alpha to list of exceptions.
	(redef2): Add arm-epoc-pe and rl78 to list of exceptions.
	(redef3): Add rl78 and x86_64 cygwin to list of exceptions.
	(do_930509a): Alpha sort list of exception targets.  Add h8300 and
	mn10200 to list of exceptions.
	(align2): Expect to fail for nds32.
	(cond): Add alpha and rl78 to list of exceptions.
	* testsuite/gas/all/none.d: Skip for ft32 and hppa.
	* testsuite/gas/all/string.d: Skip for tic4x.
	* testsuite/gas/alpha/alpha.exp: Note that the alpha-linuxecoff
	target does not support ELF.
	* testsuite/gas/arm/blx-bl-convert.dL Skip for the nto target.
	* testsuite/gas/cfi/cfi-alpha-2.d: All extended format names.
	* testsuite/gas/cfi/cfi.exp: Alpha sort list of targets.  Skip SH
	tests for sh-pe and sh-rtemscoff targets.
	* testsuite/gas/elf/elf.exp (redef): Add rl78, xgate and vax to
	list of exceptions.
	(type): Run the noifunc version for alpha-freebsd and visium.
	* testsuite/gas/elf/warn-2.s: Do not expect to fail on the mcore,
	mn10200 or moxie targets.
	* testsuite/gas/ft32/insn.d: Update expected disassembly.
	* testsuite/gas/i386/i386.exp (x86-64-pcrel): Skip for cygwin
	targets.
	* testsuite/gas/lns/lns.exp (lns-common-1): No longer skip for
	mcore and rx targets.
	* testsuite/gas/macros/macros.exp (dot): Add exceptions for ns32k,
	rl78 and vax.
	(purge): Expect to fail on the ns32k and vax.
	* testsuite/gas/nds32/alu-2.d: Update expected disassembly.
	* testsuite/gas/nds32/ls.d: Likewise.
	* testsuite/gas/nds32/sys-reg.d: Likewise.
	* testsuite/gas/nds32/usr-spe-reg.d: Likewise.
	* testsuite/gas/pe/aligncomm-d.d: Skip for the sh.
	* testsuite/gas/pe/section-align-3.d: Likewise.
	* testsuite/gas/pe/section-exclude.d: Likewise.
	* testsuite/gas/ppc/test2xcoff32.d: Pass once all the required
	data has been seen.
	* testsuite/gas/ppc/textalign-xcoff-001.d: Fix up regexp to allow
	for variations in whitespace.
	* testsuite/gas/tilepro/t_constants.d: Pass once all the required
	data has been seen.
	* testsuite/gas/tilepro/t_constants.s (.safe_word): New macro.
	Installs a 32-bit value without generating warnings on 64-bit
	hosts.
	Use the new macro to replace the .word directives.

opcodes	* nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
	constants to match expected behaviour.
	(nds32_parse_opcode): Likewise.  Also for whitespace.
2016-06-15 16:25:34 +01:00
Andrew Burgess
02f3be19f6 opcodes/arc: Fix extract for some add_s instructions
The extract function used for some arc_s instructions was not
implemented, and instead always returned 0.  Fixed in this commit.

opcodes/ChangeLog:

	* arc-opc.c (extract_rhv1): Extract value from insn.

gas/ChangeLog:

	* testsuite/gas/arc/add_s.d: New file.
	* testsuite/gas/arc/add_s.s: New file.
2016-06-15 09:01:48 +01:00
Graham Markall
28215275a6 [ARC] Add ldbit for nps
This commit adds the ldbit instruction for the NPS-400. The ldbit
instruction uses the same encoding as the ld instruction, but sets
the ZZ field to 11 (which is a reserved setting), and sets the AA
field to 1 or 2 for the x2 and x4 flags respectively.
2016-06-14 16:21:44 +01:00
Graham Markall
9ba75c8847 [ARC] Add deep packet inspection instructions for nps
With the exception of ldbit, this commit adds implementations of
all DPI instructions for the NPS-400. These instructions are:

- hash / hash.p[0-3]
- tr
- utf8
- e4by
- addf
2016-06-14 16:21:44 +01:00
Graham Markall
14053c1903 [ARC] Add arithmetic and logic instructions for nps
This commit completes the implementation of arithmetic and logic
instructions for the NPS-400. These instructions are:

- calcbsd / calcbxd
- calckey / calcxkey
- mxb / imxb
- addl, subl, orl, andl, xorl
- andab / orab
- lbdsize
- bdlen
- csms, csma, cbba
- zncv
- hofs
2016-06-14 16:21:44 +01:00
Maciej W. Rozycki
97f5015122 MIPS/GAS: Don't convert RELA JALR relocations on R6
Revert an inadvertent change to make RELA JALR relocations
section-relative on MIPS R6 targets made with commit 7361da2c95 ("Add
support for MIPS R6.").  There is no need to make this a special case
and the comment introduced with the said change clearly indicates this
was not intended.

	gas/
	* config/tc-mips.c (mips_fix_adjustable): Don't convert RELA
	JALR relocations on R6.
	* testsuite/gas/mips/jal-svr4pic-local.d: New test.
	* testsuite/gas/mips/mips1@jal-svr4pic-local.d: New test.
	* testsuite/gas/mips/r3000@jal-svr4pic-local.d: New test.
	* testsuite/gas/mips/micromips@jal-svr4pic-local.d: New test.
	* testsuite/gas/mips/jal-svr4pic-local-n32.d: New test.
	* testsuite/gas/mips/micromips@jal-svr4pic-local-n32.d: New
	test.
	* testsuite/gas/mips/jal-svr4pic-local-n64.d: New test.
	* testsuite/gas/mips/micromips@jal-svr4pic-local-n64.d: New
	test.
	* testsuite/gas/mips/jal-svr4pic-local.s: New test source.
	* testsuite/gas/mips/jal-svr4pic-local-newabi.s: New test
	source.
	* testsuite/gas/mips/mips.exp: Run the new tests.
2016-06-13 17:02:22 +01:00
Nick Clifton
69c9e028b6 Fix compile time warning messages building with gcc v6.1.1
etc	* texi2pod.pl: Escape curly braces, whilst searching for keyword
	strong.

gas	* config/tc-arm.c: For non-ELF based targets skip ARM feature sets
	that are not supported.

	* config/tc-arc.c (md_apply_fix): Avoid left shifting a signed
	constant.
	* config/tc-cr16.c (check_range): Likewise.
	* config/tc-nios2.c (nios2_check_overflow): Likewise.
2016-06-13 10:49:26 +01:00
Matthew Wahab
4d1464f294 [ARM] Add command line option for RAS extension.
This patch adds the architecture extension "+ras" to enable RAS
support. It is enabled by default for -march=armv8.2-a and available but
disabled by default for armv8-a and armv8.1-a.

gas/
	* config/tc-arm.c (arm_ext_v8_2): Rename to arm_ext_ras.
	(arm_ext_ras): Renamed from arm_ext_v8_2.
	(insns): Update for arm_ext_v8_2 renaming.
	(arm_extensions): Add "ras".
	* doc/c-arm.texi (ARM Options): Add an entry for "ras".
	* testsuite/gas/arm/armv8-a+ras.d: New.
	* testsuite/gas/arm/armv8_2-a.d: Add explicit command line
	options.

include/
	* opcode/arm.h (ARM_EXT2_RAS): New.  Also align preceding
	entries.
	(ARM_AEXT_V8_2A): Add ARM_EXT2_RAS.

opcodes/
	* arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
	ARM_EXT_RAS in relevant entries.
2016-06-07 09:56:42 +01:00
Peter Bergner
026122a670 Re-add support for lbarx, lharx, stbcx. and sthcx. insns back to the E6500 cpu.
opcodes/
	PR binutils/20196
	* ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
	opcodes for E6500.

gas/
	PR binutils/20196
	* gas/testsuite/gas/ppc/e6500.s <lbarx, lharx, lwarx, ldarx,
	stbcx., sthcx., stwcx., stdcx.>: Add tests.
	* gas/testsuite/gas/ppc/e6500.d: Likewise.
	* gas/testsuite/gas/ppc/power8.s: Likewise.
	* gas/testsuite/gas/ppc/power8.d: Likewise.
	* gas/testsuite/gas/ppc/power4.s <lwarx, ldarx, stwcx.,
	stdcx.>: Add tests.
	* gas/testsuite/gas/ppc/power4.d: Likewise.
2016-06-03 18:38:02 -05:00
H.J. Lu
07f5af7d3c Handle indirect branches for AMD64 and Intel64
AMD64 spec and Intel64 spec differ in indirect branches in 64-bit mode.
AMD64 supports indirect branches with 16-bit address via the data size
prefix while the data size prefix is ignored by Intel64.

gas/

	PR binutis/18386
	* testsuite/gas/i386/i386.exp: Run x86-64-branch-4.
	* testsuite/gas/i386/x86-64-branch.d: Updated.
	* testsuite/gas/i386/ilp32/x86-64-branch.d: Likewise.
	* testsuite/gas/i386/x86-64-branch-4.l: New file.
	* testsuite/gas/i386/x86-64-branch-4.s: Likewise.

opcodes/

	PR binutis/18386
	* i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
	(indir_v_mode): New.
	Add comments for '&'.
	(reg_table): Replace "{T|}" with "{&|}" on call and jmp.
	(putop): Handle '&'.
	(intel_operand_size): Handle indir_v_mode.
	(OP_E_register): Likewise.
	* i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64.  Add
	64-bit indirect call/jmp for AMD64.
	* i386-tbl.h: Regenerated
2016-06-03 15:55:29 -07:00
Andrew Burgess
4eb6f89250 Add support for 48 and 64 bit ARC instructions.
gas	* config/tc-arc.c (parse_opcode_flags): New function.
	(find_opcode_match): Move flag parsing code out to new function.
	Ignore operands marked IGNORE.
	(build_fake_opcode_hash_entry): New function.
	(find_special_case_long_opcode): New function.
	(find_special_case): Lookup long opcodes.
	* testsuite/gas/arc/nps400-7.d: New file.
	* testsuite/gas/arc/nps400-7.s: New file.

include	* opcode/arc.h (MAX_INSN_ARGS): Increase to 16.
	(struct arc_long_opcode): New structure.
	(arc_long_opcodes): Declare.
	(arc_num_long_opcodes): Declare.

opcodes	* arc-dis.c (struct arc_operand_iterator): New structure.
	(find_format_from_table): All the old content from find_format,
	with some minor adjustments, and parameter renaming.
	(find_format_long_instructions): New function.
	(find_format): Rewritten.
	(arc_insn_length): Add LSB parameter.
	(extract_operand_value): New function.
	(operand_iterator_next): New function.
	(print_insn_arc): Use new functions to find opcode, and iterator
	over operands.
	* arc-opc.c (insert_nps_3bit_dst_short): New function.
	(extract_nps_3bit_dst_short): New function.
	(insert_nps_3bit_src2_short): New function.
	(extract_nps_3bit_src2_short): New function.
	(insert_nps_bitop1_size): New function.
	(extract_nps_bitop1_size): New function.
	(insert_nps_bitop2_size): New function.
	(extract_nps_bitop2_size): New function.
	(insert_nps_bitop_mod4_msb): New function.
	(extract_nps_bitop_mod4_msb): New function.
	(insert_nps_bitop_mod4_lsb): New function.
	(extract_nps_bitop_mod4_lsb): New function.
	(insert_nps_bitop_dst_pos3_pos4): New function.
	(extract_nps_bitop_dst_pos3_pos4): New function.
	(insert_nps_bitop_ins_ext): New function.
	(extract_nps_bitop_ins_ext): New function.
	(arc_operands): Add new operands.
	(arc_long_opcodes): New global array.
	(arc_num_long_opcodes): New global.
	* arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
2016-06-02 14:03:23 +01:00
Graham Markall
315f180f2f Add support for some variants of the ARC nps400 rflt instruction.
gas     * testsuite/gas/arc/nps-400-1.s: Add rflt variants with
        operands of types a,b,u6, 0,b,u6, and 0,b,limm.
        * testsuite/gas/arc/nps-400-1.d: Likewise.

opcodes * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
        0,b,limm to the rflt instruction.
2016-06-01 16:29:27 +01:00
H.J. Lu
144b71e2a8 Add .noavx512XX directives to x86 assembler
Add .noavx512f, .noavx512cd, .noavx512er, .noavx512pf, .noavx512dq,
.noavx512bw, .noavx512vl, .noavx512ifma, .noavx512vbmi directives to x86
assembler.

gas/

	PR gas/20145
	* config/tc-i386.c (cpu_noarch): Add noavx512f, noavx512cd,
	noavx512er, noavx512pf, noavx512dq, noavx512bw, noavx512vl,
	noavx512ifma and noavx512vbmi.
	* doc/c-i386.texi: Mention noavx512f, noavx512cd, noavx512er,
	noavx512pf, noavx512dq, noavx512bw, noavx512vl, noavx512ifma
	and noavx512vbmi.
	* testsuite/gas/i386/i386.exp: Run noavx512-1 and noavx512-2.
	* testsuite/gas/i386/noavx512-1.l: New file.
	* testsuite/gas/i386/noavx512-1.s: Likewise.
	* testsuite/gas/i386/noavx512-2.l: Likewise.
	* testsuite/gas/i386/noavx512-2.s: Likewise.

opcodes/

	PR gas/20145
	* i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
	CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
	CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
	CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
	CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
	* i386-init.h: Regenerated.
2016-05-29 07:56:23 -07:00
H.J. Lu
1848e56734 Update x86 CPU_XXX_FLAGS handling
Support defining CPU_XXX_FLAGS with other CPU_XXX_FLAGS.  Update
CPU_XXX_FLAGS to enable more bits like x87 and SYSCALL.  Don't enable
MMX when enabling SSE, AVX or AVX512.  Don't disable AVX nor AVX512 when
disabling SSE.  Don't disable AVX512 when disabling AVX.  Disable F16C,
FMA, FMA4 and XOP when disabling AVX.  Add 87, no287, no387, no687,
nosse2, nosse3, nossse3, nosse4.1, nosse4.2, nosse4 and noavx2 directives
to x86 assembler.

TODO: Add more .noXXX, like .noavx512f, directives to x86 assembler.

gas/

	PR gas/20145
	* config/tc-i386.c (cpu_arch): Add 687.
	(cpu_noarch): Add no287, no387, no687, nosse2, nosse3, nossse3,
	nosse4.1, nosse4.2, nosse4 and noavx2.
	(parse_real_register): Check cpuregmmx instead of cpummx for MMX
	register.  Check cpuregxmm instead of cpusse for XMM register.
	Check cpuregymm instead of cpuavx for YMM register.  Check
	cpuregzmm/cpuregmask instead of cpuavx512f for ZMMM/mask register.
	* doc/c-i386.texi: Mention 687, no287, no387, no687, nosse2,
	nosse3, nossse3, nosse4.1, nosse4.2, nosse4 and noavx2.
	* testsuite/gas/i386/arch-10-prefetchw.d (as): Add mmx.
	* testsuite/gas/i386/arch-10.d (as): Likewise.
	* testsuite/gas/i386/arch-11.s: Add ".arch .mmx".
	* testsuite/gas/i386/i386.exp: Pass mmx to assembler for
	arch-10-3 and arch-10-4.  Run no87-3, nosse-4, nosse-5, noavx-3
	and noavx-4.
	* testsuite/gas/i386/no87-3.l: New file.
	* testsuite/gas/i386/no87-3.s: Likewise.
	* testsuite/gas/i386/noavx-3.l: Likewise.
	* testsuite/gas/i386/noavx-3.s: Likewise.
	* testsuite/gas/i386/noavx-4.d: Likewise.
	* testsuite/gas/i386/noavx-4.s: Likewise.
	* testsuite/gas/i386/nosse-4.l: Likewise.
	* testsuite/gas/i386/nosse-4.s: Likewise.
	* testsuite/gas/i386/nosse-5.d: Likewise.
	* testsuite/gas/i386/nosse-5.s: Likewise.

opcodes/

	PR gas/20145
	* i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS.  Remove
	CpuMMX from CPU_SSE_FLAGS.  Remove AVX and AVX512 bits from
	CPU_ANY_SSE_FLAGS.  Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
	Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
	CpuXSAVEC.  Add CPU_AVX_FLAGS to CpuF16C.  Remove CpuMMX from
	CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
	CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
	Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS.   Add CPU_ANY_287_FLAGS,
	CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
	CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
	CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS.  Enable CpuRegMMX
	for MMX.  Enable CpuRegXMM for SSE, AVX and AVX512.  Enable
	CpuRegYMM for AVX and AVX512VL,  Enable CpuRegZMM and
	CpuRegMask for AVX512.
	(cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
	and CpuRegMask.
	(set_bitfield_from_cpu_flag_init): New function.
	(set_bitfield): Remove const on f.  Call
	set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
	* i386-opc.h (CpuRegMMX): New.
	(CpuRegXMM): Likewise.
	(CpuRegYMM): Likewise.
	(CpuRegZMM): Likewise.
	(CpuRegMask): Likewise.
	(i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
	and cpuregmask.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.
2016-05-27 10:05:57 -07:00
Peter Bergner
19dfcc89e8 Add support for new POWER ISA 3.0 instructions.
opcodes/

	* ppc-opc.c (CY): New define.  Document it.
	(powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.

gas/
	* testsuite/gas/ppc/altivec3.d <vmsumudm>: Add test.
	* testsuite/gas/ppc/altivec3.s: Likewise.
	* testsuite/gas/ppc/power9.d <addex[.], lwzmx, vmsumudm>: Add tests.
	* testsuite/gas/ppc/power9.s: Likewise.
2016-05-26 19:06:51 -05:00
H.J. Lu
8d5b9a5a30 Append ".p2align 4" to some x86 directive tests
Append ".p2align 4" to some x86 directive tests for explicit paddings
for section alignment to avoid implicit section alignment in assembler
listings.

	* testsuite/gas/i386/avx512vl-2.l: Append "#pass".
	* testsuite/gas/i386/noavx-1.l: Likewise.
	* testsuite/gas/i386/nommx-1.l: Likewise.
	* testsuite/gas/i386/nosse-1.l: Likewise.
	* testsuite/gas/i386/x86-64-avx512vl-2.l: Likewise.
	* testsuite/gas/i386/avx512vl-2.s: Append ".p2align 4".
	* testsuite/gas/i386/noavx-1.s: Likewise.
	* testsuite/gas/i386/nommx-1.s: Likewise.
	* testsuite/gas/i386/nosse-1.s: Likewise.
	* testsuite/gas/i386/x86-64-avx512vl-2.s: Likewise.
2016-05-26 07:55:38 -07:00
H.J. Lu
73b090a922 Require another match for AVX512VL
The AVX512VL bit alone isn't sufficient to select a 128-bit or 256-bit
AVX512 instruction.  We must match another AVX512 bit.

	PR gas/20140
	* config/tc-i386.c (cpu_flags_match): Require another match
	for AVX512VL.
	* testsuite/gas/i386/i386.exp: Run avx512vl-1, avx512vl-2,
	x86-64-avx512vl-1 and x86-64-avx512vl-2.
	* testsuite/gas/i386/avx512vl-1.l: New file.
	* testsuite/gas/i386/avx512vl-1.s: Likewise.
	* testsuite/gas/i386/avx512vl-2.l: Likewise.
	* testsuite/gas/i386/avx512vl-2.s: Likewise.
	* testsuite/gas/i386/x86-64-avx512vl-1.l: Likewise.
	* testsuite/gas/i386/x86-64-avx512vl-1.s: Likewise.
	* testsuite/gas/i386/x86-64-avx512vl-2.l: Likewise.
	* testsuite/gas/i386/x86-64-avx512vl-2.s: Likewise.
2016-05-25 15:04:47 -07:00
H.J. Lu
f1360d5830 Enable VREX for AVX512 directives
Enable VREX for AVX512 instructions with upper 16 vector registers.

gas/

	PR gas/20141
	* testsuite/gas/i386/i386.exp: Run x86-64-pr20141.
	* testsuite/gas/i386/x86-64-pr20141.d: New file.
	* testsuite/gas/i386/x86-64-pr20141.s: Likewise.

opcodes/

	PR gas/20141
	* i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
	CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
	* i386-init.h: Regenerated.
2016-05-25 10:49:25 -07:00
H.J. Lu
293f5f6543 Reimplement .no87/.nommx/.nosse/.noavx directives
Move all .noXXX directives to cpu_noarch.

gas/

	* config/tc-i386.c (arch_entry): Remove negated.
	(noarch_entry): New struct.
	(cpu_arch): Updated.  Remove .no87, .nommx, .nosse and .noavx.
	(cpu_noarch): New.
	(set_cpu_arch): Check cpu_noarch after cpu_arch.
	(md_parse_option): Allow -march=+nosse.  Check cpu_noarch after
	cpu_arch.
	(output_message): New function.
	(show_arch): Use it.  Handle cpu_noarch.
	* testsuite/gas/i386/i386.exp: Run nommx-1, nommx-2, nommx-3,
	nosse-1, nosse-2, nosse-3, noavx-1 and noavx-2.
	* testsuite/gas/i386/noavx-1.l: New file.
	* testsuite/gas/i386/noavx-1.s: Likewise.
	* testsuite/gas/i386/noavx-2.s: Likewise.
	* testsuite/gas/i386/noavx-2.l: Likewise.
	* testsuite/gas/i386/nommx-1.s: Likewise.
	* testsuite/gas/i386/nommx-1.l: Likewise.
	* testsuite/gas/i386/nommx-2.s: Likewise.
	* testsuite/gas/i386/nommx-2.l: Likewise.
	* testsuite/gas/i386/nommx-3.s: Likewise.
	* testsuite/gas/i386/nommx-3.l: Likewise.
	* testsuite/gas/i386/nosse-1.s: Likewise.
	* testsuite/gas/i386/nosse-1.l: Likewise.
	* testsuite/gas/i386/nosse-2.s: Likewise.
	* testsuite/gas/i386/nosse-2.l: Likewise.
	* testsuite/gas/i386/nosse-3.s: Likewise.
	* testsuite/gas/i386/nosse-3.l: Likewise.

opcodes/

	* i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
	CPU_ANY_X87_FLAGS.  Add CPU_ANY_MMX_FLAGS.
	* i386-init.h: Regenerated.
2016-05-25 10:26:13 -07:00
Chua Zheng Leong
934c263269 Only generate VMOV.I64 instructions for loading constant floating point values if this instruction is supported by the currently selected fpu.
PR target/2006764
	* config/tc-arm.c (move_or_literal_pool): Only generate a VMOV.I64
	instruction if supported by the currently selected fpu variant.
	* testsuite/gas/arm/vfpv3-ldr_immediate.s: Add test of this PR.
	* testsuite/gas/arm/vfpv3-ldr_immediate.d: Update expected disassembly.
2016-05-25 13:09:51 +01:00
Maciej W. Rozycki
44d3da2338 MIPS/GAS: Treat local jump relocs the same no matter if REL or RELA
Do not convert jump relocs against local MIPS16 or microMIPS symbols to
refer to a section symbol instead even on RELA targets, as it makes it
impossible for the linker to make a JAL to JALX conversion based on ISA
symbol annotation, breaking regular and compressed MIPS interlinking.

	gas/
	* config/tc-mips.c (mips_fix_adjustable): Also return 0 for
	jump relocations against MIPS16 or microMIPS symbols on RELA
	targets.
	* testsuite/gas/mips/jalx-local.d: New test.
	* testsuite/gas/mips/jalx-local-n32.d: New test.
	* testsuite/gas/mips/jalx-local-n64.d: New test.
	* testsuite/gas/mips/jalx-local.s: New test source.
	* testsuite/gas/mips/mips.exp: Run the new tests.

	ld/
	* testsuite/ld-mips-elf/jalx-local.d: New test.
	* testsuite/ld-mips-elf/jalx-local-n32.d: New test.
	* testsuite/ld-mips-elf/jalx-local-n64.d: New test.
	* testsuite/ld-mips-elf/mips-elf.exp: Run the new tests.
2016-05-24 14:11:50 +01:00
H.J. Lu
4e21640f67 Preserve addend for R_386_GOT32 and R_X86_64_GOT32
We should preserve addend for R_386_GOT32 and R_X86_64_GOT32 as in
"movl $foo@GOT + 4, %eax" and "movq $foo@GOT + 4, %rax".

	PR gas/19600
	* config/tc-i386.c (md_apply_fix): Preserve addend for
	BFD_RELOC_386_GOT32 and BFD_RELOC_X86_64_GOT32.
	* testsuite/gas/i386/addend.d: New file.
	* testsuite/gas/i386/addend.s: Likewise.
	* testsuite/gas/i386/x86-64-addend.d: Likewise.
	* testsuite/gas/i386/x86-64-addend.s: Likewise.
	* testsuite/gas/i386/i386.exp: Run addend and x86-64-addend.
	* testsuite/gas/i386/reloc32.d: Updated.
2016-05-20 06:01:28 -07:00
Maciej W. Rozycki
17c6c9d9f3 MIPS: Fix the encoding of immediates with microMIPS JALX
The microMIPS JALX instruction shares the R_MICROMIPS_26_S1 relocation
with microMIPS J/JAL/JALS instructions, however unlike the latters its
encoded immediate argument is unusually shifted left by 2 rather than 1
in calculating the value used for the operation requested.

We already handle this exception in `mips_elf_calculate_relocation' in
LD, in a scenario where JALX is produced as a result of relaxing JAL for
the purpose of making a cross-mode jump.  We also get it right in the
disassembler in `decode_micromips_operand'.

What we don't correctly do however is processing microMIPS JALX produced
by GAS from an assembly source, where a non-zero constant argument or a
symbol reference with a non-zero in-place addend has been used.  In this
case the same calculation is made as for microMIPS J/JAL/JALS, causing
the wrong encoding to be produced by GAS on making an object file, and
then again by LD in the final link.  The latter in particular causes the
calculation, where the addend fits in the relocatable field, to produce
different final addresses for the same source code depending on whether
REL or RELA relocations are used.

Correct these issues by special-casing microMIPS JALX in the places that
have been previously missed.

	bfd/
	* elfxx-mips.c (mips_elf_read_rel_addend): Adjust the addend for
	microMIPS JALX.

	gas/
	* config/tc-mips.c (append_insn): Correct the encoding of a
	constant argument for microMIPS JALX.
	(tc_gen_reloc): Correct the encoding of an in-place addend for
	microMIPS JALX.
	* testsuite/gas/mips/jalx-addend.d: New test.
	* testsuite/gas/mips/jalx-addend-n32.d: New test.
	* testsuite/gas/mips/jalx-addend-n64.d: New test.
	* testsuite/gas/mips/jalx-imm.d: New test.
	* testsuite/gas/mips/jalx-imm-n32.d: New test.
	* testsuite/gas/mips/jalx-imm-n64.d: New test.
	* testsuite/gas/mips/jalx-addend.s: New test source.
	* testsuite/gas/mips/jalx-imm.s: New test source.
	* testsuite/gas/mips/mips.exp: Run the new tests.

	ld/
	* testsuite/ld-mips-elf/jalx-addend.d: New test.
	* testsuite/ld-mips-elf/jalx-addend-n32.d: New test.
	* testsuite/ld-mips-elf/jalx-addend-n64.d: New test.
	* testsuite/ld-mips-elf/mips-elf.exp: Run the new tests.
2016-05-20 13:38:48 +01:00
Andrew Burgess
fe779266b3 gas/arc: Fix array overrun when checking opcode array
The opcode array iterator mechanism can, in some situations, result in
reading memory outside of the opcode array.  When using the
iterator-next mechanism to find the next possible arc_opcode, if we find
an opcode where the name field is NULL, or the name does not match, then
the cached opcode pointer is not set to NULL.  The result is that
another call to iterator-next will again increment the opcode
pointer (which might now point outside the opcode array) and attempt to
access the name field of this undefined opcode.

Fixed in this commit by clearing the cached opcode pointer.

I've added a test case, which currently shows the bug, however, this
will only expose this bug while the opcode used (dsp_fp_cmp) is the last
opcode in the table.

gas/ChangeLog:

	* config/tc-arc.c (arc_opcode_hash_entry_iterator_next): Set
	cached opcode to NULL when we reach a non-matching opcode.
	* testsuite/gas/arc/asm-errors-2.d: New file.
	* testsuite/gas/arc/asm-errors-2.err: New file.
	* testsuite/gas/arc/asm-errors-2.s: New file.
2016-05-18 22:23:40 +01:00
Andrew Burgess
3b889a7878 gas/arc: Add guard against operand array overflow.
Currently supplying an input file with too many operands to an
instruction will cause the assembler to overflow and array and trigger
undefined behaviour.

This change checks that we don't access outside the limits of the
operand array.

gas/ChangeLog:

	* config/tc-arc.c (tokenize_arguments): Add checks for array
	overflow.
	* testsuite/gas/arc/asm-errors.s: Addition test line added.
	* testsuite/gas/arc/asm-errors.err: Update expected results.
2016-05-18 22:22:49 +01:00
Alan Modra
a255f00a28 PPC_OPERAND_SIGNOPT range.
Commit b84bf58a accidentally extended the range of allowed negative
numbers.

	* config/tc-ppc.c (ppc_insert_operand): Trim PPC_OPERAND_SIGNOPT
	allowed negative range.
	* testsuite/gas/ppc/power9.s: Test xxspltib of -128, not -256.
	* testsuite/gas/ppc/power9.d: Update.
2016-05-18 12:43:21 +09:30