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Author SHA1 Message Date
Jeff Law
d2c9a57bc6 * mips-opc.c (rsqrt.s): Update based on r5900 ISA manual version 2.1 
(sqrt.s): Likewise.
 1998-06-01 16:28:52 +00:00
Frank Ch. Eigler
10c3731d9c * Followup for SCEI PR 15853: 2-operand R5900 "mult1" instruction. 
Mon May 18 14:27:06 1998  Frank Ch. Eigler  <fche@cygnus.com>
	* mips-opc.c (mult1): Add two-operand variety of mult1 for R5900.
 1998-05-18 17:46:35 +00:00
Frank Ch. Eigler
58b60bec0d * Fix sanitization 1998-05-18 09:31:10 +00:00
Frank Ch. Eigler
bbee738e86 * Converted conditional-trap MIPS opcodes to extra-operand variety also. 
Thu May  7 12:49:46 1998  Frank Ch. Eigler  <fche@cygnus.com>

	* mips-opc.c (teq,tge,tgeu,tlt,tltu,tne): Added three-operand
 	variety of ISA2 instructions to set bottom ten bits of trap code.
 1998-05-07 17:43:38 +00:00
Frank Ch. Eigler
01c6e45fe7 * First batch of fixes for sky PR 15853 (20-bit break/sdbbp) 1998-05-07 15:34:13 +00:00
Frank Ch. Eigler
171c7bbffe * Bit mask pattern fix for R5900 madd.s instruction; PR 15371. 1998-04-21 14:32:53 +00:00
Gavin Romig-Koch
56f04c4945 * mips-opc.c ("clz","dclz"): Added the 4320 versions. 1998-03-10 21:01:43 +00:00
Gavin Romig-Koch
46bb89f0d2 * mips-opc.c ("macc*","mul*"): Added the 4320 versions 
of these.
 1998-03-09 20:26:37 +00:00
Gavin Romig-Koch
779b65bfdb * mips-dis.c (_print_insn_mips) : Handle bfd_mach_mips4320. 
* mips-opc.c ("mac","dmac") : Added 4320 insns.
 1998-03-03 16:53:41 +00:00
Jeff Law
bac914a58b * mips-opc.c (r5900/madd.s): Takes three operands, not four. Fix 
opcode.
        (r5900/min.s): Incorrect opcode ....,101001 not ...110000.
        (r5900/msub.s): Takes three operands, not four.  Fix opcode.
 1998-02-27 20:15:50 +00:00
Jeff Law
7409c678e6 Fix it right this time. 1998-02-20 08:25:59 +00:00
Jeff Law
10e3e6ced5 * mips-opc.c (mula.s): Renamed from multa.s. 1998-02-20 08:22:48 +00:00
Jeff Law
b898fc0a3c * mips-opc.c (c.lt.s): Add r5900 variant. 
(c.le.s): Likewise.
pr14594.
 1998-01-13 16:21:45 +00:00
Ian Lance Taylor
e3d2cd9f37 * mips-opc.c: Add FP_D to s.d instruction flags. 1997-12-22 09:37:47 +00:00
Jeff Law
91866cc9be * mips-opc.c (mtpc, mfpc, mtps, mfps): Add r5900 variants. 
Also move 'P' handling out of vr5400 sanitized code so it can be used
on r5900 too.
 1997-12-15 19:43:04 +00:00
Gavin Romig-Koch
cfcbe03ff7 mips-opc.c (sync,cache): These are 3900 insns. 1997-11-12 15:18:56 +00:00
Ken Raeburn
cfca14e759 make vr5400 disassembly work; fix bugs in some vr5400 insns 1997-11-03 18:28:35 +00:00
Gavin Romig-Koch
fe9cb9d8dd Correct tx49 sanitation. 1997-11-02 23:55:21 +00:00
Gavin Romig-Koch
0cca41d47a * mips-opc.c (deret,dmult,dmultu,madd,maddu,pref,sdbbp): 
Add tx49 insns and configury.
 1997-10-29 20:33:43 +00:00
Ken Raeburn
a0539c6102 * mips-opc.c (ffc, ffs): Fix mask. 1997-10-28 23:03:12 +00:00
Ken Raeburn
a3066d9ac8 Duh. Check in the vr5400 stuff from the directory that doesn't have 
it sanitized out this time...
 1997-10-28 03:44:27 +00:00
Ken Raeburn
581c03af3e added vr5400 stuff, fixed "not" mask 1997-10-28 03:42:29 +00:00
Gavin Romig-Koch
d7727fe96b opcodes/mips-opc.c (bnezl,beqzl): Mark these as also tx39. 1997-10-17 17:26:45 +00:00
Gavin Romig-Koch
b7dd310d55 opcodes/mips-opc.c: Note that 'jalx' is (probably incorrectly) marked I1. 1997-10-16 16:03:22 +00:00
Gavin Romig-Koch
80ae705d30 opcodes/mips-opc.c: Three op mult is not an ISA insn. 1997-10-08 03:46:38 +00:00
Gavin Romig-Koch
b0326e92a5 opcodes/mips-opc.c: Fix formatting. 1997-10-08 03:42:27 +00:00
Andrew Cagney
6546a590b4 Fix MTSA opcode encoding. 1997-07-28 13:45:45 +00:00
Jeff Law
4bb0ae107d * mips-opc.c (mips_builtin_opcodes): If an insn uses single 
precision FP, mark it as such.  Likewise for double precision
        FP.  Mark ISA1 insns.  Consolidate duplicate opcodes where
        possible.
        (mips_builtin_opcodes): Remove non-existant r5900 instructions
toshiba_5900 stuff
 1997-07-11 16:13:42 +00:00
Jeff Law
d0efa46b2d * mips-opc.c (mips_builtin_opcodes): Add "pinteh", "pexeh" and 
"pexew" as synonyms for "pintoh", "pexoh", "pexow".

pr12399.
 1997-06-30 15:06:50 +00:00
Ian Lance Taylor
a21e1e96be * mips-opc.c: Add cast when setting mips_opcodes. 1997-03-27 19:25:01 +00:00
Dawn Perchik
a2768484d9 * mips-opc.c: Add macros for cop0, cop1 cop2 and cop3. 
Change mips_opcodes from const array to a pointer,
	and change bfd_mips_num_opcodes from const int to int,
	so that we can increase the size of the mips opcodes table
	dynamically.
 1997-02-23 22:26:01 +00:00
Gavin Romig-Koch
276c2d7dc8 Add r5900 1997-02-11 13:26:34 +00:00
Ian Lance Taylor
8d67dc3077 Add support for mips16 (16 bit MIPS implementation): 
* mips16-opc.c: New file.
	* mips-dis.c: Include "elf-bfd.h" and "elf/mips.h".
	(mips16_reg_names): New static array.
	(print_insn_big_mips): Use print_insn_mips16 in 16 bit mode or
	after seeing a 16 bit symbol.
	(print_insn_little_mips): Likewise.
	(print_insn_mips16): New static function.
	(print_mips16_insn_arg): New static function.
	* mips-opc.c: Add jalx instruction.
	* Makefile.in (mips16-opc.o): New target.
	* configure.in: Use mips16-opc.o for bfd_mips_arch.
	* configure: Rebuild.
 1996-11-26 15:59:18 +00:00
Ian Lance Taylor
f27ab33041 * mips-opc.c: Add r4650 mul instruction. 1995-02-16 22:35:36 +00:00
Ian Lance Taylor
470feacfab * mips-opc.c: Add uld and usd macros for unaligned double load and 
store.
 1995-02-15 20:47:31 +00:00
Ian Lance Taylor
27faaa41e6 * mips-opc.c: Add dli as a synonym for li. 1994-12-20 16:27:45 +00:00
Ian Lance Taylor
8490907307 * mips-opc.c (mips_opcodes): Set WR_t for sc and scd. 
PR 5632
 1994-09-14 21:53:14 +00:00
Ian Lance Taylor
942a4965b7 * mips-opc.c: Set INSN_STORE_MEMORY flag for all instructions 
which store a value into memory.
PR 5433.
 1994-09-06 15:42:11 +00:00
Ian Lance Taylor
9978cd4dc9 * mips-opc.c: Correct lwu opcode value (book had it wrong). 1993-10-05 21:49:04 +00:00
Ian Lance Taylor
547998d2c8 * mips-opc.c: Change div machine instruction to be z,s,t rather 
than s,t.  Change div macro to be d,v,t rather than d,s,t.
	Likewise for divu, ddiv, ddivu.  Added z,s,t case for drem, dremu,
	rem and remu which generates only the corresponding div
	instruction.  This is for compatibility with the MIPS assembler,
	which only generates the simple machine instruction when an
	explicit destination of $0 is used.
	* mips-dis.c (print_insn_arg): Handle 'z' (always register zero).
 1993-09-02 17:14:10 +00:00
Ian Lance Taylor
a9c686adf5 * mips-opc.c: Move div machine instruction after macro forms. 
Change d,s,t form to d,v,t.  Likewise for divu, ddiv and ddivu.
	This is for compatibility with the MIPS assembler, which only
	generates the simple machine instruction when an explicit
	destination of $0 is used.
 1993-09-02 14:42:31 +00:00
Ian Lance Taylor
a5ba0d3f48 * mips-opc.c: From davidj@ICSI.Berkeley.EDU (David Johnson): Set 
WR_31 hazard for bal, bgezal, bltzal.
 1993-08-27 14:55:22 +00:00
Ian Lance Taylor
2bef2d3e57 * mips-opc.c: Added r6000 and r4000 instructions and macros. 
Changed hazard information to distinguish between memory load
	delays and coprocessor load delays.
 1993-08-20 15:40:51 +00:00
Ian Lance Taylor
45b1470513 * mips-opc.c: li.d uses "T,L", not "S,F". Added li.s. 1993-08-18 19:40:37 +00:00