3 byte instructions.
(disassemble): Handle new instruction formats FMT_D6, FMT_D7, FMT_D8
FMT_D9 and FMT_D10. Handle various new opcode flags for the am33.
(mn10300_opcodes): Reorder so as to try and select opcodes from
the core chip when multiple alternatives exist. Change several
am33 instructions to use IMM32_HIGH8_MEM. Fix typos in "mac" and
"macbu" instructions. Fix typos in a couple DSP instructions too.
printing references the symbol table to determine whether the
instruction resides in a block regular instructions or mips16
instructions. However, when the disassembler gets used in other
environments where the symbol table is not present, we no longer
rely in the symbol table, rather, use the low bit of the
instructions address to guess. There should be no change for usage
of the disassembler in host based programse, gdb ,objdump.
(print_insn_big_mips): ditto.
(print_insn_mips): ditto
* m10300-opc.c (USP, SSP, MSP, PC, IMM4, EPSW, RN0, RM1): New
operands for the am33.
(mn10300_opcodes): Add new instructions from the am33.
end-sanitize-am33
* m10300-opc.c (mn10300_opcodes): Change opcode for "syscall".
Snapshot current work.
* i386-dis.c: Don't print opcode suffix when we can figure out the
size (and gas can!) by register operands, or from the default
size.
(putop): Handle 'A', 'B', 'L', 'P', 'Q', 'R' macros. Rename 'C'
macro to 'E'.
(dis386, dis386_twobyte, grps): Use new suffix macros.
(dis386): Correct imul Ib to imul sIb. Change jnl to jge to be
consistent. Add suffix for call, jmp, lcall, ljmp, iret. Reverse
order of cmps operands to agree with Intel docs. Correct operand
of aad and aam (Ib -> sIb). Change ud2b from 0fb8 to 0fb9 to
agree with Intel docs.
(print_insn_x86): Print orphan fwait before other prefixes.
Return correct byte count for orphan fwait with prefixes. Don't
print `bound' operands in reverse order.
(ckprefix): Stop accumulating prefixes if we get fwait.
(OP_DIR): Print `$' before Ap operands of ljmp, lcall.
Fix problems when bfd_vma is wider than long.
* i386-dis.c: Make op_address and start_pc unsigned.
(set_op): Make parameter unsigned.
(print_insn_x86): Cast to bfd_vma when passing a value to
print_address_func.
* ns32k-dis.c (CORE_ADDR): Don't define.
(print_insn_ns32k): Change type of addr to bfd_vma. Use
bfd_scan_vma to read back address.
(print_insn_arg): Change type of addr to bfd_vma. Use sprintf_vma
to format it.
* m68k-dis.c (COERCE32): Cast to bfd_signed_vma to avoid overflow.
(NEXTULONG): New definition.
(print_insn_m68k): Avoid overflow when computing third argument of
print_insn_arg.
(print_insn_arg): Use NEXTULONG to fetch 32 bit address values.
Use disp instead of val to store offset values.
(print_indexed): Use base_disp instead of word to store base
displacement, to avoid overflow.
* m10300-dis.c (disassemble): Cast value to long when computing
pc-relative address, to get correct sign extension.
* i386-dis.c: Combine aflag and dflag into sizeflag. Change OP_*
functions to void.
(OP_DSreg): Rename from OP_DSSI.
(OP_ESreg): Rename from OP_ESDI.
(Xb, Xv, Yb, Yv): Use index reg code, not b_mode or v_mode.
(DSBX): Define.
(append_seg): Rename from append_prefix.
(ptr_reg): New function.
(dis386): Add S suffix to pushf, popf, ret, lret, enter, leave.
Add DSBX for xlat.
(PREFIX_ADDR): Rename from PREFIX_ADR.
(float_reg): Add non-broken opcodes for people who don't want
UNIXWARE_COMPAT.
* ppc-opc.c (powerpc_macros): Support shifts and rotates of size
0; produce error message for shifts of size 32 (or 64 for 64-bit
shifts), because the hardware doesn't support them.
Thu May 7 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
* mips-opc.c (teq,tge,tgeu,tlt,tltu,tne): Added three-operand
variety of ISA2 instructions to set bottom ten bits of trap code.
