gas:
* as.c (perform_an_assembly_pass): Do not create text, data and bss
sections for MACH-O. Do not switch to the text section.
* config/obj-macho.c (obj_mach_o_segT_from_bfd_name): Forward decl.
(mach_o_begin): Startup with only text section unless suppressed.
* config/obj-macho.h (obj_begin): define to mach_o_begin ().
gas/testsuite:
* gas/mach-o/sections-1.d: Amend to recognize that bss is not emitted
by default.
* gas/mach-o/sections-2.d: New.
* elf32-rl78.c (rl78_elf_howto_table): Add R_RL78_RH_RELAX.
(rl78_reloc_map): Add BFD_RELOC_RL78_RELAX.
(rl78_elf_relocate_section): Add R_RL78_RH_RELAX, R_RL78_RH_SFR,
and R_RL78_RH_SADDR.
(rl78_elf_finish_dynamic_sections): Only validate PLT section if
we didn't relax anything, as relaxing might remove a PLT reference
after we've set up the table.
(elf32_rl78_relax_delete_bytes): New.
(reloc_bubblesort): New.
(rl78_offset_for_reloc): New.
(relax_addr16): New.
(rl78_elf_relax_section): Add support for relaxing long
instructions into short ones.
[gas]
* config/rl78-defs.h (rl78_linkrelax_addr16): Add.
(rl78_linkrelax_dsp, rl78_linkrelax_imm): Remove.
* config/rl78-parse.y: Tag all addr16 and branch patterns with
relaxation markers.
* config/tc-rl78.c (rl78_linkrelax_addr16): New.
(rl78_linkrelax_branch): New.
(OPTION_RELAX): New.
(md_longopts): Add relax option.
(md_parse_option): Add OPTION_RELAX.
(rl78_frag_init): Support relaxation.
(rl78_handle_align): New.
(md_assemble): Support relaxation.
(md_apply_fix): Likewise.
(md_convert_frag): Likewise.
* config/tc-rl78.h (MAX_MEM_FOR_RS_ALIGN_CODE): New.
(HANDLE_ALIGN): New.
(rl78_handle_align): Declare.
* config/rl78-parse.y (rl78_bit_insn): New. Set it for all bit
insn patterns.
(find_bit_index): New. Strip .BIT suffix off relevent
expressions for bit insns.
(rl78_lex): Exclude bit suffixes from expression parsing.
[include/elf]
* rl78.h (R_RL78_RH_RELAX, R_RL78_RH_SFR, R_RL78_RH_SADDR): New.
(RL78_RELAXA_BRA, RL78_RELAXA_ADDR16: New.
* mach-o-i386.c (bfd_mach_o_section_type_valid_for_tgt): Define NULL.
* mach-o-target.c (bfd_mach_o_backend_data): Initialize bfd_mach_o_section_type_valid_for_tgt
* mach-o-x86-64.c (bfd_mach_o_section_type_valid_for_x86_64): New.
(bfd_mach_o_section_type_valid_for_tgt): Set to bfd_mach_o_section_type_valid_for_x86_64.
* mach-o.c (bfd_mach_o_section_type_name): Reorder and eliminate dup.
(bfd_mach_o_section_attribute_name): Reorder.
(bfd_mach_o_get_section_type_from_name): If the target has defined a validator for section
types, then use it.
* mach-o.h (bfd_mach_o_get_section_type_from_name): Alter declaration to include the bfd.
gas:
* config/obj-macho.c (obj_mach_o_section): Account for target-dependent section
types. Improve error handling when wrong section types/attributes are specified.
gas/testsuite:
* gas/mach-o/err-sections-1.s: New.
* gas/mach-o/err-sections-2.s: New.
* gas/mach-o/sections-3.d: New.
* gas/mach-o/sections-3.s: New.
hosts.
* cgen-asm.c (cgen_parse_signed_integer): Add code to handle the
sign extension of negative values on a 64-bit host.
* frv-asm.c: Regenerate.
* gas/frv/immediates.s: New test file - checks assembly of
constant values.
* gas/frv/immediates.d: Expected disassmbly.
* gas/frv/allinsn.exp: Run the new test.
2011-12-08 Andrew Pinski <apinski@cavium.com>
Adam Nemet <anemet@caviumnetworks.com>
* archures.c (bfd_mach_mips_octeon2): New macro
* bfd-in2.h: Regenerate.
* cpu-mips.c (I_mipsocteon2): New enum value.
(arch_info_struct): Add bfd_mach_mips_octeon2.
* elfxx-mips.c (_bfd_elf_mips_mach): Support E_MIPS_MACH_OCTEON2.
(mips_set_isa_flags): Add bfd_mach_mips_octeon2.
(mips_mach_extensions): Add bfd_mach_mips_octeon2.
gas:
2011-12-08 Andrew Pinski <apinski@cavium.com>
Adam Nemet <anemet@caviumnetworks.com>
* tc-mips.c (CPU_IS_OCTEON): Add Octeon2.
(mips_cpu_info_table): Add Octeon2.
* doc/c-mips.texi: Document octeon2 as an acceptable value for -march=.
gas/testsuite:
2011-12-08 Andrew Pinski <apinski@cavium.com>
Adam Nemet <anemet@caviumnetworks.com>
* gas/mips/mips.exp: Add Octeon2 for an architecture.
Run octeon2 test.
* gas/mips/octeon2.d: New file.
* gas/mips/octeon2.s: New file.
include/opcode:
2011-12-08 Andrew Pinski <apinski@cavium.com>
Adam Nemet <anemet@caviumnetworks.com>
* mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
(INSN_OCTEON2): New macro.
(CPU_OCTEON2): New macro.
(OPCODE_IS_MEMBER): Add Octeon2.
opcodes:
2011-12-08 Andrew Pinski <apinski@cavium.com>
Adam Nemet <anemet@caviumnetworks.com>
* mips-dis.c (mips_arch_choices): Add Octeon2.
For "octeon+", just include OcteonP for the insn.
* mips-opc.c (IOCT): Include Octeon2.
(IOCTP): Include Octeon2.
(IOCT2): New macro.
(mips_builtin_opcodes): Add "laa", "laad", "lac", "lacd", "lad",
"ladd", "lai", "laid", "las", "lasd", "law", "lawd".
Move "lbux", "ldx", "lhx", "lwx", and "lwux" up to where the standard
loads are, and add IOCT2 to them.
Add "lbx" and "lhux".
Add "qmac.00", "qmac.01", "qmac.02", "qmac.03", "qmacs.00",
"qmacs.01", "qmacs.01", "qmacs.02" and "qmacs.03".
Add "zcb" and "zcbt".
(arm_it): Use ARM_IT_MAX_OPERANDS.
(neon_select_shape): Ensure we have matched all operands.
* gas/testsuite/gas/arm/neon-suffix-bad.l: Add testcase.
* gas/testsuite/gas/arm/neon-suffix-bad.s: Likewise.
Tag_ARM_ISA_use and Tag_Thumb_ISA_use.
* gas/arm/attr-any-armv4t.d: New test.
* gas/arm/attr-any-armv4t.s: New file.
* gas/arm/attr-any-thumbv6.d: New test.
* gas/arm/attr-any-thumbv6.s: New file.
(arm_arch_option_table): Likewise.
(arm_option_extension_value_table): Likewise.
(ARM_CPU_OPT): New define.
(ARM_ARCH_OPT): Likewise.
(ARM_EXT_OPT): Likewise.
(arm_cpus): Use ARM_CPU_OPT to initialize.
(arm_archs): Use ARM_ARCH_OPT to initialize.
(arm_extensions): Use ARM_EXT_OPT to initialize.
(arm_parse_extension): Ensure option string matching matches
the whole string.
(arm_parse_cpu): Likewise.
(arm_parse_arch): Likewise.
* gas/testsuite/gas/arm/cmdline-bad-arch.d: New test case.
* gas/testsuite/gas/arm/cmdline-bad-cpu.d: Likewise.
* gas/mips/mips.exp (run_dump_test_arch): Add an opts parameter.
(run_dump_test_arches): Allow additional options to be passed.
(run_list_test_arch): Add opts to the name.
(run_list_test_arches): Allow the options to be elided.
(mips4-fp, mips5-fp): Run twice, one with -32 and once with -mabi=o64.
(mips64r2-ill, octeon-ill): Remove empty options string.
2011-11-29 Andrew Pinski <apinski@cavium.com>
* mips-dis.c (mips_arch_choices): Add Octeon+.
* mips-opc.c (IOCT): Include Octeon+.
(IOCTP): New macro.
(mips_builtin_opcodes): Add "saa" and "saad".
bfd/
2011-11-29 Andrew Pinski <apinski@cavium.com>
* archures.c (bfd_mach_mips_octeonp): New macro.
* bfd-in2.h: Regenerate.
* bfd/cpu-mips.c (I_mipsocteonp): New enum value.
(arch_info_struct): Add bfd_mach_mips_octeonp.
* elfxx-mips.c (mips_set_isa_flags): Add bfd_mach_mips_octeonp.
(mips_mach_extensions): Add bfd_mach_mips_octeonp.
include/opcodes/
2011-11-29 Andrew Pinski <apinski@cavium.com>
* mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
(INSN_OCTEONP): New macro.
(CPU_OCTEONP): New macro.
(OPCODE_IS_MEMBER): Add Octeon+.
(M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
gas/
2011-11-29 Andrew Pinski <apinski@cavium.com>
* config/tc-mips.c (CPU_IS_OCTEON): New macro function.
(CPU_HAS_SEQ): Change to use CPU_IS_OCTEON.
(NO_ISA_COP): Likewise.
(macro) <ld_st>: Add support when off0 is true.
Add support for M_SAA_AB, M_SAA_OB, M_SAAD_OB and M_SAAD_AB.
(mips_cpu_info_table): Add octeon+.
* doc/c-mips.texi: Document octeon+ as an acceptable value for -march=.
gas/testsuite/
2011-11-29 Andrew Pinski <apinski@cavium.com>
* gas/mips/mips.exp: Add octeon+ for an architecture.
Run octeon-saa-saad test.
(run_dump_test_arch): For Octeon architectures, also try octeon@.
* gas/mips/octeon-pref.d: Remove -march=octeon from command line.
* gas/mips/octeon.d: Likewise.
* gas/mips/octeon-saa-saad.d: New file.
* gas/mips/octeon-saa-saad.s: New file
* config/tc-mips.c (can_swap_branch_p): Exclude microMIPS
variant frags too.
gas/testsuite/
* gas/mips/relax-swap3.d: New test.
* gas/mips/mips16@relax-swap3.d: Likewise.
* gas/mips/micromips@relax-swap3.d: Likewise.
* gas/mips/relax-swap3.s: New test source.
* gas/mips/mips.exp: Run the new tests.
with the (PLT) instruction suffix when operating in eabi mode.
* doc/c-arm.texi (ARM_Relocations): Extend description of (PLT)
suffix.
* gas/arm/pic.d: Update expected output.
rx-parse.c: In function ‘rx_parse’:
rx-parse.c:3774:9: error: passing argument 1 of ‘rx_error’ discards ‘const’
qualifier from pointer target type [-Werror]
../../../gas/config/rx-defs.h:40:12: note:
expected ‘char *’ but argument is of type ‘const char *’
cc1: all warnings being treated as errors
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
