* sim/frv/testutils.inc (or_gr_immed): New macro.
* sim/frv/fp_exception-fr550.cgs: Write insns using
unaligned registers into the program in order to
cause the required exceptions.
* sim/frv/fp_exception.cgs: Ditto.
* sim/frv/regalign.cgs: Ditto.
* sim/frv/fr550: New subdirectory.
* sim/frv/fr400/*.cgs: Add fr550 as appropriate.
* sim/frv/fr500/*.cgs: Add fr550 as appropriate.
* sim/frv/interrupts/*.cgs: Add fr550 as appropriate.
* sim/frv/interrupts/*-fr550.cgs: New test cases for fr550.
* profile.h (update_FR_ptime): New prototype.
(update_FRdouble_ptime): Ditto.
(update_SPR_ptime): Ditto.
(increase_ACC_busy): Ditto.
(enforce_full_acc_latency): Ditto.
(post_wait_for_SPR): Ditto.
* profile.c (update_FR_ptime): Moved here from profile-fr500.c.
(update_FRdouble_ptime): Ditto.
(update_SPR_ptime): New function.
(increase_ACC_busy): Ditto.
(enforce_full_acc_latency): Ditto.
(vliw_wait_for_fdiv_resource): Correct resource name.
(vliw_wait_for_fsqrt_resource): Ditto.
(post_wait_for_SPR): New function.
* profile-fr500.c (frvbf_model_fr500_u_commit): New function.
(frvbf_model_fr500_u_gr2fr): Pass out_FRk as output register to
adjust_float_register_busy.
(frvbf_model_fr500_u_gr_load): Record latency of SPR registers.
(frvbf_model_fr500_u_fr_load): Wait for and record latency of SPR
registers.
(frvbf_model_fr500_u_float_arith): Ditto.
(frvbf_model_fr500_u_float_dual_arith): Ditto.
(frvbf_model_fr500_u_float_div): Ditto.
(frvbf_model_fr500_u_float_sqrt): Ditto.
(frvbf_model_fr500_u_float_convert): Ditto.
(update_FR_ptime): Moved to profile.c
(update_FRdouble_ptime): Moved to profile.c
* profile-fr400.c (update_FR_ptime): Removed. Identical to functions
for other machines.
(update_FRdouble_ptime): Ditto.
* arch.h,cpu.h,sem.c,decode.[ch],model.c,sem.c: Regenerated.
* registers.c (frv_check_spr_read_access): Check for access to
ACC4-ACC63 and ACCG4-ACCG63.
* profile.h (frv-desc.h): #include it.
(spr_busy): New member of FRV_PROFILE_STATE.
(spr_latency): Ditto.
(GNER_FOR_GR): New macro.
(FNER_FOR_FR): New maccro.
(update_SPR_latency): New function.
(vliw_wait_for_SPR): New function.
* profile.c (profile-fr550.h): #include it.
(update_latencies): Update SPR latencies.
(update_target_latencies): Ditto.
(update_SPR_latency): New function.
(vliw_wait_for_SPR): New function.
* profile-fr500.c (frvbf_model_fr500_u_idiv): Record GNER latency.
(frvbf_model_fr500_u_trap): Removed unused variable, ps.
(frvbf_model_fr500_u_check): Ditto.
(frvbf_model_fr500_u_clrgr): New unit modeller for fr500.
(frvbf_model_fr500_u_clrfr): Ditto.
(frvbf_model_fr500_u_spr2gr): Wait for SPR.
(frvbf_model_fr500_u_gr2spr): Ditto.
* frv-sim.h (H_SPR_ACC4): New macro.
(H_SPR_ACCG4): New macro;
(H_SPR_ACC0): Removed.
(H_SPR_ACCG0): Removed.
* arch.h,model.c,sem[ch],decode.[ch]: Regenerated.
* profile.c (slot_names): FM1 was listed twice. Changed first
instance to FM0. Added IALL, FMALL and FMLOW.
(print_parallel): Don't examine slots with no insns.
On behalf of Doug Evans <dje@sebabeach.org>
* Makefile.in (stamp-arch,stamp-cpu): Pass archfile to cgen.
Remove copying of .cpu file to cgen/cpu, no longer needed.
On behalf of Doug Evans <dje@sebabeach.org>
* cgen.sh: New arg archfile.
* Make-common.in (cgen-arch,cgen-cpu,cgen-defs,cgen-decode,
cgen-cpu-decode,cgen-desc): Update call to cgen.sh.
* sim/frv/interrupts/Ipipe-fr400.cgs: New file.
* sim/frv/interrupts/Ipipe-fr500.cgs: New file.
* sim/frv/interrupts/Ipipe.cgs: Remove (replaced by above).
Dave Brolley <brolley@redhat.com>
* frv/: New directory, simulator for the Fujitsu FR-V.
* testsuite/frv-elf/: New directory.
* testsuite/sim/frv/: New directory.
* configure.in: Add frv configury.
* configure: Regenerate.
2003-08-28 Andrew Cagney <cagney@redhat.com>
* dv-glue.c (hw_glue_finish): Change %d to %ld to match sizeof.
* sim-options.c (print_help): Cast the format with specifier to
"int".
Index: mn10300/ChangeLog
2003-08-28 Andrew Cagney <cagney@redhat.com>
* dv-mn103ser.c (do_polling_event): Change type of "serial_reg" to
"long".
(read_status_reg): Cast "serial_reg" to "long".
* dv-mn103tim.c (do_counter_event): Change type of "timer_nr" to
"long".
(do_counter6_event, write_mode_reg, write_tm6md): Ditto.
* sim/sh/gencode.c ( tab[] ): Addition of MAC.L handler and
correction for MAC.W handler
* sim/sh/interp.c ( macl ): New Function. Implementation of
MAC.L handler.
* MAINTAINERS: Andrew Cagney (mips) and Geoff Keating (ppc) drop
maintenance. List igen and sh maintainers. Mention that target
and global maintainers pick up the slack.
the physical address in virtual address.
(struct _sim_cpu): Add memory bank members.
* m68hc11_sim.c (cpu_initialize): Clear memory bank parameters.
* interp.c (sim_hw_configure): Create memory bank according to memory
bank parameters.
(sim_get_bank_parameters): New function to obtain memory bank config
from the symbol table.
(sim_prepare_for_program): Call it to obtain the memory bank parameters.
(sim_open): Call sim_prepare_for_program.
* dv-m68hc11.c (m68hc11cpu_io_write_buffer): Use memory bank parameters
to check if address is within bank window.
(m68hc11cpu_io_read_buffer): Likewise.
(attach_m68hc11_regs): Map the memory bank according to memory bank
parameters.
* cmpw.s: Add test for less-than-zero immediate.
* shll.s: Test for shll reg, reg.
* shlr.s: Test for shlr reg, reg.
* mova.s: Add dozens of new mova tests.
* compile.c (decode): Enhancements for mova.
Initialize cst, reg, and rdisp inside the loop, for each
new instruction. Defer correction of the disp2 values until
later, and then adjust them by the size of the first operand,
rather than the size of the instruction.
(sim_resume): For mova, adjust the size of the second operand
according to the type of the first operand (INDEXB vs. INDEXW).
In cases where there is only one operand, the other two must
both be composed on the fly.
* gencode.c (pshl): Change < to <= (shift by 16 is allowed).
Cast argument of >> to unsigned to prevent sign extension.
(psha): Change < to <= (shift by 32 is allowed).
* gencode.c: A few more fix-ups of refs and defs.
(frchg): Raise SIGILL if in double-precision mode.
(ldtlb): We don't simulate cache, so this is a no-op.
(movsxy_tab): Correct a few bit pattern errors.
* gencode.c (ppi_gensim): For a conditional ppi insn, if the
condition is false, we want to return (not break). A break
will take us to the end of the function where registers will
be updated, whereas the desired outcome is for nothing to change.
* gencode.c (op tab): Some fix-ups of refs and defs.
(ocbi, ocbp): Cache not simulated, but may cause memory fault.
(gensym_caselist): Add default case to switch statement.
(expand_ppi_code): Add default case to switch statement.
Written by matthew green <mrg@redhat.com>, with fixes from Aldy
Hernandez <aldyh@redhat.com>, Jim Wilson <wilson@redhat.com>, and
Nick Clifton <nickc@redhat.com>.
* ppc-instructions: Include altivec.igen and e500.igen.
(model_busy, model_data): Add vr_busy and vscr_busy.
(model_trace_release): Trace vr_busy and vscr_busy.
(model_new_cycle): Update vr_busy and vscr_busy.
(model_make_busy): Update vr_busy and vscr_busy.
* registers.c (register_description): Add Altivec and e500
registers.
* psim.c (psim_read_register, psim_read_register): Handle Altivec
and e500 registers.
* ppc-spr-table (SPEFSCR): Add VRSAVE and SPEFSCR registers.
* configure.in (sim_filter): When *altivec* add "av". When *spe*
or *simd* add e500.
(sim_float): When *altivec* define WITH_ALTIVEC. When *spe* add
WITH_E500.
* configure: Re-generate.
* e500.igen, altivec.igen: New files.
* e500_expression.h, altivec_expression.h: New files.
* idecode_expression.h: Update copyright. Include
"e500_expression.h" and "altivec_expression.h".
* e500_registers.h, altivec_registers.h: New files.
* registers.h: Update copyright. Include "e500_registers.h" and
"altivec_registers.h".
(registers): Add Altivec and e500 specific registers.
* Makefile.in (IDECODE_H): Add "idecode_e500.h" and
"idecode_altivec.h".
(REGISTERS_H): Add "e500_registers.h" and "altivec_registers.h".
(tmp-igen): Add dependencies on altivec.igen and e500.igen .
From matthew green <mrg@redhat.com>:
* sim-fpu.h: Update copyright.
(sim_fpu_fraction, sim_fpu_guard): New prototypes.
* sim-fpu.c: Update copyright.
(sim_fpu_fraction, sim_fpu_guard): New inline functions.
* cgen-trace.h (sim_disasm_read_memory): Update args to be compatible
with disassemble_info:read_memory_func.
* cgen-trace.c (sim_disasm_read_memory): Ditto.
* compile.c: Replace "Hitachi" with "Renesas".
(decode): Distinguish AV_H8S from AV_H8H.
(sim_resume): H8SX can use any register for TAS.
(decode): Add support for VECIND.
(sim_resume): Implement rte/l and rts/l.
(GETSR): New macro (actually old macro reincarnated).
(decode): Add handling for IMM2.
(sim_resume): Drop extra block around jmp, jsr, rts.
Add handling for trapa and rte.
For divxu.b, change 0xffff mask to 0xff.
(set_h8300h): Add bfd_mach_h8300sxn machine.
* compile.c (sim_info): Fix typo in output.
* h8300/compile.c (set_h8300h): Replace 'flag' arguments
with a bfd_machine argument, and decode it inline.
Check for bfd_mach_h8300hn and bfd_mach_h8300sn.
