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Author SHA1 Message Date
Nick Clifton
03ee1b7f8e PR gas/11013 
* arm-dis.c (thumb32_opc): Adjust disassembly of QADD, QDADD, QSUB
        and QDSUB.

        * gas/arm/arch7em.d: Update expected disassembly.
        * gas/arm/thumb32.d: Likewise.

        * config/tc-arm.c (do_t_simd2): New function.
        (insns): Use do_t_simd2 for QADD, QDADD, QSUB and QDSUB.
 2009-12-02 20:26:30 +00:00
Nick Clifton
ee9fd255b7 PR gas/11030 
* m68k-opc.c (m68k_opcodes): Allow the STLDSR instruction on the
        Coldfire ISA A+.
 2009-11-30 14:45:30 +00:00
Sebastian Pop
ccc5981b93 2009-11-17 Quentin Neill <quentin.neill@amd.com> 
Sebastian Pop  <sebastian.pop@amd.com>

	gas/testsuite/
	* gas/i386/x86-64-fma4.d: Add new patterns.
	* gas/i386/x86-64-fma4.s: Same.
	* gas/i386/x86-64-xop.d: Adjusted.

	opcodes/
	* i386-dis.c (get_vex_imm8): Increase bytes_before_imm when
	decoding the second source operand from the immediate byte.
	(OP_EX_VexW): Pass an extra integer to identify the second
	and third source arguments.
 2009-11-25 15:15:30 +00:00
H.J. Lu
18d0c96eb9 Allow lock on cmpxch16b. 
gas/testsuite/

2009-11-19  H.J. Lu  <hongjiu.lu@intel.com>

	* gas/i386/lock-1.s: Add cmpxchg16b test.
	* gas/i386/lock-1-intel.d: Updated.
	* gas/i386/lock-1.d: Likewise.

opcodes/

2009-11-19  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-opc.tbl: Add IsLockable to cmpxch16b.
	* i386-tbl.h: Regenerated.
 2009-11-19 15:26:42 +00:00
Nick Clifton
945ee43039 PR binutils/10924 
* gas/arm/arch4t-eabi.d: Restore previous expected dissambly of
        instructions using Immediate Offset addressing with an offset of
        zero.
        * gas/arm/arch4t.d: Likewise.
        * gas/arm/arm7t.d: Likewise.
        * gas/arm/xscale.d: Likewise.
        * gas/arm/wince-inst.d: Remove 'p' suffix from cmp, cmn, teq and
        tst instructions.

        PR binutils/10924
        * arm-dis.c (print_insn_arm): Do not print an offset of zero when
        decoding Immediaate Offset addressing.
 2009-11-19 14:07:11 +00:00
Sebastian Pop
41effecb2d 2009-11-18 Sebastian Pop <sebastian.pop@amd.com> 
opcodes/
	PR binutils/10973
	* i386-dis.c (get_vex_imm8): Do not increment codep.
	Avoid incrementing bytes_before_imm when OP_E_memory
	has already forwarded the codep pointer.
	(OP_EX_VexW): Increment codep to skip mod/rm byte.

	gas/testsuite/
	* gas/i386/x86-64-xop.d: Update patterns.
 2009-11-19 07:08:39 +00:00
Sebastian Pop
f0ae4a24b0 2009-11-18 Sebastian Pop <sebastian.pop@amd.com> 
gas/
	* config/tc-i386.c (cpu_arch): Remove cvt16.
	(md_show_usage): Same.
	* doc/c-i386.texi: Same.

	gas/testsuite/
	* gas/i386/cvt16.d: Removed.
	* gas/i386/cvt16.s: Removed.
	* gas/i386/x86-64-cvt16.d: Removed.
	* gas/i386/x86-64-cvt16.s: Removed.
	* gas/i386/i386.exp: Remove cvt16 and x86-64-cvt16 tests.

	opcodes/
	* i386-dis.c (VEX_LEN_XOP_08_A0): Removed.
	(VEX_LEN_XOP_08_A1): Removed.
	(xop_table): Remove entries for VEX_LEN_XOP_08_A0 and
	VEX_LEN_XOP_08_A1.
	(vex_len_table): Same.
	* i386-gen.c (CPU_CVT16_FLAGS): Removed.
	(cpu_flags): Remove field for CpuCVT16.
	* i386-opc.h (CpuCVT16): Removed.
	(i386_cpu_flags): Remove bitfield cpucvt16.
	(i386-opc.tbl): Remove CVT16 instructions.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Regenerated.
 2009-11-18 20:28:59 +00:00
Sebastian Pop
5dd85c9970 2009-11-17 Sebastian Pop <sebastian.pop@amd.com> 
Quentin Neill  <quentin.neill@amd.com>

	gas/
	* config/tc-i386.c (cpu_arch): Added .xop and .cvt16.
	(build_vex_prefix): Handle xop08.
	(md_assemble): Don't special case the constant 3 for insns using MODRM.
	(build_modrm_byte): Handle vex2sources.
	(md_show_usage): Add xop and cvt16.
	* doc/c-i386.texi: Document fma4, xop, and cvt16.

	gas/testsuite/
	* gas/i386/i386.exp: Run xop and cvt16 in 32-bit mode.
	Run x86-64-xop and x86-64-cvt16 in 64-bit mode.
	* gas/i386/lwp.d: Update name of the testcase.
	* gas/i386/x86-64-xop.d: New.
	* gas/i386/x86-64-xop.s: New.
	* gas/i386/xop.d: New.
	* gas/i386/xop.s: New.
	* gas/i386/cvt16.d: New.
	* gas/i386/cvt16.s: New.

	opcodes/
	* i386-dis.c (OP_Vex_2src_1): New.
	(OP_Vex_2src_2): New.
	(Vex_2src_1): New.
	(Vex_2src_2): New.
	(XOP_08): Added.
	(VEX_LEN_XOP_08_A0): Added.
	(VEX_LEN_XOP_08_A1): Added.
	(VEX_LEN_XOP_09_80): Added.
	(VEX_LEN_XOP_09_81): Added.
	(xop_table): Added an entry for XOP_08.  Handle xop instructions.
	(vex_len_table): Added entries for VEX_LEN_XOP_08_A0,
	VEX_LEN_XOP_08_A1, VEX_LEN_XOP_09_80, VEX_LEN_XOP_09_81.
	(get_valid_dis386): Handle XOP_08.
	(OP_Vex_2src): New.
	* i386-gen.c (cpu_flag_init): Add CPU_XOP_FLAGS and CPU_CVT16_FLAGS.
	(cpu_flags): Add CpuXOP and CpuCVT16.
	(opcode_modifiers): Add XOP08, Vex2Sources.
	* i386-opc.h (CpuXOP): Added.
	(CpuCVT16): Added.
	(i386_cpu_flags): Add cpuxop and cpucvt16.
	(XOP08): Added.
	(Vex2Sources): Added.
	(i386_opcode_modifier): Add xop08, vex2sources.
	* i386-opc.tbl: Add entries for XOP and CVT16 instructions.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Regenerated.
 2009-11-18 04:04:17 +00:00
Nick Clifton
aefd8a406c * gas/arm/vfma1.d: Only run on ELF based targets. 
PR binutils/10924
        * gas/arm/arch4t-eabi.d: Update expected disassembly.
        * gas/arm/arch4t.d: Likewise.
        * gas/arm/archv6t2.d: Likewise.
        * gas/arm/arm7t.d: Likewise.
        * gas/arm/inst.d: Likewise.
        * gas/arm/xscale.d: Likewise.

        PR binutils/10924
        * arm-dis.c (arm_opcodes): Add patterns to match undefined LDRB
        instruction variants.  Add pattern for MRS variant that was being
        confused with CMP.
        (arm_decode_shift): Place error message in a comment.
        (print_insn_arm): Note that writing back to the PC is
        unpredictable.
        Only print 'p' variants of cmp/cmn/teq/tst instructions if
        decoding for pre-V6 architectures.
 2009-11-17 17:20:26 +00:00
Ramana Radhakrishnan
0bb027fd62 2009-11-17 Edward Nevill <edward.nevill@arm.com> 
* arm-dis.c (print_insn_thumb32): Handle undefined instruction.
 2009-11-17 10:43:09 +00:00
Doug Evans
c7e770a030 opcodes/ 
* Makefile.am (stamp-xc16x): Use ../cpu/xc16x.cpu instead of
	../cgen/cpu.
	* Makefile.in: Regenerate.

	cgen/
	* cpu/xc16x.cpu: Delete, use copy in ../cpu.
	* cpu/xc16x.opc: Ditto.
 2009-11-14 20:04:58 +00:00
H.J. Lu
8b3f93e7a1 2009-11-13 H.J. Lu <hongjiu.lu@intel.com> 
* i386-dis.c (OP_E_extended): Removed.
 2009-11-14 07:22:05 +00:00
H.J. Lu
2a70cca486 Check rex_ignored. 
gas/testsuite/

2009-11-13  H.J. Lu  <hongjiu.lu@intel.com>

	* gas/i386/rex.s: Add a test for VEX insn.
	* gas/i386/rex.d: Updated.

opcodes/

2009-11-13  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (print_insn): Check rex_ignored.
 2009-11-13 23:13:48 +00:00
H.J. Lu
f16cd0d502 Rewrite prefix processing. 
gas/testsuite/

2009-11-13  H.J. Lu  <hongjiu.lu@intel.com>

	* gas/i386/i386.exp: Run long-1, long-1-intel, x86-64-long-1,
	and x86-64-long-1-intel.

	* gas/i386/long-1-intel.d: New.
	* gas/i386/long-1.d: Likewise.
	* gas/i386/long-1.s: Likewise.
	* gas/i386/x86-64-long-1-intel.d: Likewise.
	* gas/i386/x86-64-long-1.d: Likewise.
	* gas/i386/x86-64-long-1.s: Likewise.

	* gas/i386/jump16.d: Updated for prefix processing.
	* gas/i386/naked.d: Likewise.
	* gas/i386/nops-1-core2.d: Likewise.
	* gas/i386/nops-1-i686.d: Likewise.
	* gas/i386/nops-3-i686.d: Likewise.
	* gas/i386/nops-4-i686.d: Likewise.
	* gas/i386/nops-5-i686.d: Likewise.
	* gas/i386/nops-5.d: Likewise.
	* gas/i386/prefix.d: Likewise.
	* gas/i386/rep.d: Likewise.
	* gas/i386/string-ok.d: Likewise.
	* gas/i386/x86-64-addr32-intel.d: Likewise.
	* gas/i386/x86-64-addr32.d: Likewise.
	* gas/i386/x86-64-cbw-intel.d: Likewise.
	* gas/i386/x86-64-cbw.d: Likewise.
	* gas/i386/x86-64-io-intel.d: Likewise.
	* gas/i386/x86-64-io-suffix.d: Likewise.
	* gas/i386/x86-64-io.d: Likewise.
	* gas/i386/x86-64-lwp.d: Likewise.
	* gas/i386/x86-64-nops-1-core2.d: Likewise.
	* gas/i386/x86-64-nops-1-nocona.d: Likewise.
	* gas/i386/x86-64-nops-1.d: Likewise.
	* gas/i386/x86-64-nops-2.d: Likewise.
	* gas/i386/x86-64-nops-3.d: Likewise.
	* gas/i386/x86-64-nops-4-core2.d: Likewise.
	* gas/i386/x86-64-nops-4.d: Likewise.
	* gas/i386/x86-64-nops-5-k8.d: Likewise.
	* gas/i386/x86-64-nops-5.d: Likewise.
	* gas/i386/x86-64-rep.d: Likewise.
	* gas/i386/x86-64-stack-intel.d: Likewise.
	* gas/i386/x86-64-stack-suffix.d: Likewise.
	* gas/i386/x86-64-stack.d: Likewise.

ld/testsuite/

2009-11-13  H.J. Lu  <hongjiu.lu@intel.com>

	* ld-x86-64/tlsbin.dd: Updated for prefix processing.
	* ld-x86-64/tlsgdesc.dd: Likewise.
	* ld-x86-64/tlsld1.dd: Likewise.
	* ld-x86-64/tlspic.dd: Likewise.

opcodes/

2009-11-13  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (ckprefix): Updated to return 0 if number of
	prefixes > 14 and record the last position for each prefix.
	(lock_prefix): Removed.
	(data_prefix): Likewise.
	(addr_prefix): Likewise.
	(repz_prefix): Likewise.
	(repnz_prefix): Likewise.
	(last_lock_prefix): New.
	(last_repz_prefix): Likewise.
	(last_repnz_prefix): Likewise.
	(last_data_prefix): Likewise.
	(last_addr_prefix): Likewise.
	(last_rex_prefix): Likewise.
	(last_seg_prefix): Likewise.
	(MAX_CODE_LENGTH): Likewise.
	(ADDR16_PREFIX): Likewise.
	(ADDR32_PREFIX): Likewise.
	(DATA16_PREFIX): Likewise.
	(DATA32_PREFIX): Likewise.
	(REP_PREFIX): Likewise.
	(seg_prefix): Likewise.
	(all_prefixes): Change size to MAX_CODE_LENGTH - 1.
	(prefix_name): Handle ADDR16_PREFIX, ADDR32_PREFIX,
	DATA16_PREFIX, DATA32_PREFIX and REP_PREFIX.
	(get_valid_dis386): Updated.
	(OP_C): Likewise.
	(OP_Monitor): Likewise.
	(REP_Fixup): Likewise.
	(print_insn): Display all prefixes.
	(putop): Set PREFIX_DATA on used_prefixes only if it is used.
	(intel_operand_size): Likewise.
	(OP_E_register): Likewise.
	(OP_G): Likewise.
	(OP_REG): Likewise.
	(OP_IMREG): Likewise.
	(OP_I): Likewise.
	(OP_I64): Likewise.
	(OP_sI): Likewise.
	(CRC32_Fixup): Likewise.
	(MOVBE_Fixup): Likewise.
	(OP_E_memory): Set REFIX_DATA on used_prefixes when it is used
	in 16bit mode.
	(OP_J): Set REX_W used if it is used. Set PREFIX_DATA on
	used_prefixes only if it is used.
 2009-11-13 20:42:10 +00:00
H.J. Lu
20efc68957 2009-11-12 H.J. Lu <hongjiu.lu@intel.com> 
* i386-opc.tbl: Remove IsLockable from add, adc, and, dec, inc,
	or, sbb, sub, xor and xchg with register only operands.
	* i386-tbl.h: Regenerated.
 2009-11-12 19:15:18 +00:00
H.J. Lu
c32fa91d70 gas/ 
2009-11-12  H.J. Lu  <hongjiu.lu@intel.com>

	* config/tc-i386.c (LOCKREP_PREFIX): Removed.
	(REP_PREFIX): New.
	(LOCK_PREFIX): Likewise.
	(PREFIX_GROUP): Likewise.
	(REX_PREFIX): Updated.
	(MAX_PREFIXES): Likewise.
	(add_prefix): Updated.  Return enum PREFIX_GROUP.
	(md_assemble): Check for lock without a lockable instruction.
	(parse_insn): Updated.
	(output_insn): Likewise.

gas/testsuite/

2009-11-12  H.J. Lu  <hongjiu.lu@intel.com>

	* gas/i386/i386.exp: Run lock-1, lock-1-intel, lockbad-1,
	x86-64-lock-1, x86-64-lock-1-intel and x86-64-lockbad-1.

	* gas/i386/lock-1-intel.d: New.
	* gas/i386/lock-1.d: Likewise.
	* gas/i386/lock-1.s: Likewise.
	* gas/i386/lockbad-1.l: Likewise.
	* gas/i386/lockbad-1.s: Likewise.
	* gas/i386/x86-64-lock-1-intel.d: Likewise.
	* gas/i386/x86-64-lock-1.d: Likewise.
	* gas/i386/x86-64-lock-1.s: Likewise.
	* gas/i386/x86-64-lockbad-1.l: Likewise.
	* gas/i386/x86-64-lockbad-1.s: Likewise.

opcodes/

2009-11-12  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-gen.c (opcode_modifiers): Add IsLockable.

	* i386-opc.h (IsLockable): New.
	(i386_opcode_modifier): Add islockable.

	* i386-opc.tbl: Add IsLockable to add, adc, and, btc, btr,
	bts, cmpxchg, cmpxch8b, dec, inc, neg, not, or, sbb, sub,
	xor, xadd and xchg.
	* i386-tbl.h: Regenerated.
 2009-11-12 18:57:14 +00:00
Daniel Jacobowitz
79862e4574 gas/testsuite/ 
* gas/arm/copro.d, gas/arm/fp-save.d, gas/arm/float.d,
	gas/arm/fpa-mem.d: Update for removed generic coprocessor instructions
	and expanded PC-relative offsets.

	opcodes/
	* arm-dis.c (coprocessor_opcodes): Use %A instead of %C.  Remove
	generic coprocessor instructions for FPA loads and stores.
	(print_insn_coprocessor): Remove %C support.  Display address for
	PC-relative offsets in %A.
 2009-11-12 14:49:45 +00:00
H.J. Lu
f310f33d50 gas/testsuite/ 
2009-11-11  H.J. Lu  <hongjiu.lu@intel.com>

	* gas/i386/prefix.d: Swap order of ADDR and REP prefixes.
	* gas/i386/rep.d: Likewise.
	* gas/i386/x86-64-rep.d: Likewise.

opcodes/

2009-11-11  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (all_prefixes): New.
	(ckprefix): Set all_prefixes.
	(print_insn): Print all_prefixes instead of lock_prefix,
	repz_prefix, repnz_prefix, addr_prefix and data_prefix.
 2009-11-12 02:13:06 +00:00
Nick Clifton
c1e2689731 PR binutils/10924 
* arm-dis.c (UNPREDICTABLE_INSTRUCTION): New macro.
        (print_insn_arm): Extend %s format control code to check for
        unpredictable addressing modes.  Add support for %S format control
        code which suppresses this check.
        (W_BIT, I_BIT, U_BIT, P_BIT): New macros.
        (WRITEBACK_BIT_SET, IMMEDIATE_BIT_SET, NEGATIVE_BIT_SET,
        PRE_BIT_SET): New macros.
        (print_insn_coprocessor): Use the new macros instead of magic
        constants.
        (print_arm_address): Likewise.
        (pirnt_insn_arm): Likewise.
        (print_insn_thumb32): Likewise.
 2009-11-11 09:44:45 +00:00
Nick Clifton
41327c9d6d Updated Indonesian translation. 2009-11-11 09:36:08 +00:00
Maxim Kuvyrkov
0d999f3337 * config/m68k-parse.h (enum m68k_register): Add ACR[4-7], RGPIOBAR. 
* config/tc-m68k.c (mcf5206_ctrl): Fix whitespace.
	(mcf52223_ctrl): Remove non-existent registers.
	(mcf54418): Define.
	(mcf54455): Remove MBAR.
	(m68k_cpus): Add lines for MCF5441x family.
	(m68k_ip, init_table): Handle RGPIOBAR, ACR[4-7].

	* m68k-dis.c (print_insn_arg): Handle RGPIOBAR, ACR[4-7] and MBAR[01].
 2009-11-10 18:05:24 +00:00
Sebastian Pop
c48244a521 2009-11-06 Sebastian Pop <sebastian.pop@amd.com> 
* opcodes/i386-dis.c (reg_table): Add XOP_8F_TABLE (XOP_09) to
	reg_table[REG_8F][1]: for XOP instructions, ModRM.reg first points to
	B.mm in the RXB.mmmmm byte, and so when B is set, we still should use
	the xop_table.
	(get_valid_dis386): Removed unused condition (from cut/n/paste) for
	XOP instructions.

	* gas/testsuite/gas/i386/x86-64-lwp.s: Updated to also contain
	patterns with r[8-15] registers.
	* gas/testsuite/gas/i386/x86-64-lwp.d: Same.
 2009-11-06 23:17:26 +00:00
Sebastian Pop
f88c9eb030 2009-11-05 Sebastian Pop <sebastian.pop@amd.com> 
Quentin Neill  <quentin.neill@amd.com>

	* gas/config/tc-i386.c (cpu_arch): Add CPU_LWP_FLAGS.
	(build_vex_prefix): Handle xop09 and xop0a.
	(build_modrm_byte): Handle vexlwp.
	(md_show_usage): Add lwp.
	* gas/doc/c-i386.texi (i386-LWP): New section.

	* gas/testsuite/gas/i386/i386.exp: Run x86-64-lwp in 64-bit mode,
	run lwp in 32-bit mode.
	* gas/testsuite/gas/i386/x86-64-lwp.d: New.
	* gas/testsuite/gas/i386/x86-64-lwp.s: New.
	* gas/testsuite/gas/i386/lwp.d: New.
	* gas/testsuite/gas/i386/lwp.s: New.

	* opcodes/i386-dis.c (OP_LWPCB_E): New.
	(OP_LWP_E): New.
	(OP_LWP_I): New.
	(USE_XOP_8F_TABLE): New.
	(XOP_8F_TABLE): New.
	(REG_XOP_LWPCB): New.
	(REG_XOP_LWP): New.
	(XOP_09): New.
	(XOP_0A): New.
	(reg_table): Redirect REG_8F to XOP_8F_TABLE.
	Add entries for REG_XOP_LWPCB and REG_XOP_LWP.
	(xop_table): New.
	(get_valid_dis386): Handle USE_XOP_8F_TABLE.
	Use the offsets VEX_0F, VEX_0F38, and VEX_0F3A instead of their values
	to access to the vex_table.
	(OP_LWPCB_E): New.
	(OP_LWP_E): New.
	(OP_LWP_I): New.
	* opcodes/i386-gen.c (cpu_flag_init): Add CPU_LWP_FLAGS, CpuLWP.
	(cpu_flags): Add CpuLWP.
	(opcode_modifiers): Add VexLWP, XOP09, and XOP0A.
	* opcodes/i386-opc.h (CpuLWP): New.
	(i386_cpu_flags): Add bit cpulwp.
	(VexLWP): New.
	(XOP09): New.
	(XOP0A): New.
	(i386_opcode_modifier): Add vexlwp, xop09, and xop0a.
	* opcodes/i386-opc.tbl (llwpcb): Added.
	(lwpval): Added.
	(lwpins): Added.
 2009-11-05 23:40:05 +00:00
DJ Delorie
0d734b5d06 [opcodes] 
* rx-decode.opc (rx_decode_opcode) (mvtipl): Add.
	(mvtcp, mvfcp, opecp): Remove.
	* rx-decode.c: Regenerate.
	* rx-dis.c (cpen): Remove.

[gas]
	* config/rx-parse.y (MVTIPL): Update bit pattern.
	(cpen): Remove.

[include/opcode]
	* rx.h (rx_decode_opcode) (mvtipl): Add.
	(mvtcp, mvfcp, opecp): Remove.
 2009-11-05 00:38:45 +00:00
Doug Evans
d51b88d344 * m32c-desc.c: Regenerate. 
* mep-desc.c: Regenerate.
 2009-11-04 06:18:27 +00:00
Paul Brook
62f3b8c867 2009-11-02 Paul Brook <paul@codesourcery.com> 
ld/testsuite/
	* ld-arm/arm-elf.exp: Add new attr-merge-vfp tests.
	* ld-arm/attr-merge-vfp-1.d: New test.
	* ld-arm/attr-merge-vfp-1r.d: New test.
	* ld-arm/attr-merge-vfp-2.d: New test.
	* ld-arm/attr-merge-vfp-2r.d: New test.
	* ld-arm/attr-merge-vfp-3.d: New test.
	* ld-arm/attr-merge-vfp-3r.d: New test.
	* ld-arm/attr-merge-vfp-4.d: New test.
	* ld-arm/attr-merge-vfp-4r.d: New test.
	* ld-arm/attr-merge-vfp-5.d: New test.
	* ld-arm/attr-merge-vfp-5r.d: New test.
	* ld-arm/attr-merge-vfp-2.s: New test.
	* ld-arm/attr-merge-vfp-3.s: New test.
	* ld-arm/attr-merge-vfp-3-d16.s: New test.
	* ld-arm/attr-merge-vfp-4.s: New test.
	* ld-arm/attr-merge-vfp-4-d16.s: New test.

	gas/
	* doc/c-arm.texi: Document new -mfpu options.
	* config/tc-arm.c (fpu_vfp_ext_v3xd, fpu_vfp_fp16, fpu_neon_ext_fma,
	fpu_vfp_ext_fma): New.
	(NEON_ENC_TAB): Add vfma, vfms, vfnma and vfnms.
	(do_vfp_nsyn_fma_fms, do_neon_fmac): New functions.
	(insns): Move double precision load/store.  Split out double
	precision VFPv3 instrucitons.  Add VFPv4 instructions.
	(arm_fpus): Add VFPv3-FP16, VFPv3xD and VFPv4 variants.
	(aeabi_set_public_attributes): Set VFPv4 variants

	gas/testsuite/
	* gas/arm/attr-mfpu-vfpv4.d: New test.
	* gas/arm/attr-mfpu-vfpv4-d16.d: New test.
	* gas/arm/neon-fma-cov.d: New test.
	* gas/arm/neon-fma-cov.s: New test.
	* gas/arm/vfp-fma-inc.s: New test.
	* gas/arm/vfp-fma-arm.d: New test.
	* gas/arm/vfp-fma-arm.s: New test.
	* gas/arm/vfp-fma-thumb.d: New test.
	* gas/arm/vfp-fma-thumb.s: New test.
	* gas/arm/vfma1.d: New test.
	* gas/arm/vfma1.s: New test.
	* gas/arm/vfpv3xd.d: New test.
	* gas/arm/vfpv3xd.s: New test.

	include/opcode/
	* arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
	FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
	(FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
	FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
	FPU_ARCH_NEON_VFP_V4): Define.

	binutils/
	* readelf.c (arm_attr_tag_VFP_arch): Add VFPv4 and VFPv4-D16.

	bfd/
	* elf32-arm.c (elf32_arm_merge_eabi_attributes): Handle VFPv4
	attributes.

	opcodes/
	* arm-dis.c (coprocessor_opcodes): Update to use new feature flags.
	Add VFPv4 instructions.
 2009-11-02 13:44:05 +00:00
H.J. Lu
206c2556c2 gas/ 
2009-10-29  Sebastian Pop  <sebastian.pop@amd.com>

	* config/tc-i386.c (build_modrm_byte): Do not swap REG and
	NDS operands for FMA4.

gas/testsuite/

2009-10-29  Sebastian Pop  <sebastian.pop@amd.com>

	* gas/i386/fma4.d: Updated patterns.
	* gas/i386/x86-64-fma4.d: Same.

opcodes/

2009-10-29  Sebastian Pop  <sebastian.pop@amd.com>

	* i386-dis.c (OP_VEX_FMA): Removed.
	(VexFMA): Removed.
	(Vex128FMA): Removed.
	(prefix_table): First source operand of FMA4 insns is decoded
	with Vex not with VexFMA.
	(OP_EX_VexW): Second source operand is decoded with get_vex_imm8
	when vex.w is set.  Third source operand is decoded with
	get_vex_imm8 when vex.w is cleared.
	(OP_VEX_FMA): Removed.
 2009-10-29 22:22:59 +00:00
Alan Modra
a2b2318d99 * Makefile.am (HFILES): Remove cgen-ops.h and cgen-types.h. 2009-10-27 01:49:26 +00:00
Doug Evans
ac1e9eca70 cpu/ 
* m32c.opc (opc.h): cgen-types.h -> cgen/basic-modes.h.
	cgen-ops.h -> cgen/basic-ops.h.

	include/opcode/
	* cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
	* cgen.h: Update.  Improve multi-inclusion macro name.

	include/cgen/
	* basic-modes.h: New file.  Moved here from opcodes/cgen-types.h.
	* basic-ops.h: New file.  Moved here from opcodes/cgen-ops.h.
	* bitset.h: New file.  Moved here from ../opcode/cgen-bitset.h.
	Update license to GPL v3.

	opcodes/
	* cgen-ops.h: Delete, moved to ../include/cgen/basic-ops.h.
	* cgen-types.h: Delete, moved to ../include/cgen/basic-modes.h.
	* cgen-bitset.c: Update.
	* fr30-desc.h: Regenerate.
	* frv-desc.h: Regenerate.
	* ip2k-desc.h: Regenerate.
	* iq2000-desc.h: Regenerate.
	* lm32-desc.h: Regenerate.
	* m32c-desc.h: Regenerate.
	* m32c-opc.h: Regenerate.
	* m32r-desc.h: Regenerate.
	* mep-desc.h: Regenerate.
	* mt-desc.h: Regenerate.
	* openrisc-desc.h: Regenerate.
	* xc16x-desc.h: Regenerate.
	* xstormy16-desc.h: Regenerate.
 2009-10-24 00:17:08 +00:00
DJ Delorie
f282425ecd * rx-decode.opc (decode_opcode): Fix flags for MUL, SUNTIL, and SWHILE. 
* rx-decode.c: Regenerated.
 2009-10-23 01:11:53 +00:00
H.J. Lu
4b06377fcc gas/ 
2009-10-20  H.J. Lu  <hongjiu.lu@intel.com>

	PR gas/10775
	* doc/c-i386.texi: Mention movabs.

gas/testsuite/

2009-10-20  H.J. Lu  <hongjiu.lu@intel.com>

	PR gas/10775
	* gas/i386/immed64.d: Updated.
	* gas/i386/l1om.d: Likewise.
	* gas/i386/x86-64-disp-intel.d: Likewise.
	* gas/i386/x86-64-disp.d: Likewise.
	* gas/i386/x86_64.d: Likewise.

opcodes/

2009-10-20  H.J. Lu  <hongjiu.lu@intel.com>

	PR gas/10775
	* i386-dis.c: Document LB, LS and LV macros.
	(dis386): Use mov%LB, mov%LS and mov%LV on mov instruction
	with the 64-bit displacement or immediate operand.
	(putop): Handle LB, LS and LV macros.
 2009-10-20 22:18:19 +00:00
Doug Evans
cedb97b6d0 * lm32-opinst.c: Regenerate. 
* m32c-desc.c: Regenerate.
	* m32r-opinst.c: Regenerate.
	* openrisc-ibld.c: Regenerate.
	* xc16x-desc.c: Regenerate.
	* xc16x-desc.h: Regenerate.
 2009-10-19 05:09:44 +00:00
Doug Evans
d1119f7a8c * Makefile.am (CGEN_CPUS): Add iq2000, lm32. 
(FR30_DEPS, FRV_DEPS, IQ2000_DEPS): Move so all cgen *_DEPS are
	sorted alphabetically.
	(stamp-fr30, stamp-frv, stamp-iq2000, stamp-xc16x): Move so all cgen
	stamp-* rules are sorted alphabetically.
	* Makefile.in: Regenerate.
 2009-10-17 17:38:09 +00:00
H.J. Lu
52a6c1fedd 2009-10-16 H.J. Lu <hongjiu.lu@intel.com> 
* i386-opc.h: Use enum instead of nested macros.
 2009-10-16 15:50:52 +00:00
H.J. Lu
3873ba1230 2009-10-16 H.J. Lu <hongjiu.lu@intel.com> 
* i386-dis.c: Simplify enums.
 2009-10-16 14:47:08 +00:00
H.J. Lu
51e7da1b40 2009-10-15 H.J. Lu <hongjiu.lu@intel.com> 
Ineiev <ineiev@gmail.com>

	PR binutils/10767
	* i386-dis.c: Use enum instead of nested macros.
 2009-10-15 22:50:09 +00:00
H.J. Lu
c39846ed0a 2009-10-15 H.J. Lu <hongjiu.lu@intel.com> 
* i386-dis.c (MAX_BYTEMODE): Removed.
 2009-10-15 22:26:55 +00:00
Alan Modra
6a327e170e PR 969 
* m68k-opc.c (m68k_opcodes): Correct mask for macl and msacl.
 2009-10-14 11:30:20 +00:00
H.J. Lu
55b126d49c 2009-10-13 H.J. Lu <hongjiu.lu@intel.com> 
* i386-dis.c (print_insn): Always clear need_vex, need_vex_reg
	and vex_w_done.
 2009-10-13 18:44:19 +00:00
Michael Eager
ef29941507 * opcodes/microblaze-dis.c: Add include for microblaze-dis.h, 
eliminate local extern decls.
* opcodes/microblaze-dis.h: New.
 2009-10-07 15:40:17 +00:00
Nick Clifton
245caaea22 Updated Finnish translation 2009-10-06 15:44:40 +00:00
Nick Clifton
49293ef70b * opc2c.c: Include "libiberty.h" and <errno.h>. 
(orig_filename): Constify.
        (dump_lines): Fix line number directive.
        (main): Set orig_filename to basename of input file.  Use
        xstrerror.

        * Makefile.am (rx-dis.lo): Remove explicit dependencies.
        ($(srcdir)/rx-decode.c): Use @MAINT@.  Use $(EXEEXT_FOR_BUILD)
        instead of $(EXEEXT).
        (opc2c$(EXEEXT_FOR_BUILD)): Renamed from opc2c$(EXEEXT) and use
        $(LINK_FOR_BUILD).  Link with libiberty.
        (MOSTLYCLEANFILES): Add opc2c$(EXEEXT_FOR_BUILD).
        (MAINTAINERCLEANFILES): Add $(srcdir)/rx-decode.c.
        * Makefile.in: Regenerated.
        * rx-decode.c: Regenerated.
 2009-10-05 13:14:55 +00:00
H.J. Lu
caeec88ad4 Revert the last change. 2009-10-03 17:00:16 +00:00
H.J. Lu
ac845c8691 2009-10-03 H.J. Lu <hongjiu.lu@intel.com> 
* Makefile.am ($(srcdir)/rx-decode.c): Add @MAINT@.
	(rx-dis.lo): Remove a space.
	(pc2c$(EXEEXT)): Remove a space. Use $(LINK_FOR_BUILD) instead
	of gcc.
	(MAINTAINERCLEANFILES): Add $(srcdir)/rx-decode.c.
	* Makefile.in: Regenerated.
 2009-10-03 14:36:34 +00:00
Alan Modra
8977d4b219 * arm-dis.c (print_insn): Check symtab_size not *symtab. 2009-10-03 00:39:53 +00:00
H.J. Lu
f98fa53424 2009-10-02 H.J. Lu <hongjiu.lu@intel.com> 
* i386-opc.tbl: Drop Disp64 on jump and loop instructions.
	* i386-tbl.h: Regenerated.
 2009-10-02 19:03:40 +00:00
Alan Modra
e0c483d688 typo fix 2009-10-02 15:35:01 +00:00
Peter Bergner
9fe54b1ca1 gas/ 
* config/tc-ppc.c (md_show_usage): Document -m476.
	* doc/c-ppc.texi (PowerPC-Opts): Document -m476.

gas/testsuite/
	* gas/ppc/476.s: New test.
	* gas/ppc/476.d: Likewise.
	* gas/ppc/ppc.exp: Run the 476 test.

include/opcode/
	* ppc.h (PPC_OPCODE_476): Define.

opcodes/
	* ppc-dis.c (ppc_opts): Add "476" entry.
	* ppc-opc.c (PPC476): Define.
	(powerpc_opcodes): Update mnemonics where required for 476.
 2009-10-02 14:42:42 +00:00
Peter Bergner
634b50f2a6 gas/ 
* config/tc-ppc.c (md_show_usage): Rename "ppca2" to "a2".
	* doc/c-ppc.texi (PowerPC-Opts): Likewise.

gas/testsuite/
	* gas/ppc/a2.d: Rename "ppca2" to "a2".

include/opcode/
	* ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.

opcodes/
	* ppc-opc.c (PPCA2): Use renamed mask PPC_OPCODE_A2.
	* ppc-dis.c (ppc_opts): Likewise.
	Rename "ppca2" to "a2".
 2009-10-01 19:24:48 +00:00
M R Swami Reddy
4ded9dda7c 2009-10-01 M R Swami Reddy <MR.Swami.Reddy@nsc.com> 
* crx-dis.c (match_opcode): Truncate mcode to 32-bit.
 2009-10-01 08:19:55 +00:00