Add support for ColdFire MAC instructions and tidy up support for other m68k
variants.
This commit is contained in:
Nick Clifton
parent
69b975477d
commit
fd99574ba5
20 changed files with 20250 additions and 153 deletions
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@ -1,3 +1,9 @@
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2004-04-22 Peter Barada <peter@the-baradas.com>
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* archures.c: Add bfd_mach_mcfv4e to bfd_architecture.
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* bfd2-in.h: Regenerate.
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* cpu-m68k.c: Add 'm68k:mcfv4e' to arch_info_struct[].
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2004-04-21 Chris Demetriou <cgd@broadcom.com>
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* coff-mips.c (bfd_mips_ecoff_create_embedded_relocs): Remove.
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@ -85,6 +85,7 @@ DESCRIPTION
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.#define bfd_mach_mcf5307 11
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.#define bfd_mach_mcf5407 12
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.#define bfd_mach_mcf528x 13
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.#define bfd_mach_mcfv4e 14
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. bfd_arch_vax, {* DEC Vax *}
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. bfd_arch_i960, {* Intel 960 *}
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. {* The order of the following is important.
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@ -1491,6 +1491,7 @@ enum bfd_architecture
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#define bfd_mach_mcf5307 11
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#define bfd_mach_mcf5407 12
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#define bfd_mach_mcf528x 13
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#define bfd_mach_mcfv4e 14
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bfd_arch_vax, /* DEC Vax */
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bfd_arch_i960, /* Intel 960 */
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/* The order of the following is important.
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@ -1,6 +1,6 @@
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/* BFD library support routines for architectures.
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Copyright 1990, 1991, 1992, 1993, 1994, 1997, 1998, 2000, 2001, 2002,
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2003 Free Software Foundation, Inc.
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2003, 2004 Free Software Foundation, Inc.
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Hacked by Steve Chamberlain of Cygnus Support.
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This file is part of BFD, the Binary File Descriptor library.
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@ -40,7 +40,8 @@ static const bfd_arch_info_type arch_info_struct[] =
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N(bfd_mach_mcf5307, "m68k:5307", FALSE, &arch_info_struct[10]),
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N(bfd_mach_mcf5407, "m68k:5407", FALSE, &arch_info_struct[11]),
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N(bfd_mach_m68060, "m68k:68060", FALSE, &arch_info_struct[12]),
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N(bfd_mach_mcf528x, "m68k:528x", FALSE, 0),
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N(bfd_mach_mcf528x, "m68k:528x", FALSE, &arch_info_struct[13]),
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N(bfd_mach_mcfv4e, "m68k:cfv4e", FALSE, 0),
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};
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const bfd_arch_info_type bfd_m68k_arch =
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@ -1,3 +1,23 @@
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2004-04-22 Peter Barada <peter@the-baradas.com>
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* NEWS: Added support for EMAC instructions and MAC/EMAC
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Motorola syntax.
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* config/m68k-parse.h: Add ACC[123], ACCEXT{01,23}, MAC/EMAC
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scale factor tokens, trailing_ampersand to mark mask addressing
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for MAC/EMAC instructions.
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* config/m68k-parse.y: Add options_ampersand clause, '<<',
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'>>'.
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(yylex): Handle '>', '<', and '&' following '+'.
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* config/tc-m68k.c: Set mcfmac/mcfemac on appropriate ColdFire
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architectures in archs[].
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(m68k-ip): Add '4', 'e', 'g', 'i', cases to handle mask addressing
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for MAC/EMAC instructions, ACC[0123], ACCEXT{01,23}, and '<<'/'>>'
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respectively.
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(m68k_ip): Handle trailing '&' on MAC/EMAC insns.
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(install_operand): Fix 'n' case, Add 'F', 'f', 'G', 'H', 'I', ']'
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cases.
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Add EMAC operands to init_table[].
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2004-04-22 Bruno De Bus <bdebus@elis.ugent.be>
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* config/tc-arm.h (enum mstate): Move here, add MAP_UNDEFINED
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3
gas/NEWS
3
gas/NEWS
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@ -1,5 +1,8 @@
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-*- text -*-
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* Support for ColdFire EMAC instructions added and Motorola syntax for MAC/EMAC
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instrucitons.
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* The MIPS -membedded-pic option (Embedded-PIC code generation) is
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deprecated and will be removed in a future release.
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@ -1,6 +1,6 @@
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/* m68k-parse.h -- header file for m68k assembler
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Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1999, 2000,
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2003 Free Software Foundation, Inc.
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2003, 2004 Free Software Foundation, Inc.
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This file is part of GAS, the GNU Assembler.
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@ -84,7 +84,12 @@ enum m68k_register
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ZPC, /* Hack for Program space, but 0 addressing */
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SR, /* Status Reg */
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CCR, /* Condition code Reg */
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ACC, /* Accumulator Reg */
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ACC, /* Accumulator Reg0 (EMAC or ACC on MAC). */
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ACC1, /* Accumulator Reg 1 (EMAC). */
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ACC2, /* Accumulator Reg 2 (EMAC). */
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ACC3, /* Accumulator Reg 3 (EMAC). */
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ACCEXT01, /* Accumulator extension 0&1 (EMAC). */
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ACCEXT23, /* Accumulator extension 2&3 (EMAC). */
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MACSR, /* MAC Status Reg */
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MASK, /* Modulus Reg */
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@ -295,6 +300,8 @@ enum m68k_operand_type
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BASE,
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POST,
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PRE,
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LSH, /* MAC/EMAC scalefactor '<<'. */
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RSH, /* MAC/EMAC scalefactor '>>'. */
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REGLST
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};
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@ -322,6 +329,9 @@ struct m68k_op
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/* The outer displacement. */
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struct m68k_exp odisp;
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/* Is a trailing '&' added to an <ea>? (for MAC/EMAC mask addressing). */
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int trailing_ampersand;
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};
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#endif /* ! defined (M68K_PARSE_H) */
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@ -98,6 +98,7 @@ static struct m68k_op *op;
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struct m68k_exp exp;
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unsigned long mask;
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int onereg;
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int trailing_ampersand;
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}
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%token <reg> DR AR FPR FPCR LPC ZAR ZDR LZPC CREG
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@ -109,6 +110,7 @@ static struct m68k_op *op;
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%type <exp> optcexpr optexprc
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%type <mask> reglist ireglist reglistpair
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%type <onereg> reglistreg
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%type <trailing_ampersand> optional_ampersand
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%%
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@ -116,14 +118,35 @@ static struct m68k_op *op;
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operand:
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generic_operand
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| motorola_operand
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| motorola_operand optional_ampersand
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{
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op->trailing_ampersand = $2;
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}
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| mit_operand
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;
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/* A trailing ampersand(for MAC/EMAC mask addressing). */
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optional_ampersand:
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/* empty */
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{ $$ = 0; }
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| '&'
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{ $$ = 1; }
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;
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/* A generic operand. */
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generic_operand:
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DR
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'<' '<'
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{
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op->mode = LSH;
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}
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| '>' '>'
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{
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op->mode = RSH;
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}
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| DR
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{
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op->mode = DREG;
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op->reg = $1;
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@ -757,12 +780,14 @@ yylex ()
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case '/':
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case '[':
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case ']':
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case '<':
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case '>':
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return *str++;
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case '+':
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/* It so happens that a '+' can only appear at the end of an
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operand. If it appears anywhere else, it must be a unary
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plus on an expression. */
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if (str[1] == '\0')
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operand, or if it is trailed by an '&'(see mac load insn).
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If it appears anywhere else, it must be a unary. */
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if (str[1] == '\0' || (str[1] == '&' && str[2] == '\0'))
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return *str++;
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break;
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case '-':
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@ -382,10 +382,10 @@ static const struct m68k_cpu archs[] =
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{ m68851, "68851", 0 },
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{ mcf5200, "5200", 0 },
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{ mcf5206e, "5206e", 0 },
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{ mcf528x, "528x", 0 },
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{ mcf5307, "5307", 0 },
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{ mcf5407, "5407", 0 },
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{ mcfv4e, "cfv4e", 0 },
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{ mcf528x|mcfmac, "528x", 0 },
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{ mcf5307|mcfmac, "5307", 0 },
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{ mcf5407|mcfmac, "5407", 0 },
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{ mcfv4e|mcfemac, "cfv4e", 0 },
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/* Aliases (effectively, so far as gas is concerned) for the above
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cpus. */
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{ m68020, "68k", 1 },
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@ -416,7 +416,7 @@ static const struct m68k_cpu archs[] =
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{ mcf5200, "5202", 1 },
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{ mcf5200, "5204", 1 },
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{ mcf5200, "5206", 1 },
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{ mcf5407, "cfv4", 1 },
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{ mcf5407|mcfmac, "cfv4", 1 },
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};
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static const int n_archs = sizeof (archs) / sizeof (archs[0]);
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@ -1505,6 +1505,14 @@ m68k_ip (instring)
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++losing;
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break;
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case '4':
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if (opP->mode != AINDR && opP->mode != AINC && opP->mode != ADEC
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&& (opP->mode != DISP
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|| opP->reg < ADDR0
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|| opP->reg > ADDR7))
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++losing;
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break;
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case 'B': /* FOO */
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if (opP->mode != ABSL
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|| (flag_long_jumps
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@ -1552,6 +1560,12 @@ m68k_ip (instring)
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losing++;
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break;
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case 'e':
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if (opP->reg != ACC && opP->reg != ACC1
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&& opP->reg != ACC2 && opP->reg != ACC3)
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losing++;
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break;
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case 'F':
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if (opP->mode != FPREG)
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losing++;
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@ -1562,6 +1576,11 @@ m68k_ip (instring)
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losing++;
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break;
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case 'g':
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if (opP->reg != ACCEXT01 && opP->reg != ACCEXT23)
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losing++;
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break;
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case 'H':
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if (opP->reg != MASK)
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losing++;
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@ -1574,6 +1593,11 @@ m68k_ip (instring)
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losing++;
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break;
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case 'i':
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if (opP->mode != LSH && opP->mode != RSH)
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losing++;
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break;
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case 'J':
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if (opP->mode != CONTROL
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|| opP->reg < USP
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@ -1994,6 +2018,7 @@ m68k_ip (instring)
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case 'w':
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case 'y':
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case 'z':
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case '4':
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#ifndef NO_68851
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case '|':
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#endif
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@ -2519,6 +2544,16 @@ m68k_ip (instring)
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as_bad (_("unknown/incorrect operand"));
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/* abort (); */
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}
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/* If s[0] is '4', then this is for the mac instructions
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that can have a trailing_ampersand set. If so, set 0x100
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bit on tmpreg so install_gen_operand can check for it and
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set the appropriate bit (word2, bit 5). */
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if (s[0] == '4')
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{
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if (opP->trailing_ampersand)
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tmpreg |= 0x100;
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}
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install_gen_operand (s[1], tmpreg);
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break;
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@ -2737,6 +2772,10 @@ m68k_ip (instring)
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install_operand (s[1], opP->reg - DATA);
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break;
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case 'e': /* EMAC ACCx, reg/reg. */
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install_operand (s[1], opP->reg - ACC);
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break;
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case 'E': /* Ignore it. */
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break;
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@ -2744,6 +2783,10 @@ m68k_ip (instring)
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install_operand (s[1], opP->reg - FP0);
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break;
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case 'g': /* EMAC ACCEXTx. */
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install_operand (s[1], opP->reg - ACCEXT01);
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break;
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case 'G': /* Ignore it. */
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case 'H':
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break;
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@ -2753,6 +2796,10 @@ m68k_ip (instring)
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install_operand (s[1], tmpreg);
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break;
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case 'i': /* MAC/EMAC scale factor. */
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install_operand (s[1], opP->mode == LSH ? 0x1 : 0x3);
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break;
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case 'J': /* JF foo. */
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switch (opP->reg)
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{
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@ -3286,25 +3333,46 @@ install_operand (mode, val)
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the_ins.opcode[0] |= ((val & 0x7) << 9);
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the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
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break;
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case 'n':
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case 'n': /* MAC/EMAC Rx on !load. */
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the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
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the_ins.opcode[0] |= ((val & 0x7) << 9);
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the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
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break;
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case 'o':
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case 'o': /* MAC/EMAC Rx on load. */
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the_ins.opcode[1] |= val << 12;
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the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
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break;
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case 'M':
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case 'M': /* MAC/EMAC Ry on !load. */
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the_ins.opcode[0] |= (val & 0xF);
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the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
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break;
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case 'N':
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case 'N': /* MAC/EMAC Ry on load. */
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the_ins.opcode[1] |= (val & 0xF);
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the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
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break;
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case 'h':
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the_ins.opcode[1] |= ((val != 1) << 10);
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break;
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case 'F':
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the_ins.opcode[0] |= ((val & 0x3) << 9);
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break;
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case 'f':
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the_ins.opcode[0] |= ((val & 0x3) << 0);
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break;
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case 'G':
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the_ins.opcode[0] |= ((~val & 0x1) << 7);
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the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
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break;
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case 'H':
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the_ins.opcode[0] |= ((val & 0x1) << 7);
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the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
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break;
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case 'I':
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the_ins.opcode[1] |= ((val & 0x3) << 9);
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break;
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case ']':
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the_ins.opcode[0] |= (val & 0x1) <<10;
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break;
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case 'c':
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default:
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as_fatal (_("failed sanity check."));
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@ -3318,6 +3386,11 @@ install_gen_operand (mode, val)
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{
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switch (mode)
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{
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case '/': /* Special for mask loads for mac/msac insns with
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possible mask; trailing_ampersend set in bit 8. */
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the_ins.opcode[0] |= (val & 0x3f);
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the_ins.opcode[1] |= (((val & 0x100) >> 8) << 5);
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break;
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case 's':
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the_ins.opcode[0] |= val;
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break;
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@ -3507,6 +3580,12 @@ static const struct init_entry init_table[] =
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{ "cc", CCR },
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{ "acc", ACC },
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{ "acc0", ACC },
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{ "acc1", ACC1 },
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{ "acc2", ACC2 },
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{ "acc3", ACC3 },
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{ "accext01", ACCEXT01 },
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{ "accext23", ACCEXT23 },
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{ "macsr", MACSR },
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{ "mask", MASK },
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@ -1,3 +1,11 @@
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2004-04-22 Peter Barada <peter@the-baradas.com>
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* gas/m68k/mcf-mac.s: New test: Check ColdFire MAC instructions.
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* gas/m68k/mcf-emac.s: New test: Similar checks.
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* gas/m68k/mcf-mac.d: New test: Expected output.
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* gas/m68k/mcf-emac.d: New test: Likewise.
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* gas/m68k/all.exp: Run new tests.
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2004-04-21 Chris Demetriou <cgd@broadcom.com>
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* gas/mips/elempic.d: File removed as part of -membedded-pic removal.
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@ -35,6 +35,8 @@ if [istarget m68*-*-*] then {
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run_dump_test link
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run_dump_test fmoveml
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run_dump_test mcf-mov3q
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run_dump_test mcf-mac
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run_dump_test mcf-emac
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set testname "68000 operands"
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gas_run "operands.s" "-m68000" "2>err.out"
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|
|||
6538
gas/testsuite/gas/m68k/mcf-emac.d
Normal file
6538
gas/testsuite/gas/m68k/mcf-emac.d
Normal file
File diff suppressed because it is too large
Load diff
6660
gas/testsuite/gas/m68k/mcf-emac.s
Normal file
6660
gas/testsuite/gas/m68k/mcf-emac.s
Normal file
File diff suppressed because it is too large
Load diff
3325
gas/testsuite/gas/m68k/mcf-mac.d
Normal file
3325
gas/testsuite/gas/m68k/mcf-mac.d
Normal file
File diff suppressed because it is too large
Load diff
3331
gas/testsuite/gas/m68k/mcf-mac.s
Normal file
3331
gas/testsuite/gas/m68k/mcf-mac.s
Normal file
File diff suppressed because it is too large
Load diff
|
|
@ -1,3 +1,11 @@
|
|||
2004-04-22 Peter Barada <peter@the-baradas.com>
|
||||
|
||||
* m68k.h: Add mcfmac/mcfemac definitions. Update operand
|
||||
descriptions for new EMAC cases.
|
||||
Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
|
||||
handle Motorola MAC syntax.
|
||||
Allow disassembly of ColdFire V4e object files.
|
||||
|
||||
2004-03-16 Alan Modra <amodra@bigpond.net.au>
|
||||
|
||||
* ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
/* Opcode table header for m680[01234]0/m6888[12]/m68851.
|
||||
Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1999, 2001,
|
||||
2003 Free Software Foundation, Inc.
|
||||
2003, 2004 Free Software Foundation, Inc.
|
||||
|
||||
This file is part of GDB, GAS, and the GNU binutils.
|
||||
|
||||
|
|
@ -42,6 +42,8 @@
|
|||
#define mcf5407 0x1000
|
||||
#define mcfv4e 0x2000
|
||||
#define mcf528x 0x4000
|
||||
#define mcfmac 0x8000
|
||||
#define mcfemac 0x10000
|
||||
|
||||
/* Handy aliases. */
|
||||
#define m68040up (m68040 | m68060)
|
||||
|
|
@ -99,7 +101,7 @@ struct m68k_opcode_alias
|
|||
operand; the second, the place it is stored. */
|
||||
|
||||
/* Kinds of operands:
|
||||
Characters used: AaBbCcDdEFfGHIJkLlMmnOopQqRrSsTtU VvWwXxYyZz0123|*~%;@!&$?/<>#^+-
|
||||
Characters used: AaBbCcDdEeFfGgHIiJkLlMmnOopQqRrSsTtU VvWwXxYyZz01234|*~%;@!&$?/<>#^+-
|
||||
|
||||
D data register only. Stored as 3 bits.
|
||||
A address register only. Stored as 3 bits.
|
||||
|
|
@ -133,9 +135,12 @@ struct m68k_opcode_alias
|
|||
C the CCR. No need to store it; this is just for filtering validity.
|
||||
S the SR. No need to store, just as with CCR.
|
||||
U the USP. No need to store, just as with CCR.
|
||||
E the ACC. No need to store, just as with CCR.
|
||||
G the MACSR. No need to store, just as with CCR.
|
||||
E the MAC ACC. No need to store, just as with CCR.
|
||||
e the EMAC ACC[0123].
|
||||
G the MAC/EMAC MACSR. No need to store, just as with CCR.
|
||||
g the EMAC ACCEXT{01,23}.
|
||||
H the MASK. No need to store, just as with CCR.
|
||||
i the MAC/EMAC scale factor.
|
||||
|
||||
I Coprocessor ID. Not printed if 1. The Coprocessor ID is always
|
||||
extracted from the 'd' field of word one, which means that an extended
|
||||
|
|
@ -230,7 +235,9 @@ struct m68k_opcode_alias
|
|||
w (modes 2-5,7.2)
|
||||
y (modes 2,5)
|
||||
z (modes 2,5,7.2)
|
||||
x mov3q immediate operand. */
|
||||
x mov3q immediate operand.
|
||||
4 (modes 2,3,4,5)
|
||||
*/
|
||||
|
||||
/* For the 68851: */
|
||||
/* I didn't use much imagination in choosing the
|
||||
|
|
@ -283,7 +290,7 @@ struct m68k_opcode_alias
|
|||
*/
|
||||
|
||||
/* Places to put an operand, for non-general operands:
|
||||
Characters used: BbCcDdghijkLlMmNnostWw123456789
|
||||
Characters used: BbCcDdFfGgHhIijkLlMmNnostWw123456789/
|
||||
|
||||
s source, low bits of first word.
|
||||
d dest, shifted 9 in first word
|
||||
|
|
@ -348,6 +355,13 @@ struct m68k_opcode_alias
|
|||
F double precision float, low bit of 1st word, immediate uses 8 bytes
|
||||
x extended precision float, low bit of 1st word, immediate uses 12 bytes
|
||||
p packed float, low bit of 1st word, immediate uses 12 bytes
|
||||
G EMAC accumulator, load (bit 4 2nd word, !bit8 first word)
|
||||
H EMAC accumulator, non load (bit 4 2nd word, bit 8 first word)
|
||||
F EMAC ACCx
|
||||
f EMAC ACCy
|
||||
I MAC/EMAC scale factor
|
||||
/ Like 's', but set 2nd word, bit 5 if trailing_ampersand set
|
||||
] first word, bit 10
|
||||
*/
|
||||
|
||||
extern const struct m68k_opcode m68k_opcodes[];
|
||||
|
|
|
|||
|
|
@ -1,3 +1,13 @@
|
|||
2004-04-22 Peter Barada <peter@the-baradas.com>
|
||||
|
||||
* m68k-dis.c(print_insn_m68k): Set mfcmac/mcfemac on
|
||||
appropriate ColdFire architectures.
|
||||
(print_insn_m68k): Handle EMAC, MAC/EMAC scalefactor, and MAC/EMAC
|
||||
mask addressing.
|
||||
Add EMAC instructions, fix MAC instructions. Remove
|
||||
macmw/macml/msacmw/msacml instructions since mask addressing now
|
||||
supported.
|
||||
|
||||
2004-04-20 Jakub Jelinek <jakub@redhat.com>
|
||||
|
||||
* sparc-opc.c (fmoviccx, fmovfccx, fmovccx): Define.
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
/* Print Motorola 68k instructions.
|
||||
Copyright 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
|
||||
1998, 1999, 2000, 2001, 2002, 2003
|
||||
1998, 1999, 2000, 2001, 2002, 2003, 2004
|
||||
Free Software Foundation, Inc.
|
||||
|
||||
This file is free software; you can redistribute it and/or modify
|
||||
|
|
@ -264,16 +264,19 @@ print_insn_m68k (memaddr, info)
|
|||
arch_mask = mcf5200;
|
||||
break;
|
||||
case bfd_mach_mcf528x:
|
||||
arch_mask = mcf528x;
|
||||
arch_mask = mcf528x | mcfmac;
|
||||
break;
|
||||
case bfd_mach_mcf5206e:
|
||||
arch_mask = mcf5206e;
|
||||
arch_mask = mcf5206e | mcfmac;
|
||||
break;
|
||||
case bfd_mach_mcf5307:
|
||||
arch_mask = mcf5307;
|
||||
arch_mask = mcf5307 | mcfmac;
|
||||
break;
|
||||
case bfd_mach_mcf5407:
|
||||
arch_mask = mcf5407;
|
||||
arch_mask = mcf5407 | mcfmac;
|
||||
break;
|
||||
case bfd_mach_mcfv4e:
|
||||
arch_mask = mcfv4e | mcfemac;
|
||||
break;
|
||||
}
|
||||
|
||||
|
|
@ -736,6 +739,24 @@ print_insn_arg (d, buffer, p0, addr, info)
|
|||
fpcr_names[fetch_arg (buffer, place, 3, info)]);
|
||||
break;
|
||||
|
||||
case 'e':
|
||||
val = fetch_arg(buffer, place, 2, info);
|
||||
(*info->fprintf_func) (info->stream, "%%acc%d", val);
|
||||
break;
|
||||
|
||||
case 'g':
|
||||
val = fetch_arg(buffer, place, 2, info);
|
||||
(*info->fprintf_func) (info->stream, "%%accext%s", val==0 ? "01" : "23");
|
||||
break;
|
||||
|
||||
case 'i':
|
||||
val = fetch_arg(buffer, place, 2, info);
|
||||
if (val == 1)
|
||||
(*info->fprintf_func) (info->stream, "<<");
|
||||
else if (val == 3)
|
||||
(*info->fprintf_func) (info->stream, ">>");
|
||||
break;
|
||||
|
||||
case 'I':
|
||||
/* Get coprocessor ID... */
|
||||
val = fetch_arg (buffer, 'd', 3, info);
|
||||
|
|
@ -744,6 +765,7 @@ print_insn_arg (d, buffer, p0, addr, info)
|
|||
(*info->fprintf_func) (info->stream, "(cpid=%d) ", val);
|
||||
break;
|
||||
|
||||
case '4':
|
||||
case '*':
|
||||
case '~':
|
||||
case '%':
|
||||
|
|
@ -881,6 +903,16 @@ print_insn_arg (d, buffer, p0, addr, info)
|
|||
return -1;
|
||||
}
|
||||
}
|
||||
|
||||
/* If place is '/', then this is the case of the mask bit for
|
||||
mac/emac loads. Now that the arg has been printed, grab the
|
||||
mask bit and if set, add a '&' to the arg. */
|
||||
if (place == '/')
|
||||
{
|
||||
val = fetch_arg (buffer, place, 1, info);
|
||||
if (val)
|
||||
(*info->fprintf_func) (info->stream, "&");
|
||||
}
|
||||
break;
|
||||
|
||||
case 'L':
|
||||
|
|
@ -1075,6 +1107,34 @@ fetch_arg (buffer, code, bits, info)
|
|||
register int val = 0;
|
||||
switch (code)
|
||||
{
|
||||
case '/': /* MAC/EMAC mask bit. */
|
||||
val = buffer[3] >> 5;
|
||||
break;
|
||||
|
||||
case 'G': /* EMAC ACC load. */
|
||||
val = ((buffer[3] >> 3) & 0x2) | ((~buffer[2] >> 7) & 0x1);
|
||||
break;
|
||||
|
||||
case 'H': /* EMAC ACC !load. */
|
||||
val = ((buffer[3] >> 3) & 0x2) | ((buffer[2] >> 7) & 0x1);
|
||||
break;
|
||||
|
||||
case ']': /* EMAC ACCEXT bit. */
|
||||
val = buffer[0] >> 2;
|
||||
break;
|
||||
|
||||
case 'I': /* MAC/EMAC scale factor. */
|
||||
val = buffer[0] >> 1;
|
||||
break;
|
||||
|
||||
case 'F': /* EMAC ACCx. */
|
||||
val = buffer[0] >> 1;
|
||||
break;
|
||||
|
||||
case 'f':
|
||||
val = buffer[0];
|
||||
break;
|
||||
|
||||
case 's':
|
||||
val = buffer[1];
|
||||
break;
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
/* Opcode table for m680[012346]0/m6888[12]/m68851/mcf5200.
|
||||
Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
|
||||
2000, 2001, 2003
|
||||
2000, 2001, 2003, 2004
|
||||
Free Software Foundation, Inc.
|
||||
|
||||
This file is part of GDB, GAS, and the GNU binutils.
|
||||
|
|
@ -1459,44 +1459,33 @@ const struct m68k_opcode m68k_opcodes[] =
|
|||
{"lsrl", one(0160210), one(0170770), "QdDs", m68000up | mcf },
|
||||
{"lsrl", one(0160250), one(0170770), "DdDs", m68000up | mcf },
|
||||
|
||||
/* FIXME: add MAM mode (`&' after <ea> operand) / remove MACM */
|
||||
{"macw", two(0120000, 0000000), two(0170660, 0005400), "uMum", mcf5206eup },
|
||||
{"macw", two(0120000, 0001000), two(0170660, 0005400), "uMumMh",mcf5206eup },
|
||||
{"macw", two(0120220, 0000000), two(0170670, 0005460), "uNuoasRn", mcf5206eup },
|
||||
{"macw", two(0120230, 0000000), two(0170670, 0005460), "uNuo+sRn", mcf5206eup },
|
||||
{"macw", two(0120240, 0000000), two(0170670, 0005460), "uNuo-sRn", mcf5206eup },
|
||||
{"macw", two(0120250, 0000000), two(0170670, 0005460), "uNuodsRn", mcf5206eup },
|
||||
{"macw", two(0120220, 0001000), two(0170670, 0005460), "uNuoMhasRn", mcf5206eup },
|
||||
{"macw", two(0120230, 0001000), two(0170670, 0005460), "uNuoMh+sRn", mcf5206eup },
|
||||
{"macw", two(0120240, 0001000), two(0170670, 0005460), "uNuoMh-sRn", mcf5206eup },
|
||||
{"macw", two(0120250, 0001000), two(0170670, 0005460), "uNuoMhdsRn", mcf5206eup },
|
||||
{"macmw", two(0120220, 0000040), two(0170670, 0005460), "uNuoasRn", mcf5206eup },
|
||||
{"macmw", two(0120230, 0000040), two(0170670, 0005460), "uNuo+sRn", mcf5206eup },
|
||||
{"macmw", two(0120240, 0000040), two(0170670, 0005460), "uNuo-sRn", mcf5206eup },
|
||||
{"macmw", two(0120250, 0000040), two(0170670, 0005460), "uNuodsRn", mcf5206eup },
|
||||
{"macmw", two(0120220, 0001040), two(0170670, 0005460), "uNuoMhasRn", mcf5206eup },
|
||||
{"macmw", two(0120230, 0001040), two(0170670, 0005460), "uNuoMh+sRn", mcf5206eup },
|
||||
{"macmw", two(0120240, 0001040), two(0170670, 0005460), "uNuoMh-sRn", mcf5206eup },
|
||||
{"macmw", two(0120250, 0001040), two(0170670, 0005460), "uNuoMhdsRn", mcf5206eup },
|
||||
{"macw", two(0xa000, 0x0000), two(0xf1b0, 0x0800), "uMum", mcfmac },
|
||||
{"macw", two(0xa000, 0x0000), two(0xf1b0, 0x0b00), "uMumiI", mcfmac },
|
||||
{"macw", two(0xa000, 0x0200), two(0xf1b0, 0x0b00), "uMumMh", mcfmac },
|
||||
{"macw", two(0xa080, 0x0000), two(0xf180, 0x0f30), "uNuo4/Rn", mcfmac },
|
||||
{"macw", two(0xa080, 0x0000), two(0xf180, 0x0910), "uNuoiI4/Rn", mcfmac },
|
||||
{"macw", two(0xa080, 0x0200), two(0xf180, 0x0910), "uNuoMh4/Rn", mcfmac },
|
||||
|
||||
{"macl", two(0120000, 0004000), two(0170660, 0005400), "RsRm", mcf5206eup },
|
||||
{"macl", two(0120000, 0005000), two(0170660, 0005400), "RsRmMh", mcf5206eup },
|
||||
{"macl", two(0120220, 0004000), two(0170670, 0005460), "R3R1asRn", mcf5206eup },
|
||||
{"macl", two(0120230, 0004000), two(0170670, 0005460), "R3R1+sRn", mcf5206eup },
|
||||
{"macl", two(0120240, 0004000), two(0170670, 0005460), "R3R1-sRn", mcf5206eup },
|
||||
{"macl", two(0120250, 0004000), two(0170670, 0005460), "R3R1dsRn", mcf5206eup },
|
||||
{"macl", two(0120220, 0005000), two(0170670, 0005460), "R3R1MhasRn", mcf5206eup },
|
||||
{"macl", two(0120230, 0005000), two(0170670, 0005460), "R3R1Mh+sRn", mcf5206eup },
|
||||
{"macl", two(0120240, 0005000), two(0170670, 0005460), "R3R1Mh-sRn", mcf5206eup },
|
||||
{"macl", two(0120250, 0005000), two(0170670, 0005460), "R3R1MhdsRn", mcf5206eup },
|
||||
{"macml", two(0120220, 0004040), two(0170670, 0005460), "R3R1asRn", mcf5206eup },
|
||||
{"macml", two(0120230, 0004040), two(0170670, 0005460), "R3R1+sRn", mcf5206eup },
|
||||
{"macml", two(0120240, 0004040), two(0170670, 0005460), "R3R1-sRn", mcf5206eup },
|
||||
{"macml", two(0120250, 0004040), two(0170670, 0005460), "R3R1dsRn", mcf5206eup },
|
||||
{"macml", two(0120220, 0005040), two(0170670, 0005460), "R3R1MhasRn", mcf5206eup },
|
||||
{"macml", two(0120230, 0005040), two(0170670, 0005460), "R3R1Mh+sRn", mcf5206eup },
|
||||
{"macml", two(0120240, 0005040), two(0170670, 0005460), "R3R1Mh-sRn", mcf5206eup },
|
||||
{"macml", two(0120250, 0005040), two(0170670, 0005460), "R3R1MhdsRn", mcf5206eup },
|
||||
{"macw", two(0xa000, 0x0000), two(0xf130, 0x0f00), "uMumeH", mcfemac }, /* Ry,Rx,accX. */
|
||||
{"macw", two(0xa000, 0x0000), two(0xf130, 0x0900), "uMumiIeH", mcfemac },/* Ry,Rx,SF,accX. */
|
||||
{"macw", two(0xa000, 0x0200), two(0xf130, 0x0900), "uMumMheH", mcfemac },/* Ry,Rx,+1/-1,accX. */
|
||||
{"macw", two(0xa000, 0x0000), two(0xf100, 0x0f00), "uMum4/RneG", mcfemac },/* Ry,Rx,<ea>,accX. */
|
||||
{"macw", two(0xa000, 0x0000), two(0xf100, 0x0900), "uMumiI4/RneG", mcfemac },/* Ry,Rx,SF,<ea>,accX. */
|
||||
{"macw", two(0xa000, 0x0200), two(0xf100, 0x0900), "uMumMh4/RneG", mcfemac },/* Ry,Rx,+1/-1,<ea>,accX. */
|
||||
|
||||
{"macl", two(0xa000, 0x0800), two(0xf1b0, 0x0800), "RMRm", mcfmac },
|
||||
{"macl", two(0xa000, 0x0800), two(0xf1b0, 0x0b00), "RMRmiI", mcfmac },
|
||||
{"macl", two(0xa000, 0x0a00), two(0xf1b0, 0x0b00), "RMRmMh", mcfmac },
|
||||
{"macl", two(0xa080, 0x0800), two(0xf180, 0x0f30), "RNRo4/Rn", mcfmac },
|
||||
{"macl", two(0xa080, 0x0800), two(0xf180, 0x0910), "RNRoiI4/Rn", mcfmac },
|
||||
{"macl", two(0xa080, 0x0a00), two(0xf180, 0x0910), "RNRoMh4/Rn", mcfmac },
|
||||
|
||||
{"macl", two(0xa000, 0x0800), two(0xf130, 0x0f00), "RMRmeH", mcfemac },
|
||||
{"macl", two(0xa000, 0x0800), two(0xf130, 0x0900), "RMRmiIeH", mcfemac },
|
||||
{"macl", two(0xa000, 0x0a00), two(0xf130, 0x0900), "RMRmMheH", mcfemac },
|
||||
{"macl", two(0xa000, 0x0800), two(0xf100, 0x0f00), "R3R14/RneG", mcfemac },
|
||||
{"macl", two(0xa000, 0x0800), two(0xf100, 0x0900), "R3R1iI4/RneG", mcfemac },
|
||||
{"macl", two(0xa000, 0x0a00), two(0xf100, 0x0900), "R3R1Mh4/RneG", mcfemac },
|
||||
|
||||
/* NOTE: The mcf5200 family programmer's reference manual does not
|
||||
indicate the byte form of the movea instruction is invalid (as it
|
||||
|
|
@ -1518,6 +1507,8 @@ const struct m68k_opcode m68k_opcodes[] =
|
|||
{"moveal", one(0020100), one(0170700), "*lAd", m68000up | mcf },
|
||||
{"moveaw", one(0030100), one(0170700), "*wAd", m68000up | mcf },
|
||||
|
||||
{"movclrl", one(0xA1C0), one(0xf9f0), "eFRs", mcfemac },
|
||||
|
||||
{"movec", one(0047173), one(0177777), "R1Jj", m68010up | mcf },
|
||||
{"movec", one(0047173), one(0177777), "R1#j", m68010up | mcf },
|
||||
{"movec", one(0047172), one(0177777), "JjR1", m68010up },
|
||||
|
|
@ -1588,16 +1579,31 @@ const struct m68k_opcode m68k_opcodes[] =
|
|||
{"movel", one(0020000), one(0170000), "olnd", mcfv4up },
|
||||
{"movel", one(0047140), one(0177770), "AsUd", m68000up | mcfv4e },
|
||||
{"movel", one(0047150), one(0177770), "UdAs", m68000up | mcfv4e },
|
||||
{"movel", one(0120600), one(0177760), "EsRs", mcf5206eup },
|
||||
{"movel", one(0120400), one(0177760), "RsEs", mcf5206eup },
|
||||
{"movel", one(0120474), one(0177777), "#lEs", mcf5206eup },
|
||||
{"movel", one(0124600), one(0177760), "GsRs", mcf5206eup },
|
||||
{"movel", one(0124400), one(0177760), "RsGs", mcf5206eup },
|
||||
{"movel", one(0124474), one(0177777), "#lGs", mcf5206eup },
|
||||
{"movel", one(0126600), one(0177760), "HsRs", mcf5206eup },
|
||||
{"movel", one(0126400), one(0177760), "RsHs", mcf5206eup },
|
||||
{"movel", one(0126474), one(0177777), "#lHs", mcf5206eup },
|
||||
{"movel", one(0124700), one(0177777), "GsCs", mcf5206eup },
|
||||
{"movel", one(0120600), one(0177760), "EsRs", mcfmac },
|
||||
{"movel", one(0120400), one(0177760), "RsEs", mcfmac },
|
||||
{"movel", one(0120474), one(0177777), "#lEs", mcfmac },
|
||||
{"movel", one(0124600), one(0177760), "GsRs", mcfmac },
|
||||
{"movel", one(0124400), one(0177760), "RsGs", mcfmac },
|
||||
{"movel", one(0124474), one(0177777), "#lGs", mcfmac },
|
||||
{"movel", one(0126600), one(0177760), "HsRs", mcfmac },
|
||||
{"movel", one(0126400), one(0177760), "RsHs", mcfmac },
|
||||
{"movel", one(0126474), one(0177777), "#lHs", mcfmac },
|
||||
{"movel", one(0124700), one(0177777), "GsCs", mcfmac },
|
||||
|
||||
{"movel", one(0xa180), one(0xf9f0), "eFRs", mcfemac }, /* ACCx,Rx. */
|
||||
{"movel", one(0xab80), one(0xfbf0), "g]Rs", mcfemac }, /* ACCEXTx,Rx. */
|
||||
{"movel", one(0xa980), one(0xfff0), "G-Rs", mcfemac }, /* macsr,Rx. */
|
||||
{"movel", one(0xad80), one(0xfff0), "H-Rs", mcfemac }, /* mask,Rx. */
|
||||
{"movel", one(0xa110), one(0xf9fc), "efeF", mcfemac }, /* ACCy,ACCx. */
|
||||
{"movel", one(0xa9c0), one(0xffff), "G-C-", mcfemac }, /* macsr,ccr. */
|
||||
{"movel", one(0xa100), one(0xf9f0), "RseF", mcfemac }, /* Rx,ACCx. */
|
||||
{"movel", one(0xa13c), one(0xf9ff), "#leF", mcfemac }, /* #,ACCx. */
|
||||
{"movel", one(0xab00), one(0xfbc0), "Rsg]", mcfemac }, /* Rx,ACCEXTx. */
|
||||
{"movel", one(0xab3c), one(0xfbff), "#lg]", mcfemac }, /* #,ACCEXTx. */
|
||||
{"movel", one(0xa900), one(0xffc0), "RsG-", mcfemac }, /* Rx,macsr. */
|
||||
{"movel", one(0xa93c), one(0xffff), "#lG-", mcfemac }, /* #,macsr. */
|
||||
{"movel", one(0xad00), one(0xffc0), "RsH-", mcfemac }, /* Rx,mask. */
|
||||
{"movel", one(0xad3c), one(0xffff), "#lH-", mcfemac }, /* #,mask. */
|
||||
|
||||
{"move", one(0030000), one(0170000), "*w%d", m68000up },
|
||||
{"move", one(0030000), one(0170000), "ms%d", mcf },
|
||||
|
|
@ -1637,44 +1643,33 @@ const struct m68k_opcode m68k_opcodes[] =
|
|||
{"move16", one(0xf610), one(0xfff8), "as_L", m68040up },
|
||||
{"move16", one(0xf618), one(0xfff8), "_Las", m68040up },
|
||||
|
||||
/* FIXME: add MAM mode (`&' after <ea> operand) / remove MSACM */
|
||||
{"msacw", two(0120000, 0000400), two(0170660, 0005400), "uMum", mcf5206eup },
|
||||
{"msacw", two(0120000, 0001400), two(0170660, 0005400), "uMumMh", mcf5206eup },
|
||||
{"msacw", two(0120220, 0000400), two(0170670, 0005460), "uNuoasRn", mcf5206eup },
|
||||
{"msacw", two(0120230, 0000400), two(0170670, 0005460), "uNuo+sRn", mcf5206eup },
|
||||
{"msacw", two(0120240, 0000400), two(0170670, 0005460), "uNuo-sRn", mcf5206eup },
|
||||
{"msacw", two(0120250, 0000400), two(0170670, 0005460), "uNuodsRn", mcf5206eup },
|
||||
{"msacw", two(0120220, 0001400), two(0170670, 0005460), "uNuoMhasRn", mcf5206eup },
|
||||
{"msacw", two(0120230, 0001400), two(0170670, 0005460), "uNuoMh+sRn", mcf5206eup },
|
||||
{"msacw", two(0120240, 0001400), two(0170670, 0005460), "uNuoMh-sRn", mcf5206eup },
|
||||
{"msacw", two(0120250, 0001400), two(0170670, 0005460), "uNuoMhdsRn", mcf5206eup },
|
||||
{"msacmw", two(0120220, 0000440), two(0170670, 0005460), "uNuoasRn", mcf5206eup },
|
||||
{"msacmw", two(0120230, 0000440), two(0170670, 0005460), "uNuo+sRn", mcf5206eup },
|
||||
{"msacmw", two(0120240, 0000440), two(0170670, 0005460), "uNuo-sRn", mcf5206eup },
|
||||
{"msacmw", two(0120250, 0000440), two(0170670, 0005460), "uNuodsRn", mcf5206eup },
|
||||
{"msacmw", two(0120220, 0001440), two(0170670, 0005460), "uNuoMhasRn", mcf5206eup },
|
||||
{"msacmw", two(0120230, 0001440), two(0170670, 0005460), "uNuoMh+sRn", mcf5206eup },
|
||||
{"msacmw", two(0120240, 0001440), two(0170670, 0005460), "uNuoMh-sRn", mcf5206eup },
|
||||
{"msacmw", two(0120250, 0001440), two(0170670, 0005460), "uNuoMhdsRn", mcf5206eup },
|
||||
{"msacw", two(0xa000, 0x0100), two(0xf1b0, 0x0800), "uMum", mcfmac },
|
||||
{"msacw", two(0xa000, 0x0100), two(0xf1b0, 0x0b00), "uMumiI", mcfmac },
|
||||
{"msacw", two(0xa000, 0x0300), two(0xf1b0, 0x0b00), "uMumMh", mcfmac },
|
||||
{"msacw", two(0xa080, 0x0100), two(0xf180, 0x0f30), "uNuo4/Rn", mcfmac },
|
||||
{"msacw", two(0xa080, 0x0100), two(0xf180, 0x0910), "uNuoiI4/Rn", mcfmac },
|
||||
{"msacw", two(0xa080, 0x0300), two(0xf180, 0x0910), "uNuoMh4/Rn", mcfmac },
|
||||
|
||||
{"msacl", two(0120000, 0004400), two(0170660, 0005400), "RsRm", mcf5206eup },
|
||||
{"msacl", two(0120000, 0005400), two(0170660, 0005400), "RsRmMh", mcf5206eup },
|
||||
{"msacl", two(0120220, 0004400), two(0170670, 0005460), "R3R1asRn", mcf5206eup },
|
||||
{"msacl", two(0120230, 0004400), two(0170670, 0005460), "R3R1+sRn", mcf5206eup },
|
||||
{"msacl", two(0120240, 0004400), two(0170670, 0005460), "R3R1-sRn", mcf5206eup },
|
||||
{"msacl", two(0120250, 0004400), two(0170670, 0005460), "R3R1dsRn", mcf5206eup },
|
||||
{"msacl", two(0120220, 0005400), two(0170670, 0005460), "R3R1MhasRn", mcf5206eup },
|
||||
{"msacl", two(0120230, 0005400), two(0170670, 0005460), "R3R1Mh+sRn", mcf5206eup },
|
||||
{"msacl", two(0120240, 0005400), two(0170670, 0005460), "R3R1Mh-sRn", mcf5206eup },
|
||||
{"msacl", two(0120250, 0005400), two(0170670, 0005460), "R3R1MhdsRn", mcf5206eup },
|
||||
{"msacml", two(0120220, 0004440), two(0170670, 0005460), "R3R1asRn", mcf5206eup },
|
||||
{"msacml", two(0120230, 0004440), two(0170670, 0005460), "R3R1+sRn", mcf5206eup },
|
||||
{"msacml", two(0120240, 0004440), two(0170670, 0005460), "R3R1-sRn", mcf5206eup },
|
||||
{"msacml", two(0120250, 0004440), two(0170670, 0005460), "R3R1dsRn", mcf5206eup },
|
||||
{"msacml", two(0120220, 0005440), two(0170670, 0005460), "R3R1MhasRn", mcf5206eup },
|
||||
{"msacml", two(0120230, 0005440), two(0170670, 0005460), "R3R1Mh+sRn", mcf5206eup },
|
||||
{"msacml", two(0120240, 0005440), two(0170670, 0005460), "R3R1Mh-sRn", mcf5206eup },
|
||||
{"msacml", two(0120250, 0005440), two(0170670, 0005460), "R3R1MhdsRn", mcf5206eup },
|
||||
{"msacw", two(0xa000, 0x0100), two(0xf130, 0x0f00), "uMumeH", mcfemac }, /* Ry,Rx,accX. */
|
||||
{"msacw", two(0xa000, 0x0100), two(0xf130, 0x0900), "uMumiIeH", mcfemac },/* Ry,Rx,SF,accX. */
|
||||
{"msacw", two(0xa000, 0x0300), two(0xf130, 0x0900), "uMumMheH", mcfemac },/* Ry,Rx,+1/-1,accX. */
|
||||
{"msacw", two(0xa000, 0x0100), two(0xf100, 0x0f00), "uMum4/RneG", mcfemac },/* Ry,Rx,<ea>,accX. */
|
||||
{"msacw", two(0xa000, 0x0100), two(0xf100, 0x0900), "uMumiI4/RneG", mcfemac },/* Ry,Rx,SF,<ea>,accX. */
|
||||
{"msacw", two(0xa000, 0x0300), two(0xf100, 0x0900), "uMumMh4/RneG", mcfemac },/* Ry,Rx,+1/-1,<ea>,accX. */
|
||||
|
||||
{"msacl", two(0xa000, 0x0900), two(0xf1b0, 0x0800), "RMRm", mcfmac },
|
||||
{"msacl", two(0xa000, 0x0900), two(0xf1b0, 0x0b00), "RMRmiI", mcfmac },
|
||||
{"msacl", two(0xa000, 0x0b00), two(0xf1b0, 0x0b00), "RMRmMh", mcfmac },
|
||||
{"msacl", two(0xa080, 0x0900), two(0xf180, 0x0f30), "RNRo4/Rn", mcfmac },
|
||||
{"msacl", two(0xa080, 0x0900), two(0xf180, 0x0910), "RNRoiI4/Rn", mcfmac },
|
||||
{"msacl", two(0xa080, 0x0b00), two(0xf180, 0x0910), "RNRoMh4/Rn", mcfmac },
|
||||
|
||||
{"msacl", two(0xa000, 0x0900), two(0xf130, 0x0f00), "RMRmeH", mcfemac },
|
||||
{"msacl", two(0xa000, 0x0900), two(0xf130, 0x0900), "RMRmiIeH", mcfemac },
|
||||
{"msacl", two(0xa000, 0x0b00), two(0xf130, 0x0900), "RMRmMheH", mcfemac },
|
||||
{"msacl", two(0xa000, 0x0900), two(0xf100, 0x0f00), "R3R14/RneG", mcfemac },
|
||||
{"msacl", two(0xa000, 0x0900), two(0xf100, 0x0900), "R3R1iI4/RneG", mcfemac },
|
||||
{"msacl", two(0xa000, 0x0b00), two(0xf100, 0x0900), "R3R1Mh4/RneG", mcfemac },
|
||||
|
||||
{"mulsw", one(0140700), one(0170700), ";wDd", m68000up|mcf },
|
||||
{"mulsl", two(0046000,004000), two(0177700,0107770), ";lD1", m68020up|cpu32 },
|
||||
|
|
|
|||
Loading…
Reference in a new issue