Add support for ColdFire MAC instructions and tidy up support for other m68k

variants.

bfd/ChangeLog

@@ -1,3 +1,9 @@
+2004-04-22  Peter Barada <peter@the-baradas.com>
+
+	* archures.c: Add bfd_mach_mcfv4e to bfd_architecture.
+	* bfd2-in.h: Regenerate.
+	* cpu-m68k.c: Add 'm68k:mcfv4e' to arch_info_struct[].
+
 2004-04-21  Chris Demetriou  <cgd@broadcom.com>
 
 	* coff-mips.c (bfd_mips_ecoff_create_embedded_relocs): Remove.

bfd/archures.c

@@ -85,6 +85,7 @@ DESCRIPTION
 .#define bfd_mach_mcf5307  11
 .#define bfd_mach_mcf5407  12
 .#define bfd_mach_mcf528x  13
+.#define bfd_mach_mcfv4e   14
 .  bfd_arch_vax,       {* DEC Vax *}
 .  bfd_arch_i960,      {* Intel 960 *}
 .    {* The order of the following is important.

bfd/bfd-in2.h

@@ -1491,6 +1491,7 @@ enum bfd_architecture
 #define bfd_mach_mcf5307  11
 #define bfd_mach_mcf5407  12
 #define bfd_mach_mcf528x  13
+#define bfd_mach_mcfv4e   14
   bfd_arch_vax,       /* DEC Vax */
   bfd_arch_i960,      /* Intel 960 */
     /* The order of the following is important.

bfd/cpu-m68k.c

@@ -1,6 +1,6 @@
 /* BFD library support routines for architectures.
    Copyright 1990, 1991, 1992, 1993, 1994, 1997, 1998, 2000, 2001, 2002,
-   2003 Free Software Foundation, Inc.
+   2003, 2004 Free Software Foundation, Inc.
    Hacked by Steve Chamberlain of Cygnus Support.
 
    This file is part of BFD, the Binary File Descriptor library.
@@ -40,7 +40,8 @@ static const bfd_arch_info_type arch_info_struct[] =
     N(bfd_mach_mcf5307, "m68k:5307",  FALSE, &arch_info_struct[10]),
     N(bfd_mach_mcf5407, "m68k:5407",  FALSE, &arch_info_struct[11]),
     N(bfd_mach_m68060,  "m68k:68060", FALSE, &arch_info_struct[12]),
-    N(bfd_mach_mcf528x, "m68k:528x",  FALSE, 0),
+    N(bfd_mach_mcf528x, "m68k:528x",  FALSE, &arch_info_struct[13]),
+    N(bfd_mach_mcfv4e, "m68k:cfv4e",  FALSE, 0),
   };
 
 const bfd_arch_info_type bfd_m68k_arch =

gas/ChangeLog

@@ -1,3 +1,23 @@
+2004-04-22  Peter Barada <peter@the-baradas.com>
+
+	* NEWS: Added support for EMAC instructions and MAC/EMAC
+	Motorola syntax.
+	* config/m68k-parse.h: Add ACC[123], ACCEXT{01,23}, MAC/EMAC
+	scale factor tokens, trailing_ampersand to mark mask addressing
+	for MAC/EMAC instructions.
+	* config/m68k-parse.y: Add options_ampersand clause, '<<',
+	'>>'.
+	(yylex): Handle '>', '<', and '&' following '+'.
+	* config/tc-m68k.c: Set mcfmac/mcfemac on appropriate ColdFire
+	architectures in archs[].  
+	(m68k-ip): Add '4', 'e', 'g', 'i', cases to handle mask addressing
+	for MAC/EMAC instructions, ACC[0123], ACCEXT{01,23}, and '<<'/'>>'
+	respectively.
+	(m68k_ip): Handle trailing '&' on MAC/EMAC insns.
+	(install_operand): Fix 'n' case, Add 'F', 'f', 'G', 'H', 'I', ']'
+	cases.
+	Add EMAC operands to init_table[].
+
 2004-04-22  Bruno De Bus <bdebus@elis.ugent.be>
 
 	* config/tc-arm.h (enum mstate): Move here, add MAP_UNDEFINED

gas/NEWS

@@ -1,5 +1,8 @@
 -*- text -*-
 
+* Support for ColdFire EMAC instructions added and Motorola syntax for MAC/EMAC
+  instrucitons.
+
 * The MIPS -membedded-pic option (Embedded-PIC code generation) is
   deprecated and will be removed in a future release.
 

gas/config/m68k-parse.h

@@ -1,6 +1,6 @@
 /* m68k-parse.h -- header file for m68k assembler
    Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1999, 2000,
-   2003 Free Software Foundation, Inc.
+   2003, 2004 Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler.
 
@@ -84,7 +84,12 @@ enum m68k_register
   ZPC,				/* Hack for Program space, but 0 addressing */
   SR,				/* Status Reg */
   CCR,				/* Condition code Reg */
-  ACC,				/* Accumulator Reg */
+  ACC,				/* Accumulator Reg0 (EMAC or ACC on MAC).  */
+  ACC1,				/* Accumulator Reg 1 (EMAC).  */
+  ACC2,				/* Accumulator Reg 2 (EMAC).  */
+  ACC3,				/* Accumulator Reg 3 (EMAC).  */
+  ACCEXT01,			/* Accumulator extension 0&1 (EMAC).  */
+  ACCEXT23,			/* Accumulator extension 2&3 (EMAC).  */
   MACSR,			/* MAC Status Reg */
   MASK,				/* Modulus Reg */
 
@@ -295,6 +300,8 @@ enum m68k_operand_type
   BASE,
   POST,
   PRE,
+  LSH,  /* MAC/EMAC scalefactor '<<'.  */
+  RSH,  /* MAC/EMAC scalefactor '>>'.  */
   REGLST
 };
 
@@ -322,6 +329,9 @@ struct m68k_op
 
   /* The outer displacement.  */
   struct m68k_exp odisp;
+
+  /* Is a trailing '&' added to an <ea>? (for MAC/EMAC mask addressing).  */
+  int trailing_ampersand;
 };
 
 #endif /* ! defined (M68K_PARSE_H) */

gas/config/m68k-parse.y

@@ -98,6 +98,7 @@ static struct m68k_op *op;
   struct m68k_exp exp;
   unsigned long mask;
   int onereg;
+  int trailing_ampersand;
 }
 
 %token <reg> DR AR FPR FPCR LPC ZAR ZDR LZPC CREG
@@ -109,6 +110,7 @@ static struct m68k_op *op;
 %type <exp> optcexpr optexprc
 %type <mask> reglist ireglist reglistpair
 %type <onereg> reglistreg
+%type <trailing_ampersand> optional_ampersand
 
 %%
 
@@ -116,14 +118,35 @@ static struct m68k_op *op;
 
 operand:
 	  generic_operand
-	| motorola_operand
+	| motorola_operand optional_ampersand
+		{
+		  op->trailing_ampersand = $2;
+		}
 	| mit_operand
 	;
 
+/* A trailing ampersand(for MAC/EMAC mask addressing).  */
+optional_ampersand:
+	/* empty */
+		{ $$ = 0; }
+	| '&'
+		{ $$ = 1; }
+	;
+
 /* A generic operand.  */
 
 generic_operand:
-	  DR
+	  '<' '<'
+		{
+		  op->mode = LSH;
+		}
+
+	| '>' '>'
+		{
+		  op->mode = RSH;
+		}
+
+	| DR
 		{
 		  op->mode = DREG;
 		  op->reg = $1;
@@ -757,12 +780,14 @@ yylex ()
     case '/':
     case '[':
     case ']':
+    case '<':
+    case '>':
       return *str++;
     case '+':
       /* It so happens that a '+' can only appear at the end of an
-         operand.  If it appears anywhere else, it must be a unary
+	 operand, or if it is trailed by an '&'(see mac load insn).
-         plus on an expression.  */
+	 If it appears anywhere else, it must be a unary.  */
-      if (str[1] == '\0')
+      if (str[1] == '\0' || (str[1] == '&' && str[2] == '\0'))
 	return *str++;
       break;
     case '-':

gas/config/tc-m68k.c

@@ -382,10 +382,10 @@ static const struct m68k_cpu archs[] =
     { m68851,		"68851", 0 },
     { mcf5200,		"5200",  0 },
     { mcf5206e,		"5206e", 0 },
-    { mcf528x, "528x",  0 },
+    { mcf528x|mcfmac,	"528x",  0 },
-    { mcf5307, "5307",  0 },
+    { mcf5307|mcfmac,	"5307",  0 },
-    { mcf5407, "5407",  0 },
+    { mcf5407|mcfmac,	"5407",  0 },
-    { mcfv4e,  "cfv4e", 0 },
+    { mcfv4e|mcfemac,	"cfv4e", 0 },
     /* Aliases (effectively, so far as gas is concerned) for the above
        cpus.  */
     { m68020,		"68k", 1 },
@@ -416,7 +416,7 @@ static const struct m68k_cpu archs[] =
     { mcf5200,		"5202", 1 },
     { mcf5200,		"5204", 1 },
     { mcf5200,		"5206", 1 },
-    { mcf5407, "cfv4", 1 },
+    { mcf5407|mcfmac,	"cfv4", 1 },
   };
 
 static const int n_archs = sizeof (archs) / sizeof (archs[0]);
@@ -1505,6 +1505,14 @@ m68k_ip (instring)
 		    ++losing;
 		  break;
 
+		case '4':
+		  if (opP->mode != AINDR && opP->mode != AINC && opP->mode != ADEC
+		      && (opP->mode != DISP
+			   || opP->reg < ADDR0
+			   || opP->reg > ADDR7))
+		    ++losing;
+		  break;
+
 		case 'B':	/* FOO */
 		  if (opP->mode != ABSL
 		      || (flag_long_jumps
@@ -1552,6 +1560,12 @@ m68k_ip (instring)
 		    losing++;
 		  break;
 
+		case 'e':
+		  if (opP->reg != ACC && opP->reg != ACC1
+		      && opP->reg != ACC2 && opP->reg != ACC3)
+		    losing++;
+		  break;
+
 		case 'F':
 		  if (opP->mode != FPREG)
 		    losing++;
@@ -1562,6 +1576,11 @@ m68k_ip (instring)
 		    losing++;
 		  break;
 
+		case 'g':
+		  if (opP->reg != ACCEXT01 && opP->reg != ACCEXT23)
+		    losing++;
+		  break;
+
 		case 'H':
 		  if (opP->reg != MASK)
 		    losing++;
@@ -1574,6 +1593,11 @@ m68k_ip (instring)
 		    losing++;
 		  break;
 
+		case 'i':
+		  if (opP->mode != LSH && opP->mode != RSH)
+		    losing++;
+		  break;
+
 		case 'J':
 		  if (opP->mode != CONTROL
 		      || opP->reg < USP
@@ -1994,6 +2018,7 @@ m68k_ip (instring)
 	case 'w':
 	case 'y':
 	case 'z':
+	case '4':
 #ifndef NO_68851
 	case '|':
 #endif
@@ -2519,6 +2544,16 @@ m68k_ip (instring)
 	      as_bad (_("unknown/incorrect operand"));
 	      /* abort (); */
 	    }
+
+	  /* If s[0] is '4', then this is for the mac instructions
+	     that can have a trailing_ampersand set.  If so, set 0x100
+	     bit on tmpreg so install_gen_operand can check for it and
+	     set the appropriate bit (word2, bit 5).  */
+	  if (s[0] == '4')
+	    {
+	      if (opP->trailing_ampersand)
+		tmpreg |= 0x100;
+	    }
 	  install_gen_operand (s[1], tmpreg);
 	  break;
 
@@ -2737,6 +2772,10 @@ m68k_ip (instring)
 	  install_operand (s[1], opP->reg - DATA);
 	  break;
 
+	case 'e':  /* EMAC ACCx, reg/reg.  */
+	  install_operand (s[1], opP->reg - ACC);
+	  break;
+	  
 	case 'E':		/* Ignore it.  */
 	  break;
 
@@ -2744,6 +2783,10 @@ m68k_ip (instring)
 	  install_operand (s[1], opP->reg - FP0);
 	  break;
 
+	case 'g':  /* EMAC ACCEXTx.  */
+	  install_operand (s[1], opP->reg - ACCEXT01);
+	  break;
+
 	case 'G':		/* Ignore it.  */
 	case 'H':
 	  break;
@@ -2753,6 +2796,10 @@ m68k_ip (instring)
 	  install_operand (s[1], tmpreg);
 	  break;
 
+	case 'i':  /* MAC/EMAC scale factor.  */
+	  install_operand (s[1], opP->mode == LSH ? 0x1 : 0x3);
+	  break;
+
 	case 'J':		/* JF foo.  */
 	  switch (opP->reg)
 	    {
@@ -3286,25 +3333,46 @@ install_operand (mode, val)
       the_ins.opcode[0] |= ((val & 0x7) << 9);
       the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
       break;
-    case 'n':
+    case 'n': /* MAC/EMAC Rx on !load.  */
       the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
       the_ins.opcode[0] |= ((val & 0x7) << 9);
+      the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
       break;
-    case 'o':
+    case 'o': /* MAC/EMAC Rx on load.  */
       the_ins.opcode[1] |= val << 12;
       the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
       break;
-    case 'M':
+    case 'M': /* MAC/EMAC Ry on !load.  */
       the_ins.opcode[0] |= (val & 0xF);
       the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
       break;
-    case 'N':
+    case 'N': /* MAC/EMAC Ry on load.  */
       the_ins.opcode[1] |= (val & 0xF);
       the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
       break;
     case 'h':
       the_ins.opcode[1] |= ((val != 1) << 10);
       break;
+    case 'F':
+      the_ins.opcode[0] |= ((val & 0x3) << 9);
+      break;
+    case 'f':
+      the_ins.opcode[0] |= ((val & 0x3) << 0);
+      break;
+    case 'G':
+      the_ins.opcode[0] |= ((~val & 0x1) << 7);
+      the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
+      break;
+    case 'H':
+      the_ins.opcode[0] |= ((val & 0x1) << 7);
+      the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
+      break;
+    case 'I':
+      the_ins.opcode[1] |= ((val & 0x3) << 9);
+      break;
+    case ']':
+      the_ins.opcode[0] |= (val & 0x1) <<10;
+      break;
     case 'c':
     default:
       as_fatal (_("failed sanity check."));
@@ -3318,6 +3386,11 @@ install_gen_operand (mode, val)
 {
   switch (mode)
     {
+    case '/':  /* Special for mask loads for mac/msac insns with
+		  possible mask; trailing_ampersend set in bit 8.  */
+      the_ins.opcode[0] |= (val & 0x3f);
+      the_ins.opcode[1] |= (((val & 0x100) >> 8) << 5);
+      break;
     case 's':
       the_ins.opcode[0] |= val;
       break;
@@ -3507,6 +3580,12 @@ static const struct init_entry init_table[] =
   { "cc", CCR },
 
   { "acc", ACC },
+  { "acc0", ACC },
+  { "acc1", ACC1 },
+  { "acc2", ACC2 },
+  { "acc3", ACC3 },
+  { "accext01", ACCEXT01 },
+  { "accext23", ACCEXT23 },
   { "macsr", MACSR },
   { "mask", MASK },
 

gas/testsuite/ChangeLog

@@ -1,3 +1,11 @@
+2004-04-22  Peter Barada <peter@the-baradas.com>
+
+	* gas/m68k/mcf-mac.s: New test: Check ColdFire MAC instructions.
+	* gas/m68k/mcf-emac.s: New test: Similar checks.
+	* gas/m68k/mcf-mac.d: New test: Expected output.
+	* gas/m68k/mcf-emac.d: New test: Likewise.
+	* gas/m68k/all.exp: Run new tests.
+
 2004-04-21  Chris Demetriou  <cgd@broadcom.com>
 
 	* gas/mips/elempic.d: File removed as part of -membedded-pic removal.

gas/testsuite/gas/m68k/all.exp

@@ -35,6 +35,8 @@ if [istarget m68*-*-*] then {
     run_dump_test link
     run_dump_test fmoveml
     run_dump_test mcf-mov3q
+    run_dump_test mcf-mac
+    run_dump_test mcf-emac
 
     set testname "68000 operands"
     gas_run "operands.s" "-m68000" "2>err.out"

include/opcode/ChangeLog

@@ -1,3 +1,11 @@
+2004-04-22  Peter Barada <peter@the-baradas.com>
+
+	* m68k.h: Add mcfmac/mcfemac definitions.  Update operand
+	descriptions for new EMAC cases.
+	Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
+	handle Motorola MAC syntax.
+	Allow disassembly of ColdFire V4e object files.
+
 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
 
 	* ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.

include/opcode/m68k.h

@@ -1,6 +1,6 @@
 /* Opcode table header for m680[01234]0/m6888[12]/m68851.
    Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1999, 2001,
-   2003 Free Software Foundation, Inc.
+   2003, 2004 Free Software Foundation, Inc.
 
    This file is part of GDB, GAS, and the GNU binutils.
 
@@ -42,6 +42,8 @@
 #define mcf5407  0x1000
 #define mcfv4e   0x2000
 #define mcf528x  0x4000
+#define mcfmac   0x8000
+#define mcfemac  0x10000
 
  /* Handy aliases.  */
 #define	m68040up   (m68040 | m68060)
@@ -99,7 +101,7 @@ struct m68k_opcode_alias
    operand; the second, the place it is stored.  */
 
 /* Kinds of operands:
-   Characters used: AaBbCcDdEFfGHIJkLlMmnOopQqRrSsTtU VvWwXxYyZz0123|*~%;@!&$?/<>#^+-
+   Characters used: AaBbCcDdEeFfGgHIiJkLlMmnOopQqRrSsTtU VvWwXxYyZz01234|*~%;@!&$?/<>#^+-
 
    D  data register only.  Stored as 3 bits.
    A  address register only.  Stored as 3 bits.
@@ -133,9 +135,12 @@ struct m68k_opcode_alias
    C  the CCR.  No need to store it; this is just for filtering validity.
    S  the SR.  No need to store, just as with CCR.
    U  the USP.  No need to store, just as with CCR.
-   E  the ACC.  No need to store, just as with CCR.
+   E  the MAC ACC.  No need to store, just as with CCR.
-   G  the MACSR.  No need to store, just as with CCR.
+   e  the EMAC ACC[0123].
+   G  the MAC/EMAC MACSR.  No need to store, just as with CCR.
+   g  the EMAC ACCEXT{01,23}.
    H  the MASK.  No need to store, just as with CCR.
+   i  the MAC/EMAC scale factor.
 
    I  Coprocessor ID.   Not printed if 1.   The Coprocessor ID is always
       extracted from the 'd' field of word one, which means that an extended
@@ -230,7 +235,9 @@ struct m68k_opcode_alias
    w                                            (modes 2-5,7.2)
    y						(modes 2,5)
    z						(modes 2,5,7.2)
-   x  mov3q immediate operand.  */
+   x  mov3q immediate operand.
+   4						(modes 2,3,4,5)
+  */
 
 /* For the 68851:  */
 /* I didn't use much imagination in choosing the
@@ -283,7 +290,7 @@ struct m68k_opcode_alias
 */
 
 /* Places to put an operand, for non-general operands:
-   Characters used: BbCcDdghijkLlMmNnostWw123456789
+   Characters used: BbCcDdFfGgHhIijkLlMmNnostWw123456789/
 
    s  source, low bits of first word.
    d  dest, shifted 9 in first word
@@ -348,6 +355,13 @@ struct m68k_opcode_alias
    F  double precision float, low bit of 1st word, immediate uses 8 bytes
    x  extended precision float, low bit of 1st word, immediate uses 12 bytes
    p  packed float, low bit of 1st word, immediate uses 12 bytes
+   G  EMAC accumulator, load  (bit 4 2nd word, !bit8 first word)
+   H  EMAC accumulator, non load  (bit 4 2nd word, bit 8 first word)
+   F  EMAC ACCx
+   f  EMAC ACCy
+   I  MAC/EMAC scale factor
+   /  Like 's', but set 2nd word, bit 5 if trailing_ampersand set
+   ]  first word, bit 10
 */
 
 extern const struct m68k_opcode m68k_opcodes[];

opcodes/ChangeLog

@@ -1,3 +1,13 @@
+2004-04-22  Peter Barada <peter@the-baradas.com>
+
+	* m68k-dis.c(print_insn_m68k): Set mfcmac/mcfemac on
+	appropriate ColdFire architectures.
+	(print_insn_m68k): Handle EMAC, MAC/EMAC scalefactor, and MAC/EMAC
+	mask addressing.
+	Add EMAC instructions, fix MAC instructions. Remove
+	macmw/macml/msacmw/msacml instructions since mask addressing now
+	supported.
+
 2004-04-20  Jakub Jelinek  <jakub@redhat.com>
 
 	* sparc-opc.c (fmoviccx, fmovfccx, fmovccx): Define.

opcodes/m68k-dis.c

@@ -1,6 +1,6 @@
 /* Print Motorola 68k instructions.
    Copyright 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
-   1998, 1999, 2000, 2001, 2002, 2003
+   1998, 1999, 2000, 2001, 2002, 2003, 2004
    Free Software Foundation, Inc.
 
    This file is free software; you can redistribute it and/or modify
@@ -264,16 +264,19 @@ print_insn_m68k (memaddr, info)
       arch_mask = mcf5200;
       break;
     case bfd_mach_mcf528x:
-      arch_mask = mcf528x;
+      arch_mask = mcf528x | mcfmac;
       break;
     case bfd_mach_mcf5206e:
-      arch_mask = mcf5206e;
+      arch_mask = mcf5206e | mcfmac;
       break;
     case bfd_mach_mcf5307:
-      arch_mask = mcf5307;
+      arch_mask = mcf5307 | mcfmac;
       break;
     case bfd_mach_mcf5407:
-      arch_mask = mcf5407;
+      arch_mask = mcf5407 | mcfmac;
+      break;
+    case bfd_mach_mcfv4e:
+      arch_mask = mcfv4e | mcfemac;
       break;
     }
 
@@ -736,6 +739,24 @@ print_insn_arg (d, buffer, p0, addr, info)
 			     fpcr_names[fetch_arg (buffer, place, 3, info)]);
       break;
 
+    case 'e':
+      val = fetch_arg(buffer, place, 2, info);
+      (*info->fprintf_func) (info->stream, "%%acc%d", val);
+      break;
+
+    case 'g':
+      val = fetch_arg(buffer, place, 2, info);
+      (*info->fprintf_func) (info->stream, "%%accext%s", val==0 ? "01" : "23");
+      break;
+      
+    case 'i':
+      val = fetch_arg(buffer, place, 2, info);
+      if (val == 1)
+	(*info->fprintf_func) (info->stream, "<<");
+      else if (val == 3)
+	(*info->fprintf_func) (info->stream, ">>");
+      break;
+
     case 'I':
       /* Get coprocessor ID... */
       val = fetch_arg (buffer, 'd', 3, info);
@@ -744,6 +765,7 @@ print_insn_arg (d, buffer, p0, addr, info)
 	(*info->fprintf_func) (info->stream, "(cpid=%d) ", val);
       break;
 
+    case '4':
     case '*':
     case '~':
     case '%':
@@ -881,6 +903,16 @@ print_insn_arg (d, buffer, p0, addr, info)
 	      return -1;
 	    }
 	}
+
+      /* If place is '/', then this is the case of the mask bit for
+	 mac/emac loads. Now that the arg has been printed, grab the
+	 mask bit and if set, add a '&' to the arg.  */
+      if (place == '/')
+	{
+	  val = fetch_arg (buffer, place, 1, info);
+	  if (val)
+		(*info->fprintf_func) (info->stream, "&");
+	}
       break;
 
     case 'L':
@@ -1075,6 +1107,34 @@ fetch_arg (buffer, code, bits, info)
   register int val = 0;
   switch (code)
     {
+    case '/': /* MAC/EMAC mask bit.  */
+      val = buffer[3] >> 5;
+      break;
+
+    case 'G': /* EMAC ACC load.  */
+      val = ((buffer[3] >> 3) & 0x2) | ((~buffer[2] >> 7) & 0x1);
+      break;
+
+    case 'H': /* EMAC ACC !load.  */
+      val = ((buffer[3] >> 3) & 0x2) | ((buffer[2] >> 7) & 0x1);
+      break;
+
+    case ']': /* EMAC ACCEXT bit.  */
+      val = buffer[0] >> 2;
+      break;
+
+    case 'I': /* MAC/EMAC scale factor.  */
+      val = buffer[0] >> 1;
+      break;
+
+    case 'F': /* EMAC ACCx.  */
+      val = buffer[0] >> 1;
+      break;
+
+    case 'f':
+      val = buffer[0];
+      break;
+
     case 's':
       val = buffer[1];
       break;

opcodes/m68k-opc.c

@@ -1,6 +1,6 @@
 /* Opcode table for m680[012346]0/m6888[12]/m68851/mcf5200.
    Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
-   2000, 2001, 2003
+   2000, 2001, 2003, 2004
    Free Software Foundation, Inc.
 
    This file is part of GDB, GAS, and the GNU binutils.
@@ -1459,44 +1459,33 @@ const struct m68k_opcode m68k_opcodes[] =
 {"lsrl",	one(0160210),	one(0170770), "QdDs", m68000up | mcf },
 {"lsrl",	one(0160250),	one(0170770), "DdDs", m68000up | mcf },
 
-  /* FIXME: add MAM mode (`&' after <ea> operand) / remove MACM */
+{"macw",  two(0xa000, 0x0000), two(0xf1b0, 0x0800), "uMum", mcfmac },
-{"macw",  two(0120000, 0000000), two(0170660, 0005400), "uMum", mcf5206eup },
+{"macw",  two(0xa000, 0x0000), two(0xf1b0, 0x0b00), "uMumiI", mcfmac },
-{"macw",  two(0120000, 0001000), two(0170660, 0005400), "uMumMh",mcf5206eup },
+{"macw",  two(0xa000, 0x0200), two(0xf1b0, 0x0b00), "uMumMh", mcfmac },
-{"macw",  two(0120220, 0000000), two(0170670, 0005460), "uNuoasRn", mcf5206eup },
+{"macw",  two(0xa080, 0x0000), two(0xf180, 0x0f30), "uNuo4/Rn", mcfmac },
-{"macw",  two(0120230, 0000000), two(0170670, 0005460), "uNuo+sRn", mcf5206eup },
+{"macw",  two(0xa080, 0x0000), two(0xf180, 0x0910), "uNuoiI4/Rn", mcfmac },
-{"macw",  two(0120240, 0000000), two(0170670, 0005460), "uNuo-sRn", mcf5206eup },
+{"macw",  two(0xa080, 0x0200), two(0xf180, 0x0910), "uNuoMh4/Rn", mcfmac },
-{"macw",  two(0120250, 0000000), two(0170670, 0005460), "uNuodsRn", mcf5206eup },
-{"macw",  two(0120220, 0001000), two(0170670, 0005460), "uNuoMhasRn", mcf5206eup },
-{"macw",  two(0120230, 0001000), two(0170670, 0005460), "uNuoMh+sRn", mcf5206eup },
-{"macw",  two(0120240, 0001000), two(0170670, 0005460), "uNuoMh-sRn", mcf5206eup },
-{"macw",  two(0120250, 0001000), two(0170670, 0005460), "uNuoMhdsRn", mcf5206eup },
-{"macmw", two(0120220, 0000040), two(0170670, 0005460), "uNuoasRn", mcf5206eup },
-{"macmw", two(0120230, 0000040), two(0170670, 0005460), "uNuo+sRn", mcf5206eup },
-{"macmw", two(0120240, 0000040), two(0170670, 0005460), "uNuo-sRn", mcf5206eup },
-{"macmw", two(0120250, 0000040), two(0170670, 0005460), "uNuodsRn", mcf5206eup },
-{"macmw", two(0120220, 0001040), two(0170670, 0005460), "uNuoMhasRn", mcf5206eup },
-{"macmw", two(0120230, 0001040), two(0170670, 0005460), "uNuoMh+sRn", mcf5206eup },
-{"macmw", two(0120240, 0001040), two(0170670, 0005460), "uNuoMh-sRn", mcf5206eup },
-{"macmw", two(0120250, 0001040), two(0170670, 0005460), "uNuoMhdsRn", mcf5206eup },
 
-{"macl",  two(0120000, 0004000), two(0170660, 0005400), "RsRm", mcf5206eup },
+{"macw",  two(0xa000, 0x0000), two(0xf130, 0x0f00), "uMumeH", mcfemac }, /* Ry,Rx,accX.  */
-{"macl",  two(0120000, 0005000), two(0170660, 0005400), "RsRmMh", mcf5206eup },
+{"macw",  two(0xa000, 0x0000), two(0xf130, 0x0900), "uMumiIeH", mcfemac },/* Ry,Rx,SF,accX.  */
-{"macl",  two(0120220, 0004000), two(0170670, 0005460), "R3R1asRn", mcf5206eup },
+{"macw",  two(0xa000, 0x0200), two(0xf130, 0x0900), "uMumMheH", mcfemac },/* Ry,Rx,+1/-1,accX.  */
-{"macl",  two(0120230, 0004000), two(0170670, 0005460), "R3R1+sRn", mcf5206eup },
+{"macw",  two(0xa000, 0x0000), two(0xf100, 0x0f00), "uMum4/RneG", mcfemac },/* Ry,Rx,<ea>,accX.  */
-{"macl",  two(0120240, 0004000), two(0170670, 0005460), "R3R1-sRn", mcf5206eup },
+{"macw",  two(0xa000, 0x0000), two(0xf100, 0x0900), "uMumiI4/RneG", mcfemac },/* Ry,Rx,SF,<ea>,accX.  */
-{"macl",  two(0120250, 0004000), two(0170670, 0005460), "R3R1dsRn", mcf5206eup },
+{"macw",  two(0xa000, 0x0200), two(0xf100, 0x0900), "uMumMh4/RneG", mcfemac },/* Ry,Rx,+1/-1,<ea>,accX.  */
-{"macl",  two(0120220, 0005000), two(0170670, 0005460), "R3R1MhasRn", mcf5206eup },
+
-{"macl",  two(0120230, 0005000), two(0170670, 0005460), "R3R1Mh+sRn", mcf5206eup },
+{"macl",  two(0xa000, 0x0800), two(0xf1b0, 0x0800), "RMRm", mcfmac },
-{"macl",  two(0120240, 0005000), two(0170670, 0005460), "R3R1Mh-sRn", mcf5206eup },
+{"macl",  two(0xa000, 0x0800), two(0xf1b0, 0x0b00), "RMRmiI", mcfmac },
-{"macl",  two(0120250, 0005000), two(0170670, 0005460), "R3R1MhdsRn", mcf5206eup },
+{"macl",  two(0xa000, 0x0a00), two(0xf1b0, 0x0b00), "RMRmMh", mcfmac },
-{"macml", two(0120220, 0004040), two(0170670, 0005460), "R3R1asRn", mcf5206eup },
+{"macl",  two(0xa080, 0x0800), two(0xf180, 0x0f30), "RNRo4/Rn", mcfmac },
-{"macml", two(0120230, 0004040), two(0170670, 0005460), "R3R1+sRn", mcf5206eup },
+{"macl",  two(0xa080, 0x0800), two(0xf180, 0x0910), "RNRoiI4/Rn", mcfmac },
-{"macml", two(0120240, 0004040), two(0170670, 0005460), "R3R1-sRn", mcf5206eup },
+{"macl",  two(0xa080, 0x0a00), two(0xf180, 0x0910), "RNRoMh4/Rn", mcfmac },
-{"macml", two(0120250, 0004040), two(0170670, 0005460), "R3R1dsRn", mcf5206eup },
+
-{"macml", two(0120220, 0005040), two(0170670, 0005460), "R3R1MhasRn", mcf5206eup },
+{"macl",  two(0xa000, 0x0800), two(0xf130, 0x0f00), "RMRmeH", mcfemac },
-{"macml", two(0120230, 0005040), two(0170670, 0005460), "R3R1Mh+sRn", mcf5206eup },
+{"macl",  two(0xa000, 0x0800), two(0xf130, 0x0900), "RMRmiIeH", mcfemac },
-{"macml", two(0120240, 0005040), two(0170670, 0005460), "R3R1Mh-sRn", mcf5206eup },
+{"macl",  two(0xa000, 0x0a00), two(0xf130, 0x0900), "RMRmMheH", mcfemac },
-{"macml", two(0120250, 0005040), two(0170670, 0005460), "R3R1MhdsRn", mcf5206eup },
+{"macl",  two(0xa000, 0x0800), two(0xf100, 0x0f00), "R3R14/RneG", mcfemac },
+{"macl",  two(0xa000, 0x0800), two(0xf100, 0x0900), "R3R1iI4/RneG", mcfemac },
+{"macl",  two(0xa000, 0x0a00), two(0xf100, 0x0900), "R3R1Mh4/RneG", mcfemac },
 
 /* NOTE: The mcf5200 family programmer's reference manual does not
    indicate the byte form of the movea instruction is invalid (as it
@@ -1518,6 +1507,8 @@ const struct m68k_opcode m68k_opcodes[] =
 {"moveal",	one(0020100),	one(0170700), "*lAd", m68000up | mcf },
 {"moveaw",	one(0030100),	one(0170700), "*wAd", m68000up | mcf },
 
+{"movclrl",	one(0xA1C0),	one(0xf9f0), "eFRs", mcfemac },
+
 {"movec",	one(0047173),	one(0177777), "R1Jj", m68010up | mcf },
 {"movec",	one(0047173),	one(0177777), "R1#j", m68010up | mcf },
 {"movec",	one(0047172),	one(0177777), "JjR1", m68010up },
@@ -1588,16 +1579,31 @@ const struct m68k_opcode m68k_opcodes[] =
 {"movel",	one(0020000),	one(0170000), "olnd", mcfv4up },
 {"movel",	one(0047140),	one(0177770), "AsUd", m68000up | mcfv4e },
 {"movel",	one(0047150),	one(0177770), "UdAs", m68000up | mcfv4e },
-{"movel",	one(0120600),	one(0177760), "EsRs", mcf5206eup },
+{"movel",	one(0120600),	one(0177760), "EsRs", mcfmac },
-{"movel",	one(0120400),	one(0177760), "RsEs", mcf5206eup },
+{"movel",	one(0120400),	one(0177760), "RsEs", mcfmac },
-{"movel",	one(0120474),	one(0177777), "#lEs", mcf5206eup },
+{"movel",	one(0120474),	one(0177777), "#lEs", mcfmac },
-{"movel",	one(0124600),	one(0177760), "GsRs", mcf5206eup },
+{"movel",	one(0124600),	one(0177760), "GsRs", mcfmac },
-{"movel",	one(0124400),	one(0177760), "RsGs", mcf5206eup },
+{"movel",	one(0124400),	one(0177760), "RsGs", mcfmac },
-{"movel",	one(0124474),	one(0177777), "#lGs", mcf5206eup },
+{"movel",	one(0124474),	one(0177777), "#lGs", mcfmac },
-{"movel",	one(0126600),	one(0177760), "HsRs", mcf5206eup },
+{"movel",	one(0126600),	one(0177760), "HsRs", mcfmac },
-{"movel",	one(0126400),	one(0177760), "RsHs", mcf5206eup },
+{"movel",	one(0126400),	one(0177760), "RsHs", mcfmac },
-{"movel",	one(0126474),	one(0177777), "#lHs", mcf5206eup },
+{"movel",	one(0126474),	one(0177777), "#lHs", mcfmac },
-{"movel",	one(0124700),	one(0177777), "GsCs", mcf5206eup },
+{"movel",	one(0124700),	one(0177777), "GsCs", mcfmac },
+
+{"movel",	one(0xa180),	one(0xf9f0), "eFRs", mcfemac }, /* ACCx,Rx.  */
+{"movel",	one(0xab80),	one(0xfbf0), "g]Rs", mcfemac }, /* ACCEXTx,Rx.  */
+{"movel",	one(0xa980),	one(0xfff0), "G-Rs", mcfemac }, /* macsr,Rx.  */
+{"movel",	one(0xad80),	one(0xfff0), "H-Rs", mcfemac }, /* mask,Rx.  */
+{"movel",	one(0xa110),	one(0xf9fc), "efeF", mcfemac }, /* ACCy,ACCx.  */
+{"movel",	one(0xa9c0),	one(0xffff), "G-C-", mcfemac }, /* macsr,ccr.  */
+{"movel",	one(0xa100),	one(0xf9f0), "RseF", mcfemac }, /* Rx,ACCx.  */
+{"movel",	one(0xa13c),	one(0xf9ff), "#leF", mcfemac }, /* #,ACCx.  */
+{"movel",	one(0xab00),	one(0xfbc0), "Rsg]", mcfemac }, /* Rx,ACCEXTx.  */
+{"movel",	one(0xab3c),	one(0xfbff), "#lg]", mcfemac }, /* #,ACCEXTx.  */
+{"movel",	one(0xa900),	one(0xffc0), "RsG-", mcfemac }, /* Rx,macsr.  */
+{"movel",	one(0xa93c),	one(0xffff), "#lG-", mcfemac }, /* #,macsr.  */
+{"movel",	one(0xad00),	one(0xffc0), "RsH-", mcfemac }, /* Rx,mask.  */
+{"movel",	one(0xad3c),	one(0xffff), "#lH-", mcfemac }, /* #,mask.  */
 
 {"move",	one(0030000),	one(0170000), "*w%d", m68000up },
 {"move",	one(0030000),	one(0170000), "ms%d", mcf },
@@ -1637,44 +1643,33 @@ const struct m68k_opcode m68k_opcodes[] =
 {"move16",	one(0xf610),		one(0xfff8), "as_L", m68040up },
 {"move16",	one(0xf618),		one(0xfff8), "_Las", m68040up },
 
-  /* FIXME: add MAM mode (`&' after <ea> operand) / remove MSACM */
+{"msacw",  two(0xa000, 0x0100), two(0xf1b0, 0x0800), "uMum", mcfmac },
-{"msacw",  two(0120000, 0000400), two(0170660, 0005400), "uMum", mcf5206eup },
+{"msacw",  two(0xa000, 0x0100), two(0xf1b0, 0x0b00), "uMumiI", mcfmac },
-{"msacw",  two(0120000, 0001400), two(0170660, 0005400), "uMumMh", mcf5206eup },
+{"msacw",  two(0xa000, 0x0300), two(0xf1b0, 0x0b00), "uMumMh", mcfmac },
-{"msacw",  two(0120220, 0000400), two(0170670, 0005460), "uNuoasRn", mcf5206eup },
+{"msacw",  two(0xa080, 0x0100), two(0xf180, 0x0f30), "uNuo4/Rn", mcfmac },
-{"msacw",  two(0120230, 0000400), two(0170670, 0005460), "uNuo+sRn", mcf5206eup },
+{"msacw",  two(0xa080, 0x0100), two(0xf180, 0x0910), "uNuoiI4/Rn", mcfmac },
-{"msacw",  two(0120240, 0000400), two(0170670, 0005460), "uNuo-sRn", mcf5206eup },
+{"msacw",  two(0xa080, 0x0300), two(0xf180, 0x0910), "uNuoMh4/Rn", mcfmac },
-{"msacw",  two(0120250, 0000400), two(0170670, 0005460), "uNuodsRn", mcf5206eup },
-{"msacw",  two(0120220, 0001400), two(0170670, 0005460), "uNuoMhasRn", mcf5206eup },
-{"msacw",  two(0120230, 0001400), two(0170670, 0005460), "uNuoMh+sRn", mcf5206eup },
-{"msacw",  two(0120240, 0001400), two(0170670, 0005460), "uNuoMh-sRn", mcf5206eup },
-{"msacw",  two(0120250, 0001400), two(0170670, 0005460), "uNuoMhdsRn", mcf5206eup },
-{"msacmw", two(0120220, 0000440), two(0170670, 0005460), "uNuoasRn", mcf5206eup },
-{"msacmw", two(0120230, 0000440), two(0170670, 0005460), "uNuo+sRn", mcf5206eup },
-{"msacmw", two(0120240, 0000440), two(0170670, 0005460), "uNuo-sRn", mcf5206eup },
-{"msacmw", two(0120250, 0000440), two(0170670, 0005460), "uNuodsRn", mcf5206eup },
-{"msacmw", two(0120220, 0001440), two(0170670, 0005460), "uNuoMhasRn", mcf5206eup },
-{"msacmw", two(0120230, 0001440), two(0170670, 0005460), "uNuoMh+sRn", mcf5206eup },
-{"msacmw", two(0120240, 0001440), two(0170670, 0005460), "uNuoMh-sRn", mcf5206eup },
-{"msacmw", two(0120250, 0001440), two(0170670, 0005460), "uNuoMhdsRn", mcf5206eup },
 
-{"msacl",  two(0120000, 0004400), two(0170660, 0005400), "RsRm", mcf5206eup },
+{"msacw",  two(0xa000, 0x0100), two(0xf130, 0x0f00), "uMumeH", mcfemac }, /* Ry,Rx,accX.  */
-{"msacl",  two(0120000, 0005400), two(0170660, 0005400), "RsRmMh", mcf5206eup },
+{"msacw",  two(0xa000, 0x0100), two(0xf130, 0x0900), "uMumiIeH", mcfemac },/* Ry,Rx,SF,accX.  */
-{"msacl",  two(0120220, 0004400), two(0170670, 0005460), "R3R1asRn", mcf5206eup },
+{"msacw",  two(0xa000, 0x0300), two(0xf130, 0x0900), "uMumMheH", mcfemac },/* Ry,Rx,+1/-1,accX.  */
-{"msacl",  two(0120230, 0004400), two(0170670, 0005460), "R3R1+sRn", mcf5206eup },
+{"msacw",  two(0xa000, 0x0100), two(0xf100, 0x0f00), "uMum4/RneG", mcfemac },/* Ry,Rx,<ea>,accX.  */
-{"msacl",  two(0120240, 0004400), two(0170670, 0005460), "R3R1-sRn", mcf5206eup },
+{"msacw",  two(0xa000, 0x0100), two(0xf100, 0x0900), "uMumiI4/RneG", mcfemac },/* Ry,Rx,SF,<ea>,accX.  */
-{"msacl",  two(0120250, 0004400), two(0170670, 0005460), "R3R1dsRn", mcf5206eup },
+{"msacw",  two(0xa000, 0x0300), two(0xf100, 0x0900), "uMumMh4/RneG", mcfemac },/* Ry,Rx,+1/-1,<ea>,accX.  */
-{"msacl",  two(0120220, 0005400), two(0170670, 0005460), "R3R1MhasRn", mcf5206eup },
+
-{"msacl",  two(0120230, 0005400), two(0170670, 0005460), "R3R1Mh+sRn", mcf5206eup },
+{"msacl",  two(0xa000, 0x0900), two(0xf1b0, 0x0800), "RMRm", mcfmac },
-{"msacl",  two(0120240, 0005400), two(0170670, 0005460), "R3R1Mh-sRn", mcf5206eup },
+{"msacl",  two(0xa000, 0x0900), two(0xf1b0, 0x0b00), "RMRmiI", mcfmac },
-{"msacl",  two(0120250, 0005400), two(0170670, 0005460), "R3R1MhdsRn", mcf5206eup },
+{"msacl",  two(0xa000, 0x0b00), two(0xf1b0, 0x0b00), "RMRmMh", mcfmac },
-{"msacml", two(0120220, 0004440), two(0170670, 0005460), "R3R1asRn", mcf5206eup },
+{"msacl",  two(0xa080, 0x0900), two(0xf180, 0x0f30), "RNRo4/Rn", mcfmac },
-{"msacml", two(0120230, 0004440), two(0170670, 0005460), "R3R1+sRn", mcf5206eup },
+{"msacl",  two(0xa080, 0x0900), two(0xf180, 0x0910), "RNRoiI4/Rn", mcfmac },
-{"msacml", two(0120240, 0004440), two(0170670, 0005460), "R3R1-sRn", mcf5206eup },
+{"msacl",  two(0xa080, 0x0b00), two(0xf180, 0x0910), "RNRoMh4/Rn", mcfmac },
-{"msacml", two(0120250, 0004440), two(0170670, 0005460), "R3R1dsRn", mcf5206eup },
+
-{"msacml", two(0120220, 0005440), two(0170670, 0005460), "R3R1MhasRn", mcf5206eup },
+{"msacl",  two(0xa000, 0x0900), two(0xf130, 0x0f00), "RMRmeH", mcfemac },
-{"msacml", two(0120230, 0005440), two(0170670, 0005460), "R3R1Mh+sRn", mcf5206eup },
+{"msacl",  two(0xa000, 0x0900), two(0xf130, 0x0900), "RMRmiIeH", mcfemac },
-{"msacml", two(0120240, 0005440), two(0170670, 0005460), "R3R1Mh-sRn", mcf5206eup },
+{"msacl",  two(0xa000, 0x0b00), two(0xf130, 0x0900), "RMRmMheH", mcfemac },
-{"msacml", two(0120250, 0005440), two(0170670, 0005460), "R3R1MhdsRn", mcf5206eup },
+{"msacl",  two(0xa000, 0x0900), two(0xf100, 0x0f00), "R3R14/RneG", mcfemac },
+{"msacl",  two(0xa000, 0x0900), two(0xf100, 0x0900), "R3R1iI4/RneG", mcfemac },
+{"msacl",  two(0xa000, 0x0b00), two(0xf100, 0x0900), "R3R1Mh4/RneG", mcfemac },
 
 {"mulsw",	one(0140700),		one(0170700), ";wDd", m68000up|mcf },
 {"mulsl",	two(0046000,004000), two(0177700,0107770), ";lD1", m68020up|cpu32 },