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h8300: Add support of EXR register

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This commit is contained in:
Andrey Volkov 2002-05-17 19:19:24 +00:00
parent a8cdafbd4e
commit fc97460264
6 changed files with 104 additions and 12 deletions
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5
gdb/ChangeLog
View file

@ -1,3 +1,8 @@
2002-05-17 Andrey Volkov <avolkov@transas.com>
* h8300-tdep.c: Add support of EXR register
* config/h8300/tm-h8300.h: Ditto.
2002-05-17 Andrey Volkov <avolkov@transas.com>
* h8300-tdep.c: Add additional CCR flags (I,UI,H,U)

7
gdb/config/h8300/tm-h8300.h
View file

@ -100,7 +100,7 @@ extern CORE_ADDR h8300_skip_prologue ();
#define REGISTER_SIZE 4
#define NUM_REGS 13
#define NUM_REGS 14
#define REGISTER_BYTES (NUM_REGS * 4)
@ -137,7 +137,7 @@ extern CORE_ADDR h8300_skip_prologue ();
Entries beyond the first NUM_REGS are ignored. */
#define REGISTER_NAMES \
{"r0", "r1", "r2", "r3", "r4", "r5", "r6", "sp", "ccr","pc","cycles","tick","inst"}
{"r0", "r1", "r2", "r3", "r4", "r5", "r6", "sp", "ccr","pc","cycles","tick","inst",""}
/* An array of names of registers. */
@ -157,6 +157,7 @@ extern char **h8300_register_names;
#define SP_REGNUM 7 /* Contains address of top of stack */
#define CCR_REGNUM 8 /* Contains processor status */
#define PC_REGNUM 9 /* Contains program counter */
#define EXR_REGNUM 11 /* Contains processor status */
/* Extract from an array REGBUF containing the (raw) register state
a function return value of type TYPE, and copy that, in virtual format,
@ -272,7 +273,7 @@ extern void h8300_print_register_hook (int);
#define GDB_TARGET_IS_H8300
#define NUM_REALREGS 10
#define NUM_REALREGS (h8300smode?11:10)
#define NOP { 0x01, 0x80} /* A sleep insn */
#define BELIEVE_PCC_PROMOTION 1

20
gdb/h8300-tdep.c
View file

@ -39,8 +39,8 @@
extern int h8300hmode, h8300smode;
#undef NUM_REGS
#define NUM_REGS 11
#undef NUM_REGS
#define NUM_REGS (h8300smode?12:11)
#define UNSIGNED_SHORT(X) ((X) & 0xffff)
@ -62,7 +62,7 @@ static char *original_register_names[] = REGISTER_NAMES;
static char *h8300h_register_names[] =
{"er0", "er1", "er2", "er3", "er4", "er5", "er6",
"sp", "ccr", "pc", "cycles", "tick", "inst"};
"sp", "ccr","pc", "cycles", "exr", "tick", "inst"};
char **h8300_register_names = original_register_names;
@ -871,6 +871,20 @@ h8300_print_register_hook (int regno)
if ((Z | (N ^ V)) == 1)
printf_unfiltered ("<= ");
}
if (regno == EXR_REGNUM && h8300smode)
{
/* EXR register */
unsigned char b[REGISTER_SIZE];
unsigned char l;
read_relative_register_raw_bytes (regno, b);
l = b[REGISTER_VIRTUAL_SIZE (EXR_REGNUM) - 1];
printf_unfiltered ("\t");
printf_unfiltered ("T-%d - - - ", (l & 0x80) != 0);
printf_unfiltered ("I2-%d ", (l & 4) != 0);
printf_unfiltered ("I1-%d ", (l & 2) != 0);
printf_unfiltered ("I0-%d", (l & 1) != 0);
}
}
void

5
sim/h8300/ChangeLog
View file

@ -1,3 +1,8 @@
2002-05-17 Andrey Volkov (avolkov@transas.com)
* compile.c: Add support of EXR register
* inst.h: Ditto.
2002-05-17 Andrey Volkov (avolkov@transas.com)
* compile.c: Made h8300s as new target, not h8300h alias.

76
sim/h8300/compile.c
View file

@ -67,6 +67,7 @@ void sim_set_simcache_size PARAMS ((int));
#define OP_CCR 7
#define OP_IMM 8
#define OP_ABS 10
#define OP_EXR 11
#define h8_opcodes ops
#define DEFINE_TABLE
#include "opcode/h8300.h"
@ -84,6 +85,9 @@ void sim_set_simcache_size PARAMS ((int));
#define BUILDSR() cpu.ccr = (I << 7) | (UI << 6)| (H<<5) | (U<<4) | \
(N << 3) | (Z << 2) | (V<<1) | C;
#define BUILDEXR() \
if( h8300smode ) cpu.exr = ( trace<<7 ) | intMask;
#define GETSR() \
c = (cpu.ccr >> 0) & 1;\
v = (cpu.ccr >> 1) & 1;\
@ -94,6 +98,11 @@ void sim_set_simcache_size PARAMS ((int));
ui = ((cpu.ccr >> 6) & 1);\
intMaskBit = (cpu.ccr >> 7) & 1;
#define GETEXR() \
if( h8300smode ) { \
trace = (cpu.exr >> 7) & 1;\
intMask = cpu.exr & 7; }
#ifdef __CHAR_IS_SIGNED__
#define SEXTCHAR(x) ((char) (x))
#endif
@ -412,6 +421,10 @@ decode (addr, data, dst)
{
p->type = OP_CCR;
}
else if (x & EXR)
{
p->type = OP_EXR;
}
else
printf ("Hmmmm %x", x);
@ -946,6 +959,7 @@ sim_resume (sd, step, siggnal)
int bit;
int pc;
int c, nz, v, n, u, h, ui, intMaskBit;
int trace, intMask;
int oldmask;
init_pointers ();
@ -969,6 +983,8 @@ sim_resume (sd, step, siggnal)
abort ();
GETSR ();
GETEXR ();
oldmask = cpu.mask;
if (!h8300hmode)
cpu.mask = 0xffff;
@ -1180,21 +1196,49 @@ sim_resume (sd, step, siggnal)
#define GET_CCR(x) BUILDSR();x = cpu.ccr
#define GET_EXR(x) BUILDEXR();x = cpu.exr
case O (O_ANDC, SB):
GET_CCR (rd);
if(code->dst.type==OP_CCR)
{
GET_CCR (rd);
}
else if(code->dst.type==OP_EXR && h8300smode)
{
GET_EXR (rd);
}
else
goto illegal;
ea = code->src.literal;
res = rd & ea;
goto setc;
case O (O_ORC, SB):
GET_CCR (rd);
if(code->dst.type==OP_CCR)
{
GET_CCR (rd);
}
else if(code->dst.type==OP_EXR && h8300smode)
{
GET_EXR (rd);
}
else
goto illegal;
ea = code->src.literal;
res = rd | ea;
goto setc;
case O (O_XORC, SB):
GET_CCR (rd);
if(code->dst.type==OP_CCR)
{
GET_CCR (rd);
}
else if(code->dst.type==OP_EXR && h8300smode)
{
GET_EXR (rd);
}
else
goto illegal;
ea = code->src.literal;
res = rd ^ ea;
goto setc;
@ -1541,6 +1585,7 @@ sim_resume (sd, step, siggnal)
goto next;
default:
illegal:
cpu.state = SIM_STATE_STOPPED;
cpu.exception = SIGILL;
goto end;
@ -1549,8 +1594,19 @@ sim_resume (sd, step, siggnal)
abort ();
setc:
cpu.ccr = res;
GETSR ();
if(code->dst.type==OP_CCR)
{
cpu.ccr = res;
GETSR ();
}
else if(code->dst.type==OP_EXR && h8300smode)
{
cpu.exr = res;
GETEXR ();
}
else
goto illegal;
goto next;
condtrue:
@ -1730,6 +1786,7 @@ sim_resume (sd, step, siggnal)
cpu.pc = pc;
BUILDSR ();
BUILDEXR();
cpu.mask = oldmask;
signal (SIGINT, prev);
}
@ -1802,6 +1859,7 @@ sim_read (sd, addr, buffer, size)
#define PC_REGNUM 9 /* Contains program counter */
#define CYCLE_REGNUM 10
#define EXR_REGNUM 11 /* Contains extended processor status */
#define INST_REGNUM 11
#define TICK_REGNUM 12
@ -1841,6 +1899,9 @@ sim_store_register (sd, rn, value, length)
case CCR_REGNUM:
cpu.ccr = intval;
break;
case EXR_REGNUM:
cpu.exr = intval;
break;
case CYCLE_REGNUM:
cpu.cycles = longval;
break;
@ -1868,6 +1929,8 @@ sim_fetch_register (sd, rn, buf, length)
init_pointers ();
if(!h8300smode && rn >=EXR_REGNUM)
rn++;
switch (rn)
{
default:
@ -1875,6 +1938,9 @@ sim_fetch_register (sd, rn, buf, length)
case CCR_REGNUM:
v = cpu.ccr;
break;
case EXR_REGNUM:
v = cpu.exr;
break;
case PC_REGNUM:
v = cpu.pc;
break;

3
sim/h8300/inst.h
View file

@ -32,6 +32,7 @@ typedef enum
R_ZERO,
R_PC,
R_CCR,
R_EXR,
R_HARD_0,
R_LAST,
} reg_type;
@ -73,7 +74,7 @@ typedef struct
unsigned int regs[9];
int pc;
int ccr;
int exr;
unsigned char *memory;
unsigned char *eightbit;