Added DMAC unit test cases.
This commit is contained in:
James Lemke
parent
121d6745bc
commit
fc609c6c69
4 changed files with 580 additions and 2 deletions
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@ -1,3 +1,8 @@
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Fri Mar 20 17:41:07 1998 Jim Lemke <jlemke@cygnus.com>
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* t-dma.c: Created file of DMAC unit tests.
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* sky.ld: Created file to load tests at a lower addr.
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Tue Mar 17 15:41:07 1998 Frank Ch. Eigler <fche@cygnus.com>
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* c_gen.pl: Added file from Toronto's /build directory.
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@ -76,6 +76,7 @@ C_GEN = perl $(srcdir)/c_gen.pl
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.SUFFIXES: .trc .c .run .ok .vif0out .vif0ok .vif0expect .vif1out .vif1ok .vif1expect .uu
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TESTS = \
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t-dma.ok \
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t-pke1.vif0ok \
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t-pke2.vif1ok \
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t-pke3.ok \
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@ -143,7 +144,7 @@ sanity:
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.trc.c:
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$(C_GEN) $< $@
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.c.run:
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$(GCC_FOR_TARGET) -Tr5900.ld -o $@ $<
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$(GCC_FOR_TARGET) -T$(srcdir)/sky.ld -o $@ $<
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.uu.run:
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uudecode $< > $@
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.run.vif0out:
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87
sim/testsuite/sky/sky.ld
Normal file
87
sim/testsuite/sky/sky.ld
Normal file
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@ -0,0 +1,87 @@
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/* This is just the basic idt.ld linker script file, except that it has
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a different OUTPUT_ARCH to force the linker into r5900 mode which
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uses 32bit addresses. */
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/* The following TEXT start address leaves space for the monitor
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workspace. i.e. the NEC VR4300 (IDT) first free address is actually
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0xa001af20. */
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ENTRY(_start)
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OUTPUT_ARCH("mips:5900")
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OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-littlemips")
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GROUP(-lc -lidt -lgcc)
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SEARCH_DIR(.)
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__DYNAMIC = 0;
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/*
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* Allocate the stack to be at the top of memory, since the stack
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* grows down
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*/
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PROVIDE (__stack = 0);
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/* PROVIDE (__global = 0); */
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/*
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* Initalize some symbols to be zero so we can reference them in the
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* crt0 without core dumping. These functions are all optional, but
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* we do this so we can have our crt0 always use them if they exist.
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* This is so BSPs work better when using the crt0 installed with gcc.
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* We have to initalize them twice, so we multiple object file
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* formats, as some prepend an underscore.
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*/
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PROVIDE (hardware_init_hook = 0);
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PROVIDE (software_init_hook = 0);
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SECTIONS
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{
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. = 0x00010000;
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.text : {
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_ftext = . ;
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*(.init)
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eprol = .;
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*(.text)
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*(.mips16.fn.*)
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*(.mips16.call.*)
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PROVIDE (__runtime_reloc_start = .);
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*(.rel.sdata)
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PROVIDE (__runtime_reloc_stop = .);
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*(.fini)
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etext = .;
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_etext = .;
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}
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. = .;
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.rdata : {
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*(.rdata)
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}
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_fdata = ALIGN(16);
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.data : {
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*(.data)
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CONSTRUCTORS
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}
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. = ALIGN(8);
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_gp = . + 0x8000;
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__global = _gp;
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.lit8 : {
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*(.lit8)
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}
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.lit4 : {
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*(.lit4)
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}
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.sdata : {
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*(.sdata)
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}
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. = ALIGN(4);
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edata = .;
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_edata = .;
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_fbss = .;
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.sbss : {
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*(.sbss)
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*(.scommon)
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}
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.bss : {
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_bss_start = . ;
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*(.bss)
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*(COMMON)
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}
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end = .;
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_end = .;
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}
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485
sim/testsuite/sky/t-dma.c
Normal file
485
sim/testsuite/sky/t-dma.c
Normal file
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@ -0,0 +1,485 @@
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#include <stdio.h>
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#include <string.h>
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#define error(x) { printf(x); exit( 999); }
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void wrtest( unsigned *reg, unsigned w, unsigned e)
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{
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unsigned r;
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*reg = w;
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r = *reg;
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if( r != e)
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{
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printf( "wrtest: at 0x%08lx wrote=0x%08x read=0x%08x expected=0x%08x\n",
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reg, w, r, e);
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exit( 999);
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}
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}
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/*
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DMA tag in target format (LE).
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BE=0x00000000_00000000_aaaaaaa0_ip00cccc
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*/
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typedef struct { unsigned tagL __attribute__ ((aligned (16))), tagH, pke1, pke0; } quad;
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quad data0 = { 3, 2, 1, 0};
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/* DMArefe 1, data0 */ quad dma_refe = { 0x0c000001, 000, 0, 0};
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/* DMAcnt 2 */ quad dma_cnt = { 0x10000002, 0, 0, 0};
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quad data1 = { 7, 6, 5, 4};
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quad data2 = { 11, 10, 9, 8};
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/* DMAnext 3,dma_ref */ quad dma_next = { 0x20000003, 000, 0, 0};
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quad data3 = { 15, 14, 13, 12};
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quad data4 = { 19, 18, 17, 16};
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quad data5 = { 23, 22, 21, 20};
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quad data6 = { 27, 26, 25, 24};
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quad data7 = { 31, 30, 29, 28};
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quad data8 = { 35, 34, 33, 32};
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/* DMAref 1,data6 */ quad dma_ref = { 0x30000001, 000, 0, 0};
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/* DMArefs 2,data7 */ quad dma_refs = { 0x40000002, 000, 0, 0};
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/* DMAcall 3,dma_cal2 */quad dma_call = { 0x50000003, 000, 0, 0};
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quad data9 = { 39, 38, 37, 36};
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quad dataA = { 43, 42, 41, 40};
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quad dataB = { 47, 46, 45, 44};
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/* DMAend 1 */ quad dma_end = { 0x78000001, 0, 0, 0};
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quad dataE = { 59, 58, 57, 56};
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/* DMAcall 1,dma_rt2 */ quad dma_cal2 = { 0x50000001, 000, 0, 0 };
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quad dataC = { 51, 50, 49, 48};
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/* DMAret 0 */ quad dma_ret = { 0x60000000, 0, 0, 0};
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/* DMAret 1 */ quad dma_rt2 = { 0x60000001, 0, 0, 0};
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quad dataD = { 55, 54, 53, 52};
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int main()
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{
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#define DMA_D0_START 0x10008000
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#define DMA_D0_CHCR (unsigned*) 0x10008000
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#define DMA_Dn_CHCR__STR 0x00000100
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#define DMA_Dn_CHCR__TIE 0x00000080
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#define DMA_Dn_CHCR__TTE 0x00000040
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#define DMA_Dn_CHCR__MOD 0x0000000c
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#define DMA_Dn_CHCR__MOD_NORM 0x00000000
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#define DMA_Dn_CHCR__MOD_CHAIN 0x00000004
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#define DMA_Dn_CHCR__DIR 0x00000001
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#define DMA_D0_MADR (unsigned*) 0x10008010
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#define DMA_D0_QWC (unsigned*) 0x10008020
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#define DMA_D0_TADR (unsigned*) 0x10008030
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#define DMA_D0_ASR0 (unsigned*) 0x10008040
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#define DMA_D0_ASR1 (unsigned*) 0x10008050
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#define DMA_D0_PKTFLAG (unsigned*) 0x10008060 /* virtual reg to indicate presence of tag in data */
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#define DMA_D0_END 0x10008070
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#define DMA_D1_START 0x10009000
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#define DMA_D1_CHCR (unsigned*) 0x10009000
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#define DMA_D1_MADR (unsigned*) 0x10009010
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#define DMA_D1_QWC (unsigned*) 0x10009020
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#define DMA_D1_TADR (unsigned*) 0x10009030
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#define DMA_D1_ASR0 (unsigned*) 0x10009040
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#define DMA_D1_ASR1 (unsigned*) 0x10009050
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#define DMA_D1_PKTFLAG (unsigned*) 0x10009060 /* virtual reg to indicate presence of tag in data */
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#define DMA_D1_END 0x10009070
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#define DMA_D2_START 0x1000a000
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#define DMA_D2_CHCR (unsigned*) 0x1000a000
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#define DMA_D2_MADR (unsigned*) 0x1000a010
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#define DMA_D2_QWC (unsigned*) 0x1000a020
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#define DMA_D2_TADR (unsigned*) 0x1000a030
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#define DMA_D2_ASR0 (unsigned*) 0x1000a040
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#define DMA_D2_ASR1 (unsigned*) 0x1000a050
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#define DMA_D2_PKTFLAG (unsigned*) 0x1000a060 /* virtual reg to indicate presence of tag in data */
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#define DMA_D2_END 0x1000a070
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#define DMA_D_CTRL (unsigned*) 0x1000e000
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#define DMA_D_CTRL__DMAE 0x00000001
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#define DMA_D_STAT (unsigned*) 0x1000e010
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#define DMA_D_STAT__TOGGLE 0x63ff0000
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#define DMA_D_STAT__CLEAR 0x0000e3ff
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#define DMA_D_PCR (unsigned*) 0x1000e020
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#define DMA_D_PCR__PCE 0x80000000
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#define DMA_D_PCR__CDE 0x03ff0000
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#define DMA_D_PCR__CDE0 0x00010000
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#define DMA_D_PCR__CDE1 0x00020000
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#define DMA_D_PCR__CDE2 0x00040000
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#define DMA_D_SQWC (unsigned*) 0x1000e030
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#define DMA_D_RBSR (unsigned*) 0x1000e040
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#define DMA_D_RBOR (unsigned*) 0x1000e050
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#define DMA_D_STADR (unsigned*) 0x1000e060
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#define DMA_TAG_IRQ 0x80000000;
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unsigned *reg, temp;
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printf( "Testing DMA_D_CTRL...\n");
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reg = DMA_D_CTRL;
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if( *reg) error( "Not initialized to zero.\n");
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wrtest( reg, 0x00000555, 0x00000555);
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wrtest( reg, 0x000002aa, 0x000002aa);
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*reg = 0;
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printf( "Testing DMA_D_STAT...\n");
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reg = DMA_D_STAT;
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if( *reg) error( "Not initialized to zero.\n");
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wrtest( reg, 0xffffffff, 0x63ff0000);
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wrtest( reg, 0x63ff0000, 0x00000000);
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printf( "Testing DMA_D_PCR...\n");
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reg = DMA_D_PCR;
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if( *reg) error( "Not initialized to zero.\n");
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wrtest( reg, 0x80000000, 0x83ff0000);
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wrtest( reg, 0x8fff0000, 0x83ff0000);
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wrtest( reg, 0x05550000, 0x01550000);
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wrtest( reg, 0x0155aaaa, 0x015502aa);
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wrtest( reg, 0x00005555, 0x00000155);
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*reg = 0;
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printf( "Testing DMA_D_SQWC...\n");
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reg = DMA_D_SQWC;
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if( *reg) error( "Not initialized to zero.\n");
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wrtest( reg, 0x5555aaaa, 0x005500aa);
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wrtest( reg, 0xaaaa5555, 0x00aa0055);
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*reg = 0;
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printf( "Testing DMA_D_RBOR...\n");
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reg = DMA_D_RBOR;
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if( *reg) error( "Not initialized to zero.\n");
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wrtest( reg, 0x5555aaaa, 0x5555aaa0);
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wrtest( reg, 0xaaaa5555, 0x2aaa5550);
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*reg = 0;
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printf( "Testing DMA_D_RBSR...\n");
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reg = DMA_D_RBSR;
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if( *reg) error( "Not initialized to zero.\n");
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wrtest( reg, 0x5555aaaa, 0x5555aaa0);
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wrtest( reg, 0xaaaa5555, 0x2aaa5550);
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*reg = 0;
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printf( "Testing DMA_D_STADR...\n");
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reg = DMA_D_STADR;
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if( *reg) error( "Not initialized to zero.\n");
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wrtest( reg, 0x5555aaaa, 0x5555aaa0);
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wrtest( reg, 0xaaaa5555, 0x2aaa5550);
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*reg = 0;
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printf( "Testing DMA_D0_CHCR...\n");
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reg = DMA_D0_CHCR;
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if( *reg) error( "Not initialized to zero.\n");
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wrtest( reg, 0x5555aaaa, 0x000000aa);
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wrtest( reg, 0xaaaa5555, 0x00000155);
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*reg = 0;
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printf( "Testing DMA_D0_MADR...\n");
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reg = DMA_D0_MADR;
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if( *reg) error( "Not initialized to zero.\n");
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wrtest( reg, 0x5555aaaa, 0x5555aaa0);
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wrtest( reg, 0x2aaa5555, 0x2aaa5550);
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*reg = 0;
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printf( "Testing DMA_D0_TADR...\n");
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reg = DMA_D0_TADR;
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if( *reg) error( "Not initialized to zero.\n");
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wrtest( reg, 0x5555aaaa, 0x5555aaa0);
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wrtest( reg, 0x2aaa5555, 0x2aaa5550);
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*reg = 0;
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printf( "Testing DMA_D0_ASR0...\n");
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reg = DMA_D0_ASR0;
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if( *reg) error( "Not initialized to zero.\n");
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wrtest( reg, 0x5555aaaa, 0x5555aaa0);
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wrtest( reg, 0x2aaa5555, 0x2aaa5550);
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*reg = 0;
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printf( "Testing DMA_D0_ASR1...\n");
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reg = DMA_D0_ASR1;
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if( *reg) error( "Not initialized to zero.\n");
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wrtest( reg, 0x5555aaaa, 0x5555aaa0);
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wrtest( reg, 0x2aaa5555, 0x2aaa5550);
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*reg = 0;
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printf( "Testing DMA_D0_QWC...\n");
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reg = DMA_D0_QWC;
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if( *reg) error( "Not initialized to zero.\n");
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wrtest( reg, 0x5555aaaa, 0x0000aaaa);
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wrtest( reg, 0xaaaa5555, 0x00005555);
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*reg = 0;
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printf( "Testing DMA_D0_PKTFLAG...\n");
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reg = DMA_D0_PKTFLAG;
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if( *reg) error( "Not initialized to zero.\n");
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wrtest( reg, 0x5555aaaa, 0x5555aaaa);
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wrtest( reg, 0xaaaa5555, 0xaaaa5555);
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*reg = 0;
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printf( "Testing DMA_D1_CHCR...\n");
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reg = DMA_D1_CHCR;
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if( *reg) error( "Not initialized to zero.\n");
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wrtest( reg, 0x5555aaaa, 0x000000aa);
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wrtest( reg, 0xaaaa5555, 0x00000155);
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*reg = 0;
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printf( "Testing DMA_D1_MADR...\n");
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reg = DMA_D1_MADR;
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if( *reg) error( "Not initialized to zero.\n");
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wrtest( reg, 0x5555aaaa, 0x5555aaa0);
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wrtest( reg, 0x2aaa5555, 0x2aaa5550);
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*reg = 0;
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printf( "Testing DMA_D1_TADR...\n");
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reg = DMA_D1_TADR;
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if( *reg) error( "Not initialized to zero.\n");
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wrtest( reg, 0x5555aaaa, 0x5555aaa0);
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wrtest( reg, 0x2aaa5555, 0x2aaa5550);
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*reg = 0;
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printf( "Testing DMA_D1_ASR0...\n");
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reg = DMA_D1_ASR0;
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if( *reg) error( "Not initialized to zero.\n");
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wrtest( reg, 0x5555aaaa, 0x5555aaa0);
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wrtest( reg, 0x2aaa5555, 0x2aaa5550);
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*reg = 0;
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printf( "Testing DMA_D1_ASR1...\n");
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reg = DMA_D1_ASR1;
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if( *reg) error( "Not initialized to zero.\n");
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wrtest( reg, 0x5555aaaa, 0x5555aaa0);
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wrtest( reg, 0x2aaa5555, 0x2aaa5550);
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*reg = 0;
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printf( "Testing DMA_D1_QWC...\n");
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reg = DMA_D1_QWC;
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if( *reg) error( "Not initialized to zero.\n");
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wrtest( reg, 0x5555aaaa, 0x0000aaaa);
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wrtest( reg, 0xaaaa5555, 0x00005555);
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*reg = 0;
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printf( "Testing DMA_D1_PKTFLAG...\n");
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reg = DMA_D1_PKTFLAG;
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if( *reg) error( "Not initialized to zero.\n");
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wrtest( reg, 0x5555aaaa, 0x5555aaaa);
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wrtest( reg, 0xaaaa5555, 0xaaaa5555);
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*reg = 0;
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printf( "Testing DMA_D2_CHCR...\n");
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reg = DMA_D2_CHCR;
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if( *reg) error( "Not initialized to zero.\n");
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wrtest( reg, 0x5555aaaa, 0x000000aa);
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wrtest( reg, 0xaaaa5555, 0x00000155);
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*reg = 0;
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printf( "Testing DMA_D2_MADR...\n");
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reg = DMA_D2_MADR;
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if( *reg) error( "Not initialized to zero.\n");
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wrtest( reg, 0x5555aaaa, 0x5555aaa0);
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wrtest( reg, 0x2aaa5555, 0x2aaa5550);
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*reg = 0;
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printf( "Testing DMA_D2_TADR...\n");
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reg = DMA_D2_TADR;
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if( *reg) error( "Not initialized to zero.\n");
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wrtest( reg, 0x5555aaaa, 0x5555aaa0);
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wrtest( reg, 0x2aaa5555, 0x2aaa5550);
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*reg = 0;
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printf( "Testing DMA_D2_ASR0...\n");
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reg = DMA_D2_ASR0;
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if( *reg) error( "Not initialized to zero.\n");
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wrtest( reg, 0x5555aaaa, 0x5555aaa0);
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wrtest( reg, 0x2aaa5555, 0x2aaa5550);
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*reg = 0;
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printf( "Testing DMA_D2_ASR1...\n");
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reg = DMA_D2_ASR1;
|
||||
if( *reg) error( "Not initialized to zero.\n");
|
||||
wrtest( reg, 0x5555aaaa, 0x5555aaa0);
|
||||
wrtest( reg, 0x2aaa5555, 0x2aaa5550);
|
||||
*reg = 0;
|
||||
|
||||
printf( "Testing DMA_D2_QWC...\n");
|
||||
reg = DMA_D2_QWC;
|
||||
if( *reg)
|
||||
{
|
||||
printf ("Not initialized to zero (0x%08x).\n", *reg);
|
||||
exit (999);
|
||||
}
|
||||
wrtest( reg, 0x5555aaaa, 0x0000aaaa);
|
||||
wrtest( reg, 0xaaaa5555, 0x00005555);
|
||||
*reg = 0;
|
||||
|
||||
printf( "Testing DMA_D2_PKTFLAG...\n");
|
||||
reg = DMA_D2_PKTFLAG;
|
||||
if( *reg) error( "Not initialized to zero.\n");
|
||||
wrtest( reg, 0x5555aaaa, 0x5555aaaa);
|
||||
wrtest( reg, 0xaaaa5555, 0xaaaa5555);
|
||||
*reg = 0;
|
||||
|
||||
/* Initiate a non-chained 0-length transfer. */
|
||||
printf ("\nPreparing for a DMA1 NORM transfer...\n");
|
||||
reg = DMA_D_CTRL; /* enable DMA */
|
||||
*reg = DMA_D_CTRL__DMAE;
|
||||
reg = DMA_D1_QWC; /* set # of quad words to xfr */
|
||||
*reg = 0;
|
||||
reg = DMA_D1_MADR; /* set data address */
|
||||
*reg = 0x00012340;
|
||||
reg = DMA_D1_CHCR;
|
||||
printf ("Ready...\n");
|
||||
*reg = DMA_Dn_CHCR__STR | DMA_Dn_CHCR__MOD_NORM;
|
||||
|
||||
reg = DMA_D1_QWC;
|
||||
if (*reg)
|
||||
{
|
||||
printf ("D1_QWC is not zero after transfer.\n");
|
||||
exit (999);
|
||||
}
|
||||
reg = DMA_D1_MADR;
|
||||
if (*reg != 0x00012340)
|
||||
{
|
||||
printf ("D1_MADR value is wrong after transfer.\n");
|
||||
exit (999);
|
||||
}
|
||||
reg = DMA_D1_CHCR;
|
||||
if ((*reg & DMA_Dn_CHCR__STR) != 0)
|
||||
{
|
||||
printf ("D1_CHCR.STR is not reset after transfer.\n");
|
||||
exit (999);
|
||||
}
|
||||
printf ("Completed OK...\n");
|
||||
|
||||
/* Initiate a chained transfer. */
|
||||
|
||||
/* Some of the "tag" fields couldn't be initialised statically. */
|
||||
/* The first address is unaligned to force a warning. */
|
||||
dma_refe.tagH = (unsigned)&data0 + 1;
|
||||
dma_next.tagH = (unsigned)&dma_ref;
|
||||
dma_ref.tagH = (unsigned)&data6;
|
||||
dma_refs.tagH = (unsigned)&data7;
|
||||
dma_call.tagH = (unsigned)&dma_cal2;
|
||||
dma_cal2.tagH = (unsigned)&dma_rt2;
|
||||
|
||||
printf ("\nPreparing for a DMA0 TAG transfer...\n");
|
||||
reg = DMA_D_PCR; /* disable DMA0 */
|
||||
*reg &= ~DMA_D_PCR__CDE0;
|
||||
*reg |= DMA_D_PCR__PCE;
|
||||
reg = DMA_D_CTRL; /* enable DMA */
|
||||
*reg = DMA_D_CTRL__DMAE;
|
||||
reg = DMA_D0_TADR; /* set tag address */
|
||||
*reg = (unsigned) & dma_refe;
|
||||
reg = DMA_D0_QWC; /* set fictitious count */
|
||||
*reg = 51;
|
||||
printf ("Ready...\n");
|
||||
reg = DMA_D0_CHCR;
|
||||
*reg = DMA_Dn_CHCR__STR | DMA_Dn_CHCR__TTE | DMA_Dn_CHCR__MOD_CHAIN;
|
||||
|
||||
reg = DMA_D0_QWC;
|
||||
if (*reg != 51)
|
||||
{
|
||||
printf ("DMA0 transfer not inhibited by DMA_D_PCR__CDE0 (%d).\n", *reg);
|
||||
exit (999);
|
||||
}
|
||||
reg = DMA_D_PCR; /* enable DMA0 */
|
||||
*reg &= ~DMA_D_PCR__PCE;
|
||||
|
||||
reg = DMA_D0_QWC;
|
||||
if (*reg)
|
||||
{
|
||||
printf ("D0_QWC is not zero after transfer.\n");
|
||||
exit (999);
|
||||
}
|
||||
reg = DMA_D0_MADR;
|
||||
if (*reg != (unsigned)&dma_cal2)
|
||||
{
|
||||
printf ("D0_MADR value is wrong after transfer.\n");
|
||||
exit (999);
|
||||
}
|
||||
reg = DMA_D0_CHCR;
|
||||
if ((*reg & DMA_Dn_CHCR__STR) != 0)
|
||||
{
|
||||
printf ("D0_CHCR.STR is not reset after transfer.\n");
|
||||
exit (999);
|
||||
}
|
||||
printf ("Completed OK...\n");
|
||||
|
||||
/* Initiate a chained transfer that will be suspended
|
||||
and restarted. */
|
||||
|
||||
/* Request suspension part way through. */
|
||||
dma_ref.tagL |= DMA_TAG_IRQ;
|
||||
|
||||
printf ("\nPreparing for a DMA2 TAG transfer with suspension...\n");
|
||||
reg = DMA_D_CTRL; /* enable DMA */
|
||||
*reg = DMA_D_CTRL__DMAE;
|
||||
reg = DMA_D2_TADR; /* set tag address */
|
||||
*reg = (unsigned) & dma_refe;
|
||||
printf ("Ready...\n");
|
||||
reg = DMA_D2_CHCR;
|
||||
*reg = DMA_Dn_CHCR__STR | DMA_Dn_CHCR__MOD_CHAIN;
|
||||
printf ("returns...\n");
|
||||
|
||||
reg = DMA_D2_QWC;
|
||||
if (*reg)
|
||||
{
|
||||
printf ("D2_QWC (0x%08x) is not zero after suspension.\n", *reg);
|
||||
exit (999);
|
||||
}
|
||||
reg = DMA_D2_MADR;
|
||||
if (*reg != (unsigned)&data7)
|
||||
{
|
||||
printf ("D2_MADR value (0x%08x) is wrong after suspension.\n", *reg);
|
||||
exit (999);
|
||||
}
|
||||
reg = DMA_D2_TADR;
|
||||
if (*reg != (unsigned)&dma_refs)
|
||||
{
|
||||
printf ("D2_TADR value (0x%08x) is wrong after suspension.\n", *reg);
|
||||
exit (999);
|
||||
}
|
||||
reg = DMA_D2_CHCR;
|
||||
if ((*reg & DMA_Dn_CHCR__STR) != 0)
|
||||
{
|
||||
printf ("D2_CHCR.STR (0x%08x) is not reset after suspension.\n", *reg);
|
||||
exit (999);
|
||||
}
|
||||
reg = DMA_D_PCR;
|
||||
if ((*reg & DMA_D_PCR__PCE) == 0)
|
||||
{
|
||||
printf ("DMA_D_PCR__PCE not set by transfer.\n");
|
||||
exit (999);
|
||||
}
|
||||
printf ("Suspended OK...\n");
|
||||
|
||||
/* Reset the suspension request and continue. */
|
||||
dma_ref.tagL &= ~DMA_TAG_IRQ;
|
||||
reg = DMA_D2_CHCR;
|
||||
*reg |= DMA_Dn_CHCR__STR;
|
||||
|
||||
reg = DMA_D2_QWC;
|
||||
if (*reg)
|
||||
{
|
||||
printf ("D2_QWC (0x%08x) is not zero after transfer.\n", *reg);
|
||||
exit (999);
|
||||
}
|
||||
reg = DMA_D2_MADR;
|
||||
if (*reg != (unsigned)&dma_cal2)
|
||||
{
|
||||
printf ("D2_MADR value (0x%08x) is wrong after transfer.\n", *reg);
|
||||
exit (999);
|
||||
}
|
||||
reg = DMA_D2_CHCR;
|
||||
if ((*reg & DMA_Dn_CHCR__STR) != 0)
|
||||
{
|
||||
printf ("D2_CHCR.STR (0x%08x) is not reset after transfer.\n", *reg);
|
||||
exit (999);
|
||||
}
|
||||
reg = DMA_D_PCR;
|
||||
if (*reg & DMA_D_PCR__PCE)
|
||||
{
|
||||
printf ("DMA_D_PCR__PCE not reset by transfer.\n");
|
||||
exit (999);
|
||||
}
|
||||
printf ("Completed OK...\n");
|
||||
|
||||
exit (0);
|
||||
}
|
||||
Loading…
Reference in a new issue