- Added almost all code needed for PKE0/1 simulation. Considers
clarifications given in SCEI question/answer batches #1 and #2.
This commit is contained in:
Frank Ch. Eigler
parent
4434e2dc4e
commit
fba9bfed2d
2 changed files with 1462 additions and 100 deletions
1272
sim/mips/sky-pke.c
1272
sim/mips/sky-pke.c
File diff suppressed because it is too large
Load diff
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@ -7,6 +7,11 @@
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#include "sky-device.h"
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/* Debugguing PKE? */
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#define PKE_DEBUG
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/* External functions */
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void pke0_attach(SIM_DESC sd);
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@ -17,7 +22,7 @@ void pke1_issue();
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/* Quadword data type */
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typedef unsigned int quadword[4];
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typedef unsigned_4 quadword[4];
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/* truncate address to quadword */
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#define ADDR_TRUNC_QW(addr) ((addr) & ~0x0f)
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@ -29,8 +34,8 @@ typedef unsigned int quadword[4];
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#define PKE0_REGISTER_WINDOW_START 0x10000800
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#define PKE1_REGISTER_WINDOW_START 0x10000A00
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#define PKE0_FIFO_START 0x10008000
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#define PKE1_FIFO_START 0x10008010
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#define PKE0_FIFO_ADDR 0x10008000
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#define PKE1_FIFO_ADDR 0x10008010
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/* Quadword indices of PKE registers. Actual registers sit at bottom
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@ -51,11 +56,11 @@ typedef unsigned int quadword[4];
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#define PKE_REG_ITOP 0x0d
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#define PKE_REG_TOP 0x0e /* pke1 only */
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#define PKE_REG_DBF 0x0f /* pke1 only */
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#define PKE_REG_R0 0x10
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#define PKE_REG_R0 0x10 /* R0 .. R3 must be contiguous */
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#define PKE_REG_R1 0x11
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#define PKE_REG_R2 0x12
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#define PKE_REG_R3 0x13
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#define PKE_REG_C0 0x14
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#define PKE_REG_C0 0x14 /* C0 .. C3 must be contiguous */
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#define PKE_REG_C1 0x15
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#define PKE_REG_C2 0x16
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#define PKE_REG_C3 0x17
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@ -64,11 +69,273 @@ typedef unsigned int quadword[4];
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#define PKE_REGISTER_WINDOW_SIZE (sizeof(quadword) * PKE_NUM_REGS)
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/* virtual addresses for source-addr tracking */
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#define PKE0_SRCADDR 0x20000020
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#define PKE1_SRCADDR 0x20000024
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/* PKE commands */
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#define PKE_CMD_PKENOP_MASK 0x7F
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#define PKE_CMD_PKENOP_BITS 0x00
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#define PKE_CMD_STCYCL_MASK 0x7F
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#define PKE_CMD_STCYCL_BITS 0x01
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#define PKE_CMD_OFFSET_MASK 0x7F
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#define PKE_CMD_OFFSET_BITS 0x02
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#define PKE_CMD_BASE_MASK 0x7F
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#define PKE_CMD_BASE_BITS 0x03
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#define PKE_CMD_ITOP_MASK 0x7F
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#define PKE_CMD_ITOP_BITS 0x04
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#define PKE_CMD_STMOD_MASK 0x7F
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#define PKE_CMD_STMOD_BITS 0x05
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#define PKE_CMD_MSKPATH3_MASK 0x7F
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#define PKE_CMD_MSKPATH3_BITS 0x06
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#define PKE_CMD_PKEMARK_MASK 0x7F
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#define PKE_CMD_PKEMARK_BITS 0x07
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#define PKE_CMD_FLUSHE_MASK 0x7F
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#define PKE_CMD_FLUSHE_BITS 0x10
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#define PKE_CMD_FLUSH_MASK 0x7F
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#define PKE_CMD_FLUSH_BITS 0x11
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#define PKE_CMD_FLUSHA_MASK 0x7F
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#define PKE_CMD_FLUSHA_BITS 0x13
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#define PKE_CMD_PKEMSCAL_MASK 0x7F /* CAL == "call" */
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#define PKE_CMD_PKEMSCAL_BITS 0x14
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#define PKE_CMD_PKEMSCNT_MASK 0x7F /* CNT == "continue" */
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#define PKE_CMD_PKEMSCNT_BITS 0x17
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#define PKE_CMD_PKEMSCALF_MASK 0x7F /* CALF == "call after flush" */
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#define PKE_CMD_PKEMSCALF_BITS 0x15
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#define PKE_CMD_STMASK_MASK 0x7F
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#define PKE_CMD_STMASK_BITS 0x20
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#define PKE_CMD_STROW_MASK 0x7F
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#define PKE_CMD_STROW_BITS 0x30
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#define PKE_CMD_STCOL_MASK 0x7F
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#define PKE_CMD_STCOL_BITS 0x31
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#define PKE_CMD_MPG_MASK 0x7F
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#define PKE_CMD_MPG_BITS 0x4A
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#define PKE_CMD_DIRECT_MASK 0x7F
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#define PKE_CMD_DIRECT_BITS 0x50
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#define PKE_CMD_DIRECTHL_MASK 0x7F
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#define PKE_CMD_DIRECTHL_BITS 0x51
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#define PKE_CMD_UNPACK_MASK 0x60
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#define PKE_CMD_UNPACK_BITS 0x60
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/* test given word for particular PKE command bit pattern */
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#define IS_PKE_CMD(word,cmd) (((word) & PKE_CMD_##cmd##_MASK) == PKE_CMD_##cmd##_BITS)
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/* register bitmasks: bit numbers for end and beginning of fields */
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/* PKE opcode */
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#define PKE_OPCODE_I_E 31
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#define PKE_OPCODE_I_B 31
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#define PKE_OPCODE_CMD_E 30
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#define PKE_OPCODE_CMD_B 24
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#define PKE_OPCODE_NUM_E 23
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#define PKE_OPCODE_NUM_B 16
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#define PKE_OPCODE_IMM_E 15
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#define PKE_OPCODE_IMM_B 0
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/* STAT register */
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#define PKE_REG_STAT_FQC_E 28
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#define PKE_REG_STAT_FQC_B 24
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#define PKE_REG_STAT_FDR_E 23
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#define PKE_REG_STAT_FDR_B 23
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#define PKE_REG_STAT_ER1_E 13
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#define PKE_REG_STAT_ER1_B 13
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#define PKE_REG_STAT_ER0_E 12
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#define PKE_REG_STAT_ER0_B 12
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#define PKE_REG_STAT_INT_E 11
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#define PKE_REG_STAT_INT_B 11
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#define PKE_REG_STAT_PIS_E 10
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#define PKE_REG_STAT_PIS_B 10
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#define PKE_REG_STAT_PFS_E 9
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#define PKE_REG_STAT_PFS_B 9
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#define PKE_REG_STAT_PSS_E 8
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#define PKE_REG_STAT_PSS_B 8
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#define PKE_REG_STAT_DBF_E 7
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#define PKE_REG_STAT_DBF_B 7
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#define PKE_REG_STAT_MRK_E 6
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#define PKE_REG_STAT_MRK_B 6
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#define PKE_REG_STAT_PGW_E 3
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#define PKE_REG_STAT_PGW_B 3
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#define PKE_REG_STAT_PEW_E 2
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#define PKE_REG_STAT_PEW_B 2
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#define PKE_REG_STAT_PPS_E 1
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#define PKE_REG_STAT_PPS_B 0
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#define PKE_REG_STAT_PPS_IDLE 0x00
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#define PKE_REG_STAT_PPS_WAIT 0x01
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#define PKE_REG_STAT_PPS_DECODE 0x02
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#define PKE_REG_STAT_PPS_XFER 0x03
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/* DBF register */
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#define PKE_REG_DBF_DF_E 0
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#define PKE_REG_DBF_DF_B 0
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/* OFST register */
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#define PKE_REG_OFST_OFFSET_E 9
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#define PKE_REG_OFST_OFFSET_B 0
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/* OFST register */
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#define PKE_REG_TOPS_TOPS_E 9
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#define PKE_REG_TOPS_TOPS_B 0
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/* BASE register */
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#define PKE_REG_BASE_BASE_E 9
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#define PKE_REG_BASE_BASE_B 0
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/* ITOPS register */
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#define PKE_REG_ITOPS_ITOPS_E 9
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#define PKE_REG_ITOPS_ITOPS_B 0
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/* MODE register */
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#define PKE_REG_MODE_MDE_E 1
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#define PKE_REG_MODE_MDE_B 0
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/* MARK register */
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#define PKE_REG_MARK_MARK_E 15
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#define PKE_REG_MARK_MARK_B 0
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/* ITOP register */
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#define PKE_REG_ITOP_ITOP_E 9
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#define PKE_REG_ITOP_ITOP_B 0
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/* TOP register */
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#define PKE_REG_TOP_TOP_E 9
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#define PKE_REG_TOP_TOP_B 0
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/* MASK register */
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#define PKE_REG_MASK_MASK_E 31
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#define PKE_REG_MASK_MASK_B 0
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/* CYCLE register */
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#define PKE_REG_CYCLE_WL_E 15
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#define PKE_REG_CYCLE_WL_B 8
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#define PKE_REG_CYCLE_CL_E 7
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#define PKE_REG_CYCLE_CL_B 0
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/* ERR register */
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#define PKE_REG_ERR_ME1_E 2
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#define PKE_REG_ERR_ME1_B 2
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#define PKE_REG_ERR_ME0_E 1
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#define PKE_REG_ERR_ME0_B 1
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#define PKE_REG_ERR_MII_E 0
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#define PKE_REG_ERR_MII_B 0
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/* source-addr for words written to VU/GPUIF ports */
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#define PKE0_SRCADDR 0x20000020 /* from 1998-01-22 e-mail plans */
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#define PKE1_SRCADDR 0x20000024 /* from 1998-01-22 e-mail plans */
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/* UNPACK opcodes */
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#define PKE_UNPACK(vn,vl) ((vn) << 2 | (vl))
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#define PKE_UNPACK_S_32 PKE_UNPACK(0, 0)
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#define PKE_UNPACK_S_16 PKE_UNPACK(0, 1)
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#define PKE_UNPACK_S_8 PKE_UNPACK(0, 2)
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#define PKE_UNPACK_V2_32 PKE_UNPACK(1, 0)
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#define PKE_UNPACK_V2_16 PKE_UNPACK(1, 1)
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#define PKE_UNPACK_V2_8 PKE_UNPACK(1, 2)
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#define PKE_UNPACK_V3_32 PKE_UNPACK(2, 0)
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#define PKE_UNPACK_V3_16 PKE_UNPACK(2, 1)
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#define PKE_UNPACK_V3_8 PKE_UNPACK(2, 2)
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#define PKE_UNPACK_V4_32 PKE_UNPACK(3, 0)
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#define PKE_UNPACK_V4_16 PKE_UNPACK(3, 1)
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#define PKE_UNPACK_V4_8 PKE_UNPACK(3, 2)
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#define PKE_UNPACK_V4_5 PKE_UNPACK(3, 3)
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/* MASK register sub-field definitions */
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#define PKE_MASKREG_INPUT 0
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#define PKE_MASKREG_ROW 1
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#define PKE_MASKREG_COLUMN 2
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#define PKE_MASKREG_NOTHING 3
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/* STMOD register field definitions */
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#define PKE_MODE_INPUT 0
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#define PKE_MODE_ADDROW 1
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#define PKE_MODE_ACCROW 2
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/* extract a MASK register sub-field for row [0..3] and column [0..3] */
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/* MASK register is laid out of 2-bit values in this r-c order */
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/* m33 m32 m31 m30 m23 m22 m21 m20 m13 m12 m11 m10 m03 m02 m01 m00 */
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#define PKE_MASKREG_GET(me,row,col) \
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((((me)->regs[PKE_REG_MASK][0]) >> (8*(row) + 2*(col))) & 0x03)
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/* and now a few definitions that rightfully belong elsewhere */
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#ifdef PKE_DEBUG
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/* GPUIF addresses */
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#define GPUIF_PATH3_FIFO_ADDR 0x10008020 /* data from CORE */
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#define GPUIF_PATH1_FIFO_ADDR 0x10008030 /* data from VU1 */
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#define GPUIF_PATH2_FIFO_ADDR 0x10008040 /* data from PKE1 */
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/* VU STAT register */
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#define VU_REG_STAT_VGW_E 4
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#define VU_REG_STAT_VGW_B 4
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#define VU_REG_STAT_VBS_E 0
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#define VU_REG_STAT_VBS_B 0
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/* VU PC pseudo-registers */ /* omitted from 1998-01-22 e-mail plans */
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#define VU0_PC_START 0x20025000
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#define VU1_PC_START 0x20026000
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/* VU source-addr tracking tables */ /* changed from 1998-01-22 e-mail plans */
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#define VU0_MEM0_SRCADDR_START 0x21000000
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#define VU0_MEM1_SRCADDR_START 0x21004000
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#define VU1_MEM0_SRCADDR_START 0x21008000
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#define VU1_MEM1_SRCADDR_START 0x2100C000
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#endif /* PKE_DEBUG */
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/* operations */
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/* unsigned 32-bit mask of given width */
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#define BIT_MASK(width) ((((unsigned_4)1) << (width+1)) - 1)
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/* e.g.: BIT_MASK(5) = 00011111 */
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/* mask between given given bits numbers (MSB) */
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#define BIT_MASK_BTW(begin,end) (BIT_MASK(end) & ~BIT_MASK(begin))
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/* e.g.: BIT_MASK_BTW(4,11) = 0000111111110000 */
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/* set bitfield value */
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#define BIT_MASK_SET(lvalue,begin,end,value) \
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do { \
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lvalue &= ~BIT_MASK_BTW(begin,end); \
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lvalue |= (((value) << (begin)) & BIT_MASK_BTW(begin,end)); \
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} while(0)
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/* get bitfield value */
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#define BIT_MASK_GET(rvalue,begin,end) \
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(((rvalue) & BIT_MASK_BTW(begin,end)) >> (begin))
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/* e.g., BIT_MASK_GET(0000111100001111, 2, 8) = 0000000100001100 */
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/* get bitfield value, sign-extended to given bit number */
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#define BIT_MASK_GET_SX(rvalue,begin,end,sx) \
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(BIT_MASK_GET(rvalue,begin,end) | ((BIT_MASK_GET(rvalue,begin,end) & BIT_MASK_BTW(end,end)) ? BIT_MASK_BTW(end,sx) : 0))
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/* e.g., BIT_MASK_GET_SX(0000111100001111, 2, 8, 15) = 1111111100001100 */
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/* These ugly macro hacks allow succinct bitfield accesses */
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/* set a bitfield in a register by "name" */
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#define PKE_REG_MASK_SET(me,reg,flag,value) \
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BIT_MASK_SET(((me)->regs[PKE_REG_##reg][0]), \
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PKE_REG_##reg##_##flag##_B, PKE_REG_##reg##_##flag##_E, \
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(value))
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/* get a bitfield from a register by "name" */
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#define PKE_REG_MASK_GET(me,reg,flag) \
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BIT_MASK_GET(((me)->regs[PKE_REG_##reg][0]), \
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PKE_REG_##reg##_##flag##_B, PKE_REG_##reg##_##flag##_E)
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#define PKE_LIMIT(value,max) ((value) > (max) ? (max) : (value))
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/* One row in the FIFO */
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struct fifo_quadword
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{
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@ -76,6 +343,8 @@ struct fifo_quadword
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quadword data;
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/* source main memory address (or 0: unknown) */
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address_word source_address;
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/* DMA tag present in lower 64 bits */
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unsigned_4 dma_tag_present;
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};
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@ -89,9 +358,6 @@ struct pke_device
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int pke_number;
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int flags;
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address_word register_memory_addr;
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address_word fifo_memory_addr;
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/* quadword registers */
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quadword regs[PKE_NUM_REGS];
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@ -100,10 +366,11 @@ struct pke_device
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int fifo_num_elements; /* no. of quadwords occupied in FIFO */
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int fifo_buffer_size; /* no. of quadwords of space in FIFO */
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FILE* fifo_trace_file; /* or 0 for no trace */
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/* XXX: assumes FIFOs grow indefinately */
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/* index into FIFO of current instruction */
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int program_counter;
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/* PC */
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int fifo_pc; /* 0 .. (fifo_num_elements-1): quadword index of next instruction */
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int qw_pc; /* 0 .. 3: word index of next instruction */
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};
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@ -113,5 +380,4 @@ struct pke_device
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/* none at present */
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#endif /* H_PKE_H */
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