More mult-arch conversions: IEEE_FLOAT, SKIP_PROLOGUE,
SAVED_PC_AFTER_CALL, DECR_PC_AFTER_BREAK, BREAKPOINT_FROM_PC, INNER_THAN.
This commit is contained in:
Andrew Cagney
parent
f19ebbbc84
commit
f7b9e9fc07
3 changed files with 40 additions and 65 deletions
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@ -1,3 +1,17 @@
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Fri Jul 7 18:29:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
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* config/mips/tm-mips.h (IEEE_FLOAT, SKIP_PROLOGUE,
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SAVED_PC_AFTER_CALL, DECR_PC_AFTER_BREAK, BREAKPOINT_FROM_PC,
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INNER_THAN): Macros.
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* mips-tdep.c (mips_in_lenient_prologue): Delete function.
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(mips32_skip_prologue, mips16_skip_prologue, mips_skip_prologue):
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Remove ``lenient'' argument.
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(mips_saved_pc_after_call): New function.
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(mips_gdbarch_init): Initialize gdbarch members inner_than,
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breakpoint_from_pc, decr_pc_after_break, ieee_float,
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skip_prologue, saved_pc_after_call.
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2000-07-07 Mark Kettenis <kettenis@gnu.org>
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* config/i386/tm-linux.h: Add longjmp support.
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@ -47,9 +47,6 @@ struct value;
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#define GDB_TARGET_UNMASK_DISAS_PC(addr) MAKE_MIPS16_ADDR(addr)
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#endif
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/* Floating point is IEEE compliant */
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#define IEEE_FLOAT (1)
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/* The name of the usual type of MIPS processor that is in the target
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system. */
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@ -69,50 +66,17 @@ CORE_ADDR mips_addr_bits_remove (CORE_ADDR addr);
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#define FUNCTION_START_OFFSET 0
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/* Advance PC across any function entry prologue instructions
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to reach some "real" code. */
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#define SKIP_PROLOGUE(pc) (mips_skip_prologue (pc, 0))
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extern CORE_ADDR mips_skip_prologue (CORE_ADDR addr, int lenient);
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/* Return non-zero if PC points to an instruction which will cause a step
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to execute both the instruction at PC and an instruction at PC+4. */
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extern int mips_step_skips_delay (CORE_ADDR);
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#define STEP_SKIPS_DELAY_P (1)
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#define STEP_SKIPS_DELAY(pc) (mips_step_skips_delay (pc))
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/* Immediately after a function call, return the saved pc.
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Can't always go through the frames for this because on some machines
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the new frame is not set up until the new function executes
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some instructions. */
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#define SAVED_PC_AFTER_CALL(frame) read_register(RA_REGNUM)
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/* Are we currently handling a signal */
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extern int in_sigtramp (CORE_ADDR, char *);
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#define IN_SIGTRAMP(pc, name) in_sigtramp(pc, name)
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/* Stack grows downward. */
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#define INNER_THAN(lhs,rhs) ((lhs) < (rhs))
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/* BREAKPOINT_FROM_PC uses the program counter value to determine whether a
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16- or 32-bit breakpoint should be used. It returns a pointer
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to a string of bytes that encode a breakpoint instruction, stores
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the length of the string to *lenptr, and adjusts the pc (if necessary) to
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point to the actual memory location where the breakpoint should be
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inserted. */
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extern breakpoint_from_pc_fn mips_breakpoint_from_pc;
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#define BREAKPOINT_FROM_PC(pcptr, lenptr) mips_breakpoint_from_pc(pcptr, lenptr)
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/* Amount PC must be decremented by after a breakpoint.
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This is often the number of bytes in BREAKPOINT
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but not always. */
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#define DECR_PC_AFTER_BREAK 0
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/* Say how long (ordinary) registers are. This is a piece of bogosity
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used in push_word and a few other places; REGISTER_RAW_SIZE is the
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real way to know how big a register is. */
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@ -2841,9 +2841,7 @@ mips_step_skips_delay (pc)
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This is a helper function for mips_skip_prologue. */
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static CORE_ADDR
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mips32_skip_prologue (pc, lenient)
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CORE_ADDR pc; /* starting PC to search from */
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int lenient;
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mips32_skip_prologue (CORE_ADDR pc)
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{
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t_inst inst;
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CORE_ADDR end_pc;
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@ -2937,9 +2935,7 @@ mips32_skip_prologue (pc, lenient)
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This is a helper function for mips_skip_prologue. */
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static CORE_ADDR
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mips16_skip_prologue (pc, lenient)
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CORE_ADDR pc; /* starting PC to search from */
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int lenient;
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mips16_skip_prologue (CORE_ADDR pc)
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{
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CORE_ADDR end_pc;
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int extend_bytes = 0;
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@ -3051,9 +3047,7 @@ mips16_skip_prologue (pc, lenient)
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delay slot of a non-prologue instruction). */
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CORE_ADDR
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mips_skip_prologue (pc, lenient)
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CORE_ADDR pc;
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int lenient;
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mips_skip_prologue (CORE_ADDR pc)
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{
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/* See if we can determine the end of the prologue via the symbol table.
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If so, then return either PC, or the PC after the prologue, whichever
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@ -3068,29 +3062,11 @@ mips_skip_prologue (pc, lenient)
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instructions. */
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if (pc_is_mips16 (pc))
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return mips16_skip_prologue (pc, lenient);
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return mips16_skip_prologue (pc);
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else
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return mips32_skip_prologue (pc, lenient);
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return mips32_skip_prologue (pc);
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}
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#if 0
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/* The lenient prologue stuff should be superseded by the code in
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init_extra_frame_info which looks to see whether the stores mentioned
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in the proc_desc have actually taken place. */
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/* Is address PC in the prologue (loosely defined) for function at
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STARTADDR? */
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static int
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mips_in_lenient_prologue (startaddr, pc)
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CORE_ADDR startaddr;
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CORE_ADDR pc;
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{
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CORE_ADDR end_prologue = mips_skip_prologue (startaddr, 1);
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return pc >= startaddr && pc < end_prologue;
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}
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#endif
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/* Determine how a return value is stored within the MIPS register
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file, given the return type `valtype'. */
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@ -3930,6 +3906,19 @@ mips_get_saved_register (raw_buffer, optimized, addrp, frame, regnum, lval)
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*addrp = addr;
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}
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/* Immediately after a function call, return the saved pc.
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Can't always go through the frames for this because on some machines
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the new frame is not set up until the new function executes
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some instructions. */
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static CORE_ADDR
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mips_saved_pc_after_call (struct frame_info *frame)
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{
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return read_register (RA_REGNUM);
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}
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static gdbarch_init_ftype mips_gdbarch_init;
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static struct gdbarch *
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mips_gdbarch_init (info, arches)
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@ -4235,6 +4224,14 @@ mips_gdbarch_init (info, arches)
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set_gdbarch_frame_chain_valid (gdbarch, func_frame_chain_valid);
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set_gdbarch_get_saved_register (gdbarch, mips_get_saved_register);
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set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
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set_gdbarch_breakpoint_from_pc (gdbarch, mips_breakpoint_from_pc);
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set_gdbarch_decr_pc_after_break (gdbarch, 0);
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set_gdbarch_ieee_float (gdbarch, 1);
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set_gdbarch_skip_prologue (gdbarch, mips_skip_prologue);
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set_gdbarch_saved_pc_after_call (gdbarch, mips_saved_pc_after_call);
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return gdbarch;
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}
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