* tc-txvu.c: First pass at dma/pke/gpuif support.
(assemble_one_insn): Renamed from assemble_insn. Initialize errmsg = NULL before calling parse fn. (fixups,fixup_count): Make static globals.
This commit is contained in:
Doug Evans
parent
f31e207296
commit
f73062614b
2 changed files with 161 additions and 94 deletions
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@ -1,3 +1,12 @@
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start-sanitize-sky
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Mon Jan 26 16:29:49 1998 Doug Evans <devans@seba.cygnus.com>
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* tc-txvu.c: First pass at dma/pke/gpuif support.
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(assemble_one_insn): Renamed from assemble_insn.
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Initialize errmsg = NULL before calling parse fn.
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(fixups,fixup_count): Make static globals.
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end-sanitize-sky
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Mon Jan 26 13:07:41 1998 Nick Clifton <nickc@cygnus.com>
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* config/tc-m32r.c: Detect if explicitly parallel instructions
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@ -1,5 +1,5 @@
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/* tc-txvu.c -- Assembler for the TX VU.
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Copyright (C) 1997 Free Software Foundation.
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Copyright (C) 1997, 1998 Free Software Foundation.
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This file is part of GAS, the GNU Assembler.
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@ -40,7 +40,7 @@ const char FLT_CHARS[] = "dD";
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/* Non-zero if in vu-mode. */
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static int vu_mode_p;
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/* Non-zero if packing pke instructions with dma tags. */
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/* Non-zero if packing pke instructions in dma tags. */
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static int dma_pack_pke_p;
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const char *md_shortopts = "";
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@ -121,6 +121,8 @@ md_begin ()
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vu_mode_p = 0;
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dma_pack_pke_p = 0;
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}
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enum cputype { CPU_VUUP, CPU_VULO, CPU_DMA, CPU_PKE, CPU_GPUIF };
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/* We need to keep a list of fixups. We can't simply generate them as
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we go, because that would require us to first create the frag, and
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@ -135,16 +137,30 @@ struct txvu_fixup
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#define MAX_FIXUPS 5
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static int fixup_count;
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static struct txvu_fixup fixups[MAX_FIXUPS];
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static void assemble_dma PARAMS ((char *));
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static void assemble_gpuif PARAMS ((char *));
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static void assemble_pke PARAMS ((char *));
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static void assemble_vu PARAMS ((char *));
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static char * assemble_vu_insn PARAMS ((char *, int, char *));
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static char * assemble_vu_insn PARAMS ((enum cputype,
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const struct txvu_opcode *,
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const struct txvu_operand *,
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char *, char *));
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static char * assemble_one_insn PARAMS ((enum cputype,
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const struct txvu_opcode *,
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const struct txvu_operand *,
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char *, TXVU_INSN *));
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void
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md_assemble (str)
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char *str;
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{
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/* Skip leading white space. */
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while (isspace (*str))
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str++;
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if (! vu_mode_p)
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{
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if (strncasecmp (str, "dma", 3) == 0)
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@ -158,28 +174,43 @@ md_assemble (str)
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assemble_vu (str);
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}
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/* Subroutine of assemble_dpg to assemble DMA instructions. */
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/* Subroutine of md_assemble to assemble DMA instructions. */
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static void
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assemble_dma (str)
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char *str;
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{
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TXVU_INSN buf[4];
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assemble_one_insn (CPU_DMA,
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dma_opcode_lookup_asm (str), dma_operands,
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str, buf);
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}
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/* Subroutine of assemble_dpg to assemble GPUIF instructions. */
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static void
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assemble_gpuif (str)
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char *str;
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{
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}
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/* Subroutine of assemble_dpg to assemble PKE instructions. */
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/* Subroutine of md_assemble to assemble PKE instructions. */
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static void
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assemble_pke (str)
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char *str;
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{
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TXVU_INSN buf[4];
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assemble_one_insn (CPU_PKE,
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pke_opcode_lookup_asm (str), pke_operands,
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str, buf);
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}
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/* Subroutine of md_assemble to assemble GPUIF instructions. */
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static void
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assemble_gpuif (str)
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char *str;
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{
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TXVU_INSN buf[4];
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assemble_one_insn (CPU_GPUIF,
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gpuif_opcode_lookup_asm (str), gpuif_operands,
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str, buf);
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}
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/* Subroutine of md_assemble to assemble VU instructions. */
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@ -203,54 +234,98 @@ assemble_vu (str)
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}
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*p = 0;
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assemble_vu_insn (str, 0, f + 4);
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assemble_vu_insn (CPU_VUUP,
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txvu_upper_opcode_lookup_asm (str), txvu_operands,
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str, f + 4);
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*p = '|';
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assemble_vu_insn (p + 1, 1, f);
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assemble_vu_insn (CPU_VULO,
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txvu_lower_opcode_lookup_asm (str), txvu_operands,
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p + 1, f);
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#else
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str = assemble_vu_insn (str, 0, f + 4);
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str = assemble_vu_insn (CPU_VUUP,
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txvu_upper_opcode_lookup_asm (str), txvu_operands,
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str, f + 4);
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/* Don't assemble next one if we couldn't assemble the first. */
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if (str)
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assemble_vu_insn (str, 1, f);
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assemble_vu_insn (CPU_VULO,
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txvu_lower_opcode_lookup_asm (str), txvu_operands,
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str, f);
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#endif
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}
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/* Assemble one instruction.
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LOWER_P is non-zero if assembling in the lower insn slot.
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The result is a pointer to beyond the end of the scanned insn
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or NULL if an error occured.
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If this is the upper insn, the caller can pass back to result to us
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parse the lower insn. */
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static char *
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assemble_vu_insn (str, lower_p, buf)
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assemble_vu_insn (cpu, opcode, operand_table, str, buf)
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enum cputype cpu;
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const struct txvu_opcode *opcode;
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const struct txvu_operand *operand_table;
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char *str;
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int lower_p;
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char *buf;
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{
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const struct txvu_opcode *opcode;
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char *start;
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int i;
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TXVU_INSN insn;
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/* Skip leading white space. */
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while (isspace (*str))
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str++;
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str = assemble_one_insn (cpu, opcode, operand_table, str, &insn);
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if (str == NULL)
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return NULL;
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/* The instructions are stored in lists hashed by the first letter (though
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we needn't care how they're hashed). Get the first in the list. */
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/* Write out the instruction.
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Reminder: it is important to fetch enough space in one call to
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`frag_more'. We use (f - frag_now->fr_literal) to compute where
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we are and we don't want frag_now to change between calls. */
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md_number_to_chars (buf, insn, 4);
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if (lower_p)
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opcode = txvu_lower_opcode_lookup_asm (str);
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else
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opcode = txvu_upper_opcode_lookup_asm (str);
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/* Create any fixups. */
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for (i = 0; i < fixup_count; ++i)
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{
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int op_type, reloc_type;
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const struct txvu_operand *operand;
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/* Create a fixup for this operand.
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At this point we do not use a bfd_reloc_code_real_type for
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operands residing in the insn, but instead just use the
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operand index. This lets us easily handle fixups for any
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operand type, although that is admittedly not a very exciting
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feature. We pick a BFD reloc type in md_apply_fix. */
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op_type = fixups[i].opindex;
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reloc_type = op_type + (int) BFD_RELOC_UNUSED;
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operand = &txvu_operands[op_type];
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fix_new_exp (frag_now, buf - frag_now->fr_literal, 4,
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&fixups[i].exp,
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(operand->flags & TXVU_OPERAND_RELATIVE_BRANCH) != 0,
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(bfd_reloc_code_real_type) reloc_type);
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}
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/* All done. */
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return str;
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}
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/* Assemble one instruction.
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CPU indicates what component we're assembling for.
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The assembled instruction is stored in INSN_BUF.
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The result is a pointer to beyond the end of the scanned insn
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or NULL if an error occured. This is to handle the VU where two
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instructions appear on one line. If this is the upper insn, the caller
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can pass back to result to us parse the lower insn. */
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static char *
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assemble_one_insn (cpu, opcode, operand_table, str, insn_buf)
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enum cputype cpu;
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const struct txvu_opcode *opcode;
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const struct txvu_operand *operand_table;
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char *str;
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TXVU_INSN *insn_buf;
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{
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char *start;
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/* Keep looking until we find a match. */
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start = str;
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for ( ; opcode != NULL; opcode = TXVU_OPCODE_NEXT_ASM (opcode))
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{
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int past_opcode_p, fc, num_suffixes, num_operands;
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int past_opcode_p, num_suffixes, num_operands;
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const unsigned char *syn;
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struct txvu_fixup fixups[MAX_FIXUPS];
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/* Ensure the mnemonic part matches. */
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for (str = start, syn = opcode->mnemonic; *syn != '\0'; ++str, ++syn)
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/* Scan the syntax string. If it doesn't match, try the next one. */
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txvu_opcode_init_parse ();
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insn = opcode->value;
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fc = 0;
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*insn_buf = opcode->value;
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fixup_count = 0;
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past_opcode_p = 0;
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num_suffixes = 0;
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num_operands = 0;
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/* We have a suffix or an operand. Pick out any modifiers. */
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mods = 0;
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index = TXVU_OPERAND_INDEX (*syn);
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while (TXVU_MOD_P (txvu_operands[index].flags))
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while (TXVU_MOD_P (operand_table[index].flags))
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{
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mods |= txvu_operands[index].flags & TXVU_MOD_BITS;
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mods |= operand_table[index].flags & TXVU_MOD_BITS;
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++syn;
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index = TXVU_OPERAND_INDEX (*syn);
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}
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operand = txvu_operands + index;
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operand = operand_table + index;
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if (operand->flags & TXVU_OPERAND_FAKE)
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{
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if (operand->insert)
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{
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errmsg = NULL;
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insn = (*operand->insert) (insn, operand, mods, 0, &errmsg);
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(*operand->insert) (insn_buf, operand, mods, 0, &errmsg);
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/* If we get an error, go on to try the next insn. */
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if (errmsg)
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break;
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@ -345,6 +420,7 @@ assemble_vu_insn (str, lower_p, buf)
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continue;
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c = *t;
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*t = '\0';
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errmsg = NULL;
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suf_value = (*operand->parse) (&s, &errmsg);
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*t = c;
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if (errmsg)
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@ -357,10 +433,10 @@ assemble_vu_insn (str, lower_p, buf)
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}
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/* Insert the suffix's value into the insn. */
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if (operand->insert)
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insn = (*operand->insert) (insn, operand,
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mods, suf_value, NULL);
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(*operand->insert) (insn_buf, operand,
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mods, suf_value, NULL);
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else
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insn |= suf_value << operand->shift;
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*insn_buf |= suf_value << operand->shift;
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str = t;
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++syn;
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@ -397,6 +473,7 @@ assemble_vu_insn (str, lower_p, buf)
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/* Parse the operand. */
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if (operand->parse)
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{
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errmsg = NULL;
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value = (*operand->parse) (&str, &errmsg);
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if (errmsg)
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break;
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@ -419,11 +496,11 @@ assemble_vu_insn (str, lower_p, buf)
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else
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{
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/* We need to generate a fixup for this expression. */
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if (fc >= MAX_FIXUPS)
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if (fixup_count >= MAX_FIXUPS)
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as_fatal ("too many fixups");
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fixups[fc].exp = exp;
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fixups[fc].opindex = index;
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++fc;
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fixups[fixup_count].exp = exp;
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fixups[fixup_count].opindex = index;
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++fixup_count;
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value = 0;
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}
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}
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@ -432,13 +509,13 @@ assemble_vu_insn (str, lower_p, buf)
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if (operand->insert)
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{
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const char *errmsg = NULL;
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insn = (*operand->insert) (insn, operand, mods,
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value, &errmsg);
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(*operand->insert) (insn_buf, operand, mods,
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value, &errmsg);
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if (errmsg != (const char *) NULL)
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break;
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}
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else
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insn |= (value & ((1 << operand->bits) - 1)) << operand->shift;
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*insn_buf |= (value & ((1 << operand->bits) - 1)) << operand->shift;
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++syn;
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++num_operands;
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@ -461,40 +538,13 @@ assemble_vu_insn (str, lower_p, buf)
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if (*str != '\0'
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#ifndef VERTICAL_BAR_SEPARATOR
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&& lower_p
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&& cpu != CPU_VUUP
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#endif
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)
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as_bad ("junk at end of line: `%s'", str);
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/* Write out the instruction.
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Reminder: it is important to fetch enough space in one call to
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`frag_more'. We use (f - frag_now->fr_literal) to compute where
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we are and we don't want frag_now to change between calls. */
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md_number_to_chars (buf, insn, 4);
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/* Create any fixups. */
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for (i = 0; i < fc; ++i)
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{
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int op_type, reloc_type;
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const struct txvu_operand *operand;
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/* Create a fixup for this operand.
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At this point we do not use a bfd_reloc_code_real_type for
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operands residing in the insn, but instead just use the
|
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operand index. This lets us easily handle fixups for any
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operand type, although that is admittedly not a very exciting
|
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feature. We pick a BFD reloc type in md_apply_fix. */
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op_type = fixups[i].opindex;
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reloc_type = op_type + (int) BFD_RELOC_UNUSED;
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operand = &txvu_operands[op_type];
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fix_new_exp (frag_now, buf - frag_now->fr_literal, 4,
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&fixups[i].exp,
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(operand->flags & TXVU_OPERAND_RELATIVE_BRANCH) != 0,
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(bfd_reloc_code_real_type) reloc_type);
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}
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/* All done. */
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/* It's now up to the caller to emit the instruction and any
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relocations. */
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return str;
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}
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@ -844,7 +894,7 @@ txvu_insert_operand (insn, operand, mods, val, file, line)
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if (operand->insert)
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{
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const char *errmsg = NULL;
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insn = (*operand->insert) (insn, operand, mods, (long) val, &errmsg);
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(*operand->insert) (&insn, operand, mods, (long) val, &errmsg);
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if (errmsg != (const char *) NULL)
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as_warn (errmsg);
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}
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@ -856,12 +906,14 @@ txvu_insert_operand (insn, operand, mods, val, file, line)
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}
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static void
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s_dmadata (int ignore)
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s_dmadata (ignore)
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int ignore;
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{
|
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}
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static void
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s_dmapackpke (int ignore)
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s_dmapackpke (ignore)
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int ignore;
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{
|
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/* Syntax: .dmapackpke 0|1 */
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if (*input_line_pointer == '0')
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@ -876,34 +928,40 @@ s_dmapackpke (int ignore)
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}
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static void
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s_enddirect (int ignore)
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s_enddirect (ignore)
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int ignore;
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{
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}
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static void
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s_enddmadata (int ignore)
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s_enddmadata (ignore)
|
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int ignore;
|
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{
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}
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static void
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s_endgpuif (int ignore)
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s_endgpuif (ignore)
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int ignore;
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{
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}
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static void
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s_endmpg (int ignore)
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s_endmpg (ignore)
|
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int ignore;
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{
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vu_mode_p = 0;
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}
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static void
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s_endunpack (int ignore)
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s_endunpack (ignore)
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int ignore;
|
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{
|
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vu_mode_p = 0;
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}
|
||||
|
||||
static void
|
||||
s_vu (int enable_p)
|
||||
s_vu (enable_p)
|
||||
int enable_p;
|
||||
{
|
||||
vu_mode_p = enable_p;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in a new issue