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Allow more than just read, write and exec memory spaces in the core

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module.
This commit is contained in:
Andrew Cagney 1998-03-11 12:18:39 +00:00
parent 10572b6a43
commit eefc25e592
6 changed files with 41 additions and 31 deletions
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9
sim/common/sim-break.c
View file

@ -52,7 +52,8 @@ static SIM_RC resume_handler PARAMS ((SIM_DESC sd));
static SIM_RC suspend_handler PARAMS ((SIM_DESC sd));
/* Do the actual work of inserting a breakpoint into the instruction stream. */
/* Do the actual work of inserting a breakpoint into the instruction
stream. */
static void
insert_breakpoint (sd, bp)
@ -62,9 +63,9 @@ insert_breakpoint (sd, bp)
if (bp->flags & (SIM_BREAK_INSERTED | SIM_BREAK_DISABLED))
return;
sim_core_read_buffer (sd, NULL, sim_core_write_map, bp->loc_contents,
sim_core_read_buffer (sd, NULL, exec_map, bp->loc_contents,
bp->addr, SIM_BREAKPOINT_SIZE);
sim_core_write_buffer (sd, NULL, sim_core_write_map, sim_breakpoint,
sim_core_write_buffer (sd, NULL, exec_map, sim_breakpoint,
bp->addr, SIM_BREAKPOINT_SIZE);
bp->flags |= SIM_BREAK_INSERTED;
}
@ -79,7 +80,7 @@ remove_breakpoint (sd, bp)
if (!(bp->flags & SIM_BREAK_INSERTED))
return;
sim_core_write_buffer (sd, NULL, sim_core_write_map, bp->loc_contents,
sim_core_write_buffer (sd, NULL, exec_map, bp->loc_contents,
bp->addr, SIM_BREAKPOINT_SIZE);
bp->flags &= SIM_BREAK_INSERTED;
}

4
sim/mips/sky-pke.h
View file

@ -408,7 +408,7 @@ struct pke_device
do { \
sim_cpu* cpu = STATE_CPU(CURRENT_STATE, 0); \
unsigned_##size value = \
sim_core_read_aligned_##size(cpu, CIA_GET(cpu), sim_core_read_map, \
sim_core_read_aligned_##size(cpu, CIA_GET(cpu), read_map, \
(SIM_ADDR)(addr)); \
memcpy((unsigned_##size*) (data), (void*) & value, size); \
} while(0)
@ -417,7 +417,7 @@ struct pke_device
do { sim_cpu* cpu = STATE_CPU(CURRENT_STATE, 0); \
unsigned_##size value; \
memcpy((void*) & value, (unsigned_##size*)(data), size); \
sim_core_write_aligned_##size(cpu, CIA_GET(cpu), sim_core_write_map, \
sim_core_write_aligned_##size(cpu, CIA_GET(cpu), write_map, \
(SIM_ADDR)(addr), value); \
if((me)->fifo_trace_file != NULL) \
{ \

5
sim/tic80/ChangeLog
View file

@ -1,3 +1,8 @@
Wed Mar 11 14:12:56 1998 Andrew Cagney <cagney@b1.cygnus.com>
* alu.h (IMEM32_IMMED, IMEM32, STORE, MEM): Replace sim_core_*_map
with read_map, write_map, exec_map resp.
Thu Feb 26 19:08:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
* sim-calls.c (sim_info): Delete.

8
sim/tic80/alu.h
View file

@ -39,20 +39,20 @@ with this program; if not, write to the Free Software Foundation, Inc.,
/* Bring data in from the cold */
#define IMEM32(CIA) \
(sim_core_read_aligned_4(STATE_CPU (sd, 0), CIA, sim_core_execute_map, (CIA).ip))
(sim_core_read_aligned_4(STATE_CPU (sd, 0), CIA, exec_map, (CIA).ip))
#define IMEM32_IMMED(CIA, N) \
(sim_core_read_aligned_4 (STATE_CPU (sd, 0), CIA, sim_core_execute_map, (CIA).ip + 4 * (N)))
(sim_core_read_aligned_4 (STATE_CPU (sd, 0), CIA, exec_map, (CIA).ip + 4 * (N)))
#define MEM(SIGN, EA, NR_BYTES) \
((SIGN##_##NR_BYTES) sim_core_read_unaligned_##NR_BYTES (STATE_CPU (sd, 0), cia, \
sim_core_read_map, \
read_map, \
(EA)))
#define STORE(EA, NR_BYTES, VAL) \
do { \
sim_core_write_unaligned_##NR_BYTES (STATE_CPU (sd, 0), cia, \
sim_core_write_map, \
write_map, \
(EA), (VAL)); \
} while (0)

5
sim/txvu/ChangeLog
View file

@ -1,3 +1,8 @@
Wed Mar 11 14:14:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
* interp.c (sim_write, sim_read, load_memory, store_memory):
Replace sim_core_*_map with read_map, write_map, exec_map resp.
Tue Jan 27 18:24:01 1998 Ian Carmichael <iancarm@cygnus.com>
* Very, very early support for vu1 based on sce code.

41
sim/txvu/interp.c
View file

@ -510,7 +510,7 @@ sim_write (sd,addr,buffer,size)
int cca;
if (!address_translation (sd, NULL_CIA, vaddr, isDATA, isSTORE, &paddr, &cca, isRAW))
break;
if (sim_core_write_buffer (sd, NULL, sim_core_read_map, buffer + index, paddr, 1) != 1)
if (sim_core_write_buffer (sd, NULL, read_map, buffer + index, paddr, 1) != 1)
break;
}
@ -538,7 +538,7 @@ sim_read (sd,addr,buffer,size)
int cca;
if (!address_translation (sd, NULL_CIA, vaddr, isDATA, isLOAD, &paddr, &cca, isRAW))
break;
if (sim_core_read_buffer (sd, NULL, sim_core_read_map, buffer + index, paddr, 1) != 1)
if (sim_core_read_buffer (sd, NULL, read_map, buffer + index, paddr, 1) != 1)
break;
}
@ -1352,39 +1352,38 @@ load_memory(sd,cia,memvalp,memval1p,CCA,AccessLength,pAddr,vAddr,IorD)
{
case AccessLength_QUADWORD :
{
unsigned_16 val = sim_core_read_aligned_16 (STATE_CPU (sd, 0), NULL_CIA,
sim_core_read_map, pAddr);
unsigned_16 val = sim_core_read_aligned_16 (STATE_CPU (sd, 0), NULL_CIA, read_map, pAddr);
value1 = VH8_16 (val);
value = VL8_16 (val);
break;
}
case AccessLength_DOUBLEWORD :
value = sim_core_read_aligned_8 (STATE_CPU (sd, 0), NULL_CIA,
sim_core_read_map, pAddr);
read_map, pAddr);
break;
case AccessLength_SEPTIBYTE :
value = sim_core_read_misaligned_7 (STATE_CPU (sd, 0), NULL_CIA,
sim_core_read_map, pAddr);
read_map, pAddr);
case AccessLength_SEXTIBYTE :
value = sim_core_read_misaligned_6 (STATE_CPU (sd, 0), NULL_CIA,
sim_core_read_map, pAddr);
read_map, pAddr);
case AccessLength_QUINTIBYTE :
value = sim_core_read_misaligned_5 (STATE_CPU (sd, 0), NULL_CIA,
sim_core_read_map, pAddr);
read_map, pAddr);
case AccessLength_WORD :
value = sim_core_read_aligned_4 (STATE_CPU (sd, 0), NULL_CIA,
sim_core_read_map, pAddr);
read_map, pAddr);
break;
case AccessLength_TRIPLEBYTE :
value = sim_core_read_misaligned_3 (STATE_CPU (sd, 0), NULL_CIA,
sim_core_read_map, pAddr);
read_map, pAddr);
case AccessLength_HALFWORD :
value = sim_core_read_aligned_2 (STATE_CPU (sd, 0), NULL_CIA,
sim_core_read_map, pAddr);
read_map, pAddr);
break;
case AccessLength_BYTE :
value = sim_core_read_aligned_1 (STATE_CPU (sd, 0), NULL_CIA,
sim_core_read_map, pAddr);
read_map, pAddr);
break;
default:
abort ();
@ -1485,40 +1484,40 @@ store_memory(sd,cia,CCA,AccessLength,MemElem,MemElem1,pAddr,vAddr)
{
unsigned_16 val = U16_8 (MemElem1, MemElem);
sim_core_write_aligned_16 (STATE_CPU (sd, 0), NULL_CIA,
sim_core_write_map, pAddr, val);
write_map, pAddr, val);
break;
}
case AccessLength_DOUBLEWORD :
sim_core_write_aligned_8 (STATE_CPU (sd, 0), NULL_CIA,
sim_core_write_map, pAddr, MemElem);
write_map, pAddr, MemElem);
break;
case AccessLength_SEPTIBYTE :
sim_core_write_misaligned_7 (STATE_CPU (sd, 0), NULL_CIA,
sim_core_write_map, pAddr, MemElem);
write_map, pAddr, MemElem);
break;
case AccessLength_SEXTIBYTE :
sim_core_write_misaligned_6 (STATE_CPU (sd, 0), NULL_CIA,
sim_core_write_map, pAddr, MemElem);
write_map, pAddr, MemElem);
break;
case AccessLength_QUINTIBYTE :
sim_core_write_misaligned_5 (STATE_CPU (sd, 0), NULL_CIA,
sim_core_write_map, pAddr, MemElem);
write_map, pAddr, MemElem);
break;
case AccessLength_WORD :
sim_core_write_aligned_4 (STATE_CPU (sd, 0), NULL_CIA,
sim_core_write_map, pAddr, MemElem);
write_map, pAddr, MemElem);
break;
case AccessLength_TRIPLEBYTE :
sim_core_write_misaligned_3 (STATE_CPU (sd, 0), NULL_CIA,
sim_core_write_map, pAddr, MemElem);
write_map, pAddr, MemElem);
break;
case AccessLength_HALFWORD :
sim_core_write_aligned_2 (STATE_CPU (sd, 0), NULL_CIA,
sim_core_write_map, pAddr, MemElem);
write_map, pAddr, MemElem);
break;
case AccessLength_BYTE :
sim_core_write_aligned_1 (STATE_CPU (sd, 0), NULL_CIA,
sim_core_write_map, pAddr, MemElem);
write_map, pAddr, MemElem);
break;
default:
abort ();