darkkirb/old-cross-binutils
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

Add support for moxie's mul.x and umul.x instructions

Browse source
This commit is contained in:
Anthony Green 2014-12-24 08:37:16 -05:00
parent 0be40ae409
commit ed4fd7b7f3
2 changed files with 28 additions and 2 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
sim/moxie/ChangeLog
View file

@ -1,3 +1,7 @@
2014-12-24 Anthony Green <green@moxielogic.com>
* interp.c (sim_resume): Add mul.x and umul.x instructions.
2014-12-12 Anthony Green <green@moxielogic.com>
* interp.c (sim_resume): Add zex instructions.

26
sim/moxie/interp.c
View file

@ -622,8 +622,30 @@ sim_resume (sd, step, siggnal)
cpu.asregs.regs[a] = (int) bv & 0xffff;
}
break;
case 0x14: /* bad */
case 0x15: /* bad */
case 0x14: /* mul.x */
{
int a = (inst >> 4) & 0xf;
int b = inst & 0xf;
unsigned av = cpu.asregs.regs[a];
unsigned bv = cpu.asregs.regs[b];
TRACE("mul.x");
signed long long r =
(signed long long) av * (signed long long) bv;
cpu.asregs.regs[a] = r >> 32;
}
break;
case 0x15: /* umul.x */
{
int a = (inst >> 4) & 0xf;
int b = inst & 0xf;
unsigned av = cpu.asregs.regs[a];
unsigned bv = cpu.asregs.regs[b];
TRACE("umul.x");
unsigned long long r =
(unsigned long long) av * (unsigned long long) bv;
cpu.asregs.regs[a] = r >> 32;
}
break;
case 0x16: /* bad */
case 0x17: /* bad */
case 0x18: /* bad */