opcodes/ChangeLog
* ppc-opc.c (powerpc_opcodes): Changed opcode for vabsdub, vabsduh, vabsduw, mviwsplt. gas/testsuite/ChangeLog * gas/ppc/e6500.d: Changed opcode for vabsdub, vabsduh, vabsduw, mviwsplt.
This commit is contained in:
Alan Modra
parent
f1d4a2242f
commit
e67ed0e885
4 changed files with 43 additions and 33 deletions
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@ -1,3 +1,8 @@
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2012-08-20 Edmar Wienskoski <edmar@freescale.com>
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* gas/ppc/e6500.d: Changed opcode for vabsdub, vabsduh, vabsduw,
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mviwsplt.
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2012-08-17 Nagajyothi Eggone <nagajyothi.eggone@amd.com>
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* gas/i386/i386.exp: Run btver1 and btver2 test cases.
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@ -36,15 +41,15 @@
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* gas/mmix/err-fb-2.s: New test.
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2012-08-13 Ian Bolton <ian.bolton@arm.com>
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Laurent Desnogues <laurent.desnogues@arm.com>
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Jim MacArthur <jim.macarthur@arm.com>
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Marcus Shawcroft <marcus.shawcroft@arm.com>
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Nigel Stephens <nigel.stephens@arm.com>
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Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
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Richard Earnshaw <rearnsha@arm.com>
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Sofiane Naci <sofiane.naci@arm.com>
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Tejas Belagod <tejas.belagod@arm.com>
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Yufeng Zhang <yufeng.zhang@arm.com>
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Laurent Desnogues <laurent.desnogues@arm.com>
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Jim MacArthur <jim.macarthur@arm.com>
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Marcus Shawcroft <marcus.shawcroft@arm.com>
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Nigel Stephens <nigel.stephens@arm.com>
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Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
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Richard Earnshaw <rearnsha@arm.com>
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Sofiane Naci <sofiane.naci@arm.com>
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Tejas Belagod <tejas.belagod@arm.com>
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Yufeng Zhang <yufeng.zhang@arm.com>
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* gas/aarch64: New directory.
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* gas/aarch64/aarch64.exp: New file.
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@ -7,11 +7,11 @@
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Disassembly of section \.text:
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0+00 <start>:
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0: 10 01 10 c0 vabsdub v0,v1,v2
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4: 10 01 11 00 vabsduh v0,v1,v2
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8: 10 01 11 40 vabsduw v0,v1,v2
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0: 10 01 14 03 vabsdub v0,v1,v2
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4: 10 01 14 43 vabsduh v0,v1,v2
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8: 10 01 14 83 vabsduw v0,v1,v2
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c: 7c 01 10 dc mvidsplt v0,r1,r2
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10: 7c 01 11 1c mviwsplt v0,r1,r2
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10: 7c 01 10 5c mviwsplt v0,r1,r2
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14: 7c 00 12 0a lvexbx v0,0,r2
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18: 7c 01 12 0a lvexbx v0,r1,r2
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1c: 7c 00 12 4a lvexhx v0,0,r2
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@ -1,3 +1,8 @@
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2012-08-20 Edmar Wienskoski <edmar@freescale.com>
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* ppc-opc.c (powerpc_opcodes): Changed opcode for vabsdub,
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vabsduh, vabsduw, mviwsplt.
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2012-08-17 Nagajyothi Eggone <nagajyothi.eggone@amd.com>
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* i386-gen.c (cpu_flag_init): Add CPU_BTVER1_FLAGS and
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@ -53,15 +58,15 @@
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the instruction word.
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2012-08-13 Ian Bolton <ian.bolton@arm.com>
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Laurent Desnogues <laurent.desnogues@arm.com>
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Jim MacArthur <jim.macarthur@arm.com>
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Marcus Shawcroft <marcus.shawcroft@arm.com>
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Nigel Stephens <nigel.stephens@arm.com>
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Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
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Richard Earnshaw <rearnsha@arm.com>
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Sofiane Naci <sofiane.naci@arm.com>
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Tejas Belagod <tejas.belagod@arm.com>
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Yufeng Zhang <yufeng.zhang@arm.com>
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Laurent Desnogues <laurent.desnogues@arm.com>
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Jim MacArthur <jim.macarthur@arm.com>
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Marcus Shawcroft <marcus.shawcroft@arm.com>
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Nigel Stephens <nigel.stephens@arm.com>
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Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
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Richard Earnshaw <rearnsha@arm.com>
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Sofiane Naci <sofiane.naci@arm.com>
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Tejas Belagod <tejas.belagod@arm.com>
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Yufeng Zhang <yufeng.zhang@arm.com>
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* Makefile.am: Add AArch64.
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* Makefile.in: Regenerate.
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@ -160,8 +165,8 @@
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* po/POTFILES.in: Regenerate.
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2012-07-31 Chao-Ying Fu <fu@mips.com>
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Catherine Moore <clm@codesourcery.com>
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Maciej W. Rozycki <macro@codesourcery.com>
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Catherine Moore <clm@codesourcery.com>
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Maciej W. Rozycki <macro@codesourcery.com>
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* micromips-opc.c (WR_a, RD_a, MOD_a): New macros.
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(DSP_VOLA): Likewise.
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@ -244,9 +249,9 @@
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2012-07-05 Sean Keys <skeys@ipdatasys.com>
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* xgate-dis.c: Removed an IF statement that will
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always be false due to overlapping operand masks.
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* xgate-opc.c: Corrected 'com' opcode entry and
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fixed spacing.
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always be false due to overlapping operand masks.
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* xgate-opc.c: Corrected 'com' opcode entry and
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fixed spacing.
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2012-07-02 Roland McGrath <mcgrathr@google.com>
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@ -2858,14 +2858,12 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{"machhwsu", XO (4, 76,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
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{"machhwsu.", XO (4, 76,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
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{"ps_cmpo1", X (4, 96), X_MASK|(3<<21), PPCPS, PPCNONE, {BF, FRA, FRB}},
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{"vabsdub", VX (4, 192), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
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{"vcmpeqfp", VXR(4, 198,0), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
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{"vpkuwus", VX (4, 206), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
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{"machhws", XO (4, 108,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
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{"machhws.", XO (4, 108,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
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{"nmachhws", XO (4, 110,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
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{"nmachhws.", XO (4, 110,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
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{"vabsduh", VX (4, 256), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
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{"vmaxsb", VX (4, 258), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
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{"vslb", VX (4, 260), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
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{"vmulosb", VX (4, 264), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
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@ -2878,7 +2876,6 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{"mulchwu.", XRC(4, 136,1), X_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
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{"macchwu", XO (4, 140,0,0),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
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{"macchwu.", XO (4, 140,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
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{"vabsduw", VX (4, 320), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
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{"vmaxsh", VX (4, 322), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
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{"vslh", VX (4, 324), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
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{"vmulosh", VX (4, 328), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
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@ -3142,6 +3139,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{"nmaclhws.", XO (4, 494,0,1),XO_MASK, MULHW|PPCVLE, PPCNONE, {RT, RA, RB}},
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{"vsububm", VX (4,1024), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
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{"vavgub", VX (4,1026), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
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{"vabsdub", VX (4,1027), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
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{"evmhessf", VX (4,1027), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
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{"vand", VX (4,1028), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
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{"vcmpequb.", VXR(4, 6,1), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
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@ -3170,6 +3168,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{"evmhosmfa", VX (4,1071), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
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{"vsubuhm", VX (4,1088), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
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{"vavguh", VX (4,1090), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
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{"vabsduh", VX (4,1091), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
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{"vandc", VX (4,1092), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
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{"vcmpequh.", VXR(4, 70,1), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
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{"udi1fcm.", APU(4, 547,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
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@ -3202,6 +3201,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{"evmwsmfa", VX (4,1147), VX_MASK, PPCSPE|PPCVLE, PPCNONE, {RS, RA, RB}},
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{"vsubuwm", VX (4,1152), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
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{"vavguw", VX (4,1154), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
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{"vabsduw", VX (4,1155), VX_MASK, PPCVEC2, PPCNONE, {VD, VA, VB}},
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{"vor", VX (4,1156), VX_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
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{"vcmpequw.", VXR(4, 134,1), VXR_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB}},
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{"udi2fcm.", APU(4, 579,0), APU_MASK, PPC405|PPC440, PPC476, {URT, URA, URB}},
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@ -4286,6 +4286,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{"lvehx", X(31,39), X_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, RA0, RB}},
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{"lhfcmx", APU(31,39,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
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{"mviwsplt", X(31,46), X_MASK, PPCVEC2, PPCNONE, {VD, RA, RB}},
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{"iselgt", X(31,47), X_MASK, PPCISEL, PPCNONE, {RT, RA0, RB}},
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{"lvewx", X(31,71), X_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, RA0, RB}},
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@ -4410,8 +4412,6 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{"adde.", XO(31,138,0,1), XO_MASK, PPCCOM|PPCVLE, PPCNONE, {RT, RA, RB}},
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{"ae.", XO(31,138,0,1), XO_MASK, PWRCOM, PPCNONE, {RT, RA, RB}},
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{"mviwsplt", X(31,142), X_MASK, PPCVEC2, PPCNONE, {VD, RA, RB}},
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{"dcbtstlse", X(31,142), X_MASK, PPCCHLK, E500MC, {CT, RA0, RB}},
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{"mtcr", XFXM(31,144,0xff,0), XRARB_MASK, COM, PPCNONE, {RS}},
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