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* armemu.c (ARMul_Emulate): Compute writeback value before

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loading, since the offset register may be the destination
register.
This commit is contained in:
Alexandre Oliva 2000-07-04 05:30:43 +00:00
parent b0eae074ca
commit e62263b8ec
2 changed files with 20 additions and 8 deletions
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4
sim/arm/ChangeLog
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@ -1,5 +1,9 @@
2000-07-04 Alexandre Oliva <aoliva@redhat.com>
* armemu.c (ARMul_Emulate): Compute writeback value before
loading, since the offset register may be the destination
register.
* armdefs.h (SYSTEMBANK): Define as USERBANK.
* armsupp.c (ARMul_SwitchMode): Remove SYSTEMBANK cases.

24
sim/arm/armemu.c
View file

@ -1998,8 +1998,9 @@ ARMul_Emulate26 (register ARMul_State * state)
UNDEF_LSRPCBaseWb;
UNDEF_LSRPCOffWb;
lhs = LHS;
temp = lhs - LSRegRHS;
if (LoadWord (state, instr, lhs))
LSBase = lhs - LSRegRHS;
LSBase = temp;
break;
case 0x62: /* Store Word, WriteBack, Post Dec, Reg */
@ -2030,9 +2031,10 @@ ARMul_Emulate26 (register ARMul_State * state)
UNDEF_LSRPCBaseWb;
UNDEF_LSRPCOffWb;
lhs = LHS;
temp = lhs - LSRegRHS;
state->NtransSig = LOW;
if (LoadWord (state, instr, lhs))
LSBase = lhs - LSRegRHS;
LSBase = temp;
state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
break;
@ -2062,8 +2064,9 @@ ARMul_Emulate26 (register ARMul_State * state)
UNDEF_LSRPCBaseWb;
UNDEF_LSRPCOffWb;
lhs = LHS;
temp = lhs - LSRegRHS;
if (LoadByte (state, instr, lhs, LUNSIGNED))
LSBase = lhs - LSRegRHS;
LSBase = temp;
break;
case 0x66: /* Store Byte, WriteBack, Post Dec, Reg */
@ -2094,9 +2097,10 @@ ARMul_Emulate26 (register ARMul_State * state)
UNDEF_LSRPCBaseWb;
UNDEF_LSRPCOffWb;
lhs = LHS;
temp = lhs - LSRegRHS;
state->NtransSig = LOW;
if (LoadByte (state, instr, lhs, LUNSIGNED))
LSBase = lhs - LSRegRHS;
LSBase = temp;
state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
break;
@ -2126,8 +2130,9 @@ ARMul_Emulate26 (register ARMul_State * state)
UNDEF_LSRPCBaseWb;
UNDEF_LSRPCOffWb;
lhs = LHS;
temp = lhs + LSRegRHS;
if (LoadWord (state, instr, lhs))
LSBase = lhs + LSRegRHS;
LSBase = temp;
break;
case 0x6a: /* Store Word, WriteBack, Post Inc, Reg */
@ -2158,9 +2163,10 @@ ARMul_Emulate26 (register ARMul_State * state)
UNDEF_LSRPCBaseWb;
UNDEF_LSRPCOffWb;
lhs = LHS;
temp = lhs + LSRegRHS;
state->NtransSig = LOW;
if (LoadWord (state, instr, lhs))
LSBase = lhs + LSRegRHS;
LSBase = temp;
state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
break;
@ -2190,8 +2196,9 @@ ARMul_Emulate26 (register ARMul_State * state)
UNDEF_LSRPCBaseWb;
UNDEF_LSRPCOffWb;
lhs = LHS;
temp = lhs + LSRegRHS;
if (LoadByte (state, instr, lhs, LUNSIGNED))
LSBase = lhs + LSRegRHS;
LSBase = temp;
break;
case 0x6e: /* Store Byte, WriteBack, Post Inc, Reg */
@ -2222,9 +2229,10 @@ ARMul_Emulate26 (register ARMul_State * state)
UNDEF_LSRPCBaseWb;
UNDEF_LSRPCOffWb;
lhs = LHS;
temp = lhs + LSRegRHS;
state->NtransSig = LOW;
if (LoadByte (state, instr, lhs, LUNSIGNED))
LSBase = lhs + LSRegRHS;
LSBase = temp;
state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
break;