gas/testsuite/
* gas/i386/x86-64-stack.s: Add cases for push segment register. * gas/i386/x86-64-stack.d: Updated. * gas/i386/x86-64-stack-suffix.d: Updated. * gas/i386/x86-64-stack-intel.d: Updated. * gas/i386/ilp32/x86-64-stack.d: Updated. * gas/i386/ilp32/x86-64-stack-suffix.d: Updated. * gas/i386/ilp32/x86-64-stack-intel.d: Updated. opcodes/ * i386-dis.c (print_insn): Print spaces between multiple excess prefixes. Return actual number of excess prefixes consumed, not always one. * i386-dis.c (OP_REG): Ignore REX_B for segment register cases.
This commit is contained in:
parent
99262e37ef
commit
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10 changed files with 93 additions and 6 deletions
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@ -41,6 +41,14 @@
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2012-08-06 Roland McGrath <mcgrathr@google.com>
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* gas/i386/x86-64-stack.s: Add cases for push segment register.
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* gas/i386/x86-64-stack.d: Updated.
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* gas/i386/x86-64-stack-suffix.d: Updated.
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* gas/i386/x86-64-stack-intel.d: Updated.
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* gas/i386/ilp32/x86-64-stack.d: Updated.
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* gas/i386/ilp32/x86-64-stack-suffix.d: Updated.
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* gas/i386/ilp32/x86-64-stack-intel.d: Updated.
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* gas/i386/x86-64-stack.s: Add cases for push immediate.
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* gas/testsuite/gas/i386/ilp32/x86-64-stack-intel.d: Updated.
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* gas/testsuite/gas/i386/ilp32/x86-64-stack-suffix.d: Updated.
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@ -56,5 +56,15 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+: 03 04 48 add eax,DWORD PTR \[rax\+rcx\*2\]
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[ ]*[a-f0-9]+: 68 01 02 03 04 push 0x4030201
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[ ]*[a-f0-9]+: 66 48 68 01 02 03 04 data32 rex.W push 0x4030201
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[ ]*[a-f0-9]+: 0f a8 push gs
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[ ]*[a-f0-9]+: 66 0f a8 pushw gs
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[ ]*[a-f0-9]+: 48 0f a8 rex.W push gs
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[ ]*[a-f0-9]+: 66 48 0f a8 data32 rex.W push gs
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[ ]*[a-f0-9]+: 41 0f a8 rex.B push gs
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[ ]*[a-f0-9]+: 66 41 0f a8 rex.B pushw gs
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[ ]*[a-f0-9]+: 48 rex.W
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[ ]*[a-f0-9]+: 41 0f a8 rex.B push gs
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[ ]*[a-f0-9]+: 66 48 data16 rex.W
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[ ]*[a-f0-9]+: 41 0f a8 rex.B push gs
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[ ]*[a-f0-9]+: 90 nop
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#pass
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@ -56,5 +56,15 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+: 03 04 48 addl \(%rax,%rcx,2\),%eax
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[ ]*[a-f0-9]+: 68 01 02 03 04 pushq \$0x4030201
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[ ]*[a-f0-9]+: 66 48 68 01 02 03 04 data32 rex.W pushq \$0x4030201
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[ ]*[a-f0-9]+: 0f a8 pushq %gs
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[ ]*[a-f0-9]+: 66 0f a8 pushw %gs
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[ ]*[a-f0-9]+: 48 0f a8 rex.W pushq %gs
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[ ]*[a-f0-9]+: 66 48 0f a8 data32 rex.W pushq %gs
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[ ]*[a-f0-9]+: 41 0f a8 rex.B pushq %gs
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[ ]*[a-f0-9]+: 66 41 0f a8 rex.B pushw %gs
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[ ]*[a-f0-9]+: 48 rex.W
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[ ]*[a-f0-9]+: 41 0f a8 rex.B pushq %gs
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[ ]*[a-f0-9]+: 66 48 data16 rex.W
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[ ]*[a-f0-9]+: 41 0f a8 rex.B pushq %gs
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[ ]*[a-f0-9]+: 90 nop
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#pass
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@ -56,5 +56,15 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+: 03 04 48 add \(%rax,%rcx,2\),%eax
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[ ]*[a-f0-9]+: 68 01 02 03 04 pushq \$0x4030201
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[ ]*[a-f0-9]+: 66 48 68 01 02 03 04 data32 rex.W pushq \$0x4030201
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[ ]*[a-f0-9]+: 0f a8 pushq %gs
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[ ]*[a-f0-9]+: 66 0f a8 pushw %gs
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[ ]*[a-f0-9]+: 48 0f a8 rex.W pushq %gs
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[ ]*[a-f0-9]+: 66 48 0f a8 data32 rex.W pushq %gs
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[ ]*[a-f0-9]+: 41 0f a8 rex.B pushq %gs
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[ ]*[a-f0-9]+: 66 41 0f a8 rex.B pushw %gs
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[ ]*[a-f0-9]+: 48 rex.W
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[ ]*[a-f0-9]+: 41 0f a8 rex.B pushq %gs
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[ ]*[a-f0-9]+: 66 48 data16 rex.W
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[ ]*[a-f0-9]+: 41 0f a8 rex.B pushq %gs
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[ ]*[a-f0-9]+: 90 nop
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#pass
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@ -56,5 +56,15 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+: 03 04 48 add eax,DWORD PTR \[rax\+rcx\*2\]
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[ ]*[a-f0-9]+: 68 01 02 03 04 push 0x4030201
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[ ]*[a-f0-9]+: 66 48 68 01 02 03 04 data32 rex.W push 0x4030201
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[ ]*[a-f0-9]+: 0f a8 push gs
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[ ]*[a-f0-9]+: 66 0f a8 pushw gs
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[ ]*[a-f0-9]+: 48 0f a8 rex.W push gs
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[ ]*[a-f0-9]+: 66 48 0f a8 data32 rex.W push gs
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[ ]*[a-f0-9]+: 41 0f a8 rex.B push gs
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[ ]*[a-f0-9]+: 66 41 0f a8 rex.B pushw gs
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[ ]*[a-f0-9]+: 48 rex.W
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[ ]*[a-f0-9]+: 41 0f a8 rex.B push gs
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[ ]*[a-f0-9]+: 66 48 data16 rex.W
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[ ]*[a-f0-9]+: 41 0f a8 rex.B push gs
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[ ]*[a-f0-9]+: 90 nop
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#pass
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@ -56,5 +56,15 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+: 03 04 48 addl \(%rax,%rcx,2\),%eax
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[ ]*[a-f0-9]+: 68 01 02 03 04 pushq \$0x4030201
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[ ]*[a-f0-9]+: 66 48 68 01 02 03 04 data32 rex.W pushq \$0x4030201
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[ ]*[a-f0-9]+: 0f a8 pushq %gs
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[ ]*[a-f0-9]+: 66 0f a8 pushw %gs
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[ ]*[a-f0-9]+: 48 0f a8 rex.W pushq %gs
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[ ]*[a-f0-9]+: 66 48 0f a8 data32 rex.W pushq %gs
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[ ]*[a-f0-9]+: 41 0f a8 rex.B pushq %gs
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[ ]*[a-f0-9]+: 66 41 0f a8 rex.B pushw %gs
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[ ]*[a-f0-9]+: 48 rex.W
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[ ]*[a-f0-9]+: 41 0f a8 rex.B pushq %gs
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[ ]*[a-f0-9]+: 66 48 data16 rex.W
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[ ]*[a-f0-9]+: 41 0f a8 rex.B pushq %gs
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[ ]*[a-f0-9]+: 90 nop
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#pass
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@ -55,5 +55,15 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+: 03 04 48 add \(%rax,%rcx,2\),%eax
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[ ]*[a-f0-9]+: 68 01 02 03 04 pushq \$0x4030201
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[ ]*[a-f0-9]+: 66 48 68 01 02 03 04 data32 rex.W pushq \$0x4030201
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[ ]*[a-f0-9]+: 0f a8 pushq %gs
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[ ]*[a-f0-9]+: 66 0f a8 pushw %gs
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[ ]*[a-f0-9]+: 48 0f a8 rex.W pushq %gs
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[ ]*[a-f0-9]+: 66 48 0f a8 data32 rex.W pushq %gs
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[ ]*[a-f0-9]+: 41 0f a8 rex.B pushq %gs
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[ ]*[a-f0-9]+: 66 41 0f a8 rex.B pushw %gs
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[ ]*[a-f0-9]+: 48 rex.W
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[ ]*[a-f0-9]+: 41 0f a8 rex.B pushq %gs
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[ ]*[a-f0-9]+: 66 48 data16 rex.W
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[ ]*[a-f0-9]+: 41 0f a8 rex.B pushq %gs
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[ ]*[a-f0-9]+: 90 nop
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#pass
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@ -29,6 +29,11 @@ _start:
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# push with a 4-byte immediate
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try 0x68, 0x01, 0x02, 0x03, 0x04
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# push a segment register
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try 0x0f, 0xa8
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# with extraneous rex.B
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try 0x41, 0x0f, 0xa8
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# This is just to synchronize the disassembly.
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# Any new cases must come before this line!
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nop
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@ -1,3 +1,11 @@
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2012-08-06 Roland McGrath <mcgrathr@google.com>
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* i386-dis.c (print_insn): Print spaces between multiple excess
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prefixes. Return actual number of excess prefixes consumed,
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not always one.
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* i386-dis.c (OP_REG): Ignore REX_B for segment register cases.
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2012-08-06 Roland McGrath <mcgrathr@google.com>
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Victor Khimenko <khim@google.com>
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H.J. Lu <hongjiu.lu@intel.com>
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@ -11450,9 +11450,10 @@ print_insn (bfd_vma pc, disassemble_info *info)
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for (i = 0;
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i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
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i++)
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(*info->fprintf_func) (info->stream, "%s",
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(*info->fprintf_func) (info->stream, "%s%s",
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i == 0 ? "" : " ",
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prefix_name (all_prefixes[i], sizeflag));
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return 1;
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return i;
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}
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insn_codep = codep;
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{
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const char *s;
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int add;
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switch (code)
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{
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case es_reg: case ss_reg: case cs_reg:
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case ds_reg: case fs_reg: case gs_reg:
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oappend (names_seg[code - es_reg]);
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return;
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}
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USED_REX (REX_B);
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if (rex & REX_B)
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add = 8;
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case sp_reg: case bp_reg: case si_reg: case di_reg:
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s = names16[code - ax_reg + add];
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break;
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case es_reg: case ss_reg: case cs_reg:
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case ds_reg: case fs_reg: case gs_reg:
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s = names_seg[code - es_reg + add];
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break;
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case al_reg: case ah_reg: case cl_reg: case ch_reg:
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case dl_reg: case dh_reg: case bl_reg: case bh_reg:
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USED_REX (0);
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