o Add core and event objects into simulator
base type o Add preliminary tracing support for same o trace_printf() takes both SD and CPU arguments o Add CIA to standard set of parameters for generated functions. o Pacify GCC
This commit is contained in:
Andrew Cagney
parent
2317a49939
commit
d9b7594738
7 changed files with 104 additions and 80 deletions
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@ -1,3 +1,22 @@
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Fri May 2 14:57:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
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* sim-calls.c: Include sim-utils.h and sim-options.h.
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* sim-main.h (sim_state): Drop sim_events and sim_core members,
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moved to simulator base type.
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* alu.h (IMEM, MEM, STORE): Update track changes in common
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directory.
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* insns: Drop cia argument from functions, igen now handles this.
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* interp.c (engine_init): Include string.h/strings.h to define
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memset et.al.
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* sim-main.h (sim_cia): Delcare, tracking common dir changes.
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* cpu.h (sim_cpu): Update instruction_address with sim_cia.
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Wed Apr 30 11:26:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
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* sim-main.h (signal.h): Include so that SIG* available to all
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@ -15,14 +15,20 @@
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/* Bring data in from the cold */
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#define IMEM(EA) sim_core_read_4(sd, sim_core_execute_map, (EA))
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#define IMEM(EA) \
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(sim_core_read_4(sd, sim_core_execute_map, (EA), \
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STATE_CPU (sd, 0), cia))
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#define MEM(SIGN, EA, NR_BYTES) \
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((SIGN##_##NR_BYTES) sim_core_read_##NR_BYTES (SD, sim_core_read_map, (EA) & ~(NR_BYTES - 1)))
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((SIGN##_##NR_BYTES) sim_core_read_##NR_BYTES (SD, sim_core_read_map, \
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(EA) & ~(NR_BYTES - 1), \
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STATE_CPU (sd, 0), cia))
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#define STORE(EA, NR_BYTES, VAL) \
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do { \
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sim_core_write_##NR_BYTES (SD, sim_core_write_map, (EA) & ~(NR_BYTES - 1), (VAL)); \
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sim_core_write_##NR_BYTES (SD, sim_core_write_map, \
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(EA) & ~(NR_BYTES - 1), (VAL), \
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STATE_CPU (sd, 0), cia); \
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} while (0)
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@ -20,12 +20,12 @@ with this program; if not, write to the Free Software Foundation, Inc.,
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typedef struct _sim_cpu {
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struct _sim_cpu {
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unsigned32 reg[32];
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unsigned64 acc[4];
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instruction_address cia;
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sim_cia cia;
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sim_cpu_base base;
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} sim_cpu;
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};
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#define GPR(N) ((CPU)->reg[N])
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#define ACC(N) ((CPU)->acc[N])
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110
sim/tic80/insns
110
sim/tic80/insns
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@ -75,7 +75,7 @@ void::function::do_and:signed32 *rDest, signed32 Source1, signed32 Source2
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// bbo.[a]
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instruction_address::function::do_bbo:instruction_address cia, instruction_address nia, int bitnum, unsigned32 source, int annul, unsigned32 offset
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instruction_address::function::do_bbo:instruction_address nia, int bitnum, unsigned32 source, int annul, unsigned32 offset
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if (MASKED32 (source, bitnum, bitnum))
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{
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if (annul)
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@ -84,16 +84,16 @@ instruction_address::function::do_bbo:instruction_address cia, instruction_addre
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}
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return nia;
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31.BITNUM,26.Source,21.0b100101,15.A,14.SignedOffset::::bbo i
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nia = do_bbo (_SD, cia, nia, BITNUM, rSource, A, vSignedOffset);
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nia = do_bbo (_SD, nia, BITNUM, rSource, A, vSignedOffset);
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31.BITNUM,26.Source,21.0b11100101,13.A,12.0,11./,4.IndOff::::bbo r
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nia = do_bbo (_SD, cia, nia, BITNUM, rSource, A, rIndOff);
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nia = do_bbo (_SD, nia, BITNUM, rSource, A, rIndOff);
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31.BITNUM,26.Source,21.0b11100101,13.A,12.1,11./::::bbo l
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long_immediate (LongSignedImmediate);
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nia = do_bbo (_SD, cia, nia, BITNUM, rSource, A, LongSignedImmediate);
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nia = do_bbo (_SD, nia, BITNUM, rSource, A, LongSignedImmediate);
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// bbz[.a]
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instruction_address::function::do_bbz:instruction_address cia, instruction_address nia, int bitnum, unsigned32 source, int annul, unsigned32 offset
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instruction_address::function::do_bbz:instruction_address nia, int bitnum, unsigned32 source, int annul, unsigned32 offset
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if (!MASKED32 (source, bitnum, bitnum))
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{
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if (annul)
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@ -102,16 +102,16 @@ instruction_address::function::do_bbz:instruction_address cia, instruction_addre
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}
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return nia;
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31.BITNUM,26.Source,21.0b100100,15.A,14.SignedOffset::::bbz i
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nia = do_bbz (_SD, cia, nia, BITNUM, rSource, A, vSignedOffset);
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nia = do_bbz (_SD, nia, BITNUM, rSource, A, vSignedOffset);
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31.BITNUM,26.Source,21.0b11100100,13.A,12.0,11./,4.IndOff::::bbz r
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nia = do_bbz (_SD, cia, nia, BITNUM, rSource, A, rIndOff);
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nia = do_bbz (_SD, nia, BITNUM, rSource, A, rIndOff);
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31.BITNUM,26.Source,21.0b11100100,13.A,12.1,11./::::bbz l
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long_immediate (LongSignedImmediate);
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nia = do_bbz (_SD, cia, nia, BITNUM, rSource, A, LongSignedImmediate);
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nia = do_bbz (_SD, nia, BITNUM, rSource, A, LongSignedImmediate);
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// bcnd[.a]
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instruction_address::function::do_bcnd:instruction_address cia, instruction_address nia, int Cond, unsigned32 source, int annul, unsigned32 offset
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instruction_address::function::do_bcnd:instruction_address nia, int Cond, unsigned32 source, int annul, unsigned32 offset
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int condition;
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int size = EXTRACTED32 (Cond, 31 - 27, 30 - 27);
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int code = EXTRACTED32 (Cond, 29 - 27, 27 - 27);
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@ -142,12 +142,12 @@ instruction_address::function::do_bcnd:instruction_address cia, instruction_addr
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}
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return nia;
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31.Code,26.Source,21.0b100110,15.A,14.SignedOffset::::bcnd i
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nia = do_bcnd (_SD, cia, nia, Code, rSource, A, vSignedOffset);
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nia = do_bcnd (_SD, nia, Code, rSource, A, vSignedOffset);
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31.Code,26.Source,21.0b11100110,13.A,12.0,11./,4.IndOff::::bcnd r
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nia = do_bcnd (_SD, cia, nia, Code, rSource, A, rIndOff);
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nia = do_bcnd (_SD, nia, Code, rSource, A, rIndOff);
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31.Code,26.Source,21.0b11100110,13.A,12.1,11./::::bcnd l
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long_immediate (LongSignedImmediate);
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nia = do_bcnd (_SD, cia, nia, Code, rSource, A, LongSignedImmediate);
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nia = do_bcnd (_SD, nia, Code, rSource, A, LongSignedImmediate);
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// br[.a] - see bbz[.a]
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@ -165,7 +165,7 @@ instruction_address::function::do_bcnd:instruction_address cia, instruction_addr
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// bsr[.a]
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instruction_address::function::do_bsr:instruction_address cia, instruction_address nia, signed32 *rLink, int annul, unsigned32 offset
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instruction_address::function::do_bsr:instruction_address nia, signed32 *rLink, int annul, unsigned32 offset
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if (annul)
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{
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*rLink = nia.ip;
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@ -176,12 +176,12 @@ instruction_address::function::do_bsr:instruction_address cia, instruction_addre
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nia.dp = cia.ip + 4 * offset;
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return nia;
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31.Link,26./,21.0b100000,15.A,14.SignedOffset::::bsr i
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nia = do_bsr (_SD, cia, nia, rLink, A, vSignedOffset);
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nia = do_bsr (_SD, nia, rLink, A, vSignedOffset);
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31.Link,26./,21.0b11100000,13.A,12.0,11./,4.IndOff::::bsr r
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nia = do_bsr (_SD, cia, nia, rLink, A, rIndOff);
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nia = do_bsr (_SD, nia, rLink, A, rIndOff);
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31.Link,26./,21.0b11100000,13.A,12.1,11./::::bsr l
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long_immediate (LongSignedImmediate);
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nia = do_bsr (_SD, cia, nia, rLink, A, LongSignedImmediate);
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nia = do_bsr (_SD, nia, rLink, A, LongSignedImmediate);
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// cmnd
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@ -236,33 +236,33 @@ void::function::do_cmp:unsigned32 *rDest, unsigned32 Source1, unsigned32 Source2
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// dld[{.b|.h|.d}]
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void::function::do_dld:instruction_address cia, int Dest, unsigned32 Base, unsigned32 *rBase, int m , int sz, int S, unsigned32 Offset
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do_ld (_SD, cia, Dest, Base, rBase, m, sz, S, Offset);
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void::function::do_dld:int Dest, unsigned32 Base, unsigned32 *rBase, int m , int sz, int S, unsigned32 Offset
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do_ld (_SD, Dest, Base, rBase, m, sz, S, Offset);
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31.Dest,26.Base,21.0b110100,15.m,14.sz,12.0,11.S,10.1,9./,4.IndOff::::dld r
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do_dld (_SD, cia, Dest, rBase, &GPR(Base), m, sz, S, rIndOff);
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do_dld (_SD, Dest, rBase, &GPR(Base), m, sz, S, rIndOff);
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31.Dest,26.Base,21.0b110100,15.m,14.sz,12.1,11.S,10.1,9./::::dld l
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long_immediate (LongSignedImmediateOffset);
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do_dld (_SD, cia, Dest, rBase, &GPR(Base), m, sz, S, LongSignedImmediateOffset);
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do_dld (_SD, Dest, rBase, &GPR(Base), m, sz, S, LongSignedImmediateOffset);
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// dld.u[{.b|.h|.d}]
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void::function::do_dld_u:instruction_address cia, unsigned32 *rDest, unsigned32 Base, unsigned32 *rBase, int m , int sz, int S, unsigned32 Offset
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do_ld_u (_SD, cia, rDest, Base, rBase, m, sz, S, Offset);
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void::function::do_dld_u:unsigned32 *rDest, unsigned32 Base, unsigned32 *rBase, int m , int sz, int S, unsigned32 Offset
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do_ld_u (_SD, rDest, Base, rBase, m, sz, S, Offset);
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31.Dest,26.Base,21.0b110101,15.m,14.sz,12.0,11.S,10.1,9./,4.IndOff::::dld.u r
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do_dld_u (_SD, cia, rDest, rBase, &GPR(Base), m, sz, S, rIndOff);
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do_dld_u (_SD, rDest, rBase, &GPR(Base), m, sz, S, rIndOff);
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31.Dest,26.Base,21.0b110101,15.m,14.sz,12.1,11.S,10.1,9./::::dld.u l
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long_immediate (LongSignedImmediateOffset);
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do_dld_u (_SD, cia, rDest, rBase, &GPR(Base), m, sz, S, LongSignedImmediateOffset);
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do_dld_u (_SD, rDest, rBase, &GPR(Base), m, sz, S, LongSignedImmediateOffset);
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// dst[{.b|.h|.d}]
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void::function::do_dst:instruction_address cia, int Source, unsigned32 Base, unsigned32 *rBase, int m , int sz, int S, unsigned32 Offset
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do_st (_SD, cia, Source, Base, rBase, m, sz, S, Offset);
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void::function::do_dst:int Source, unsigned32 Base, unsigned32 *rBase, int m , int sz, int S, unsigned32 Offset
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do_st (_SD, Source, Base, rBase, m, sz, S, Offset);
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31.Source,26.Base,21.0b110110,15.m,14.sz,12.0,11.S,10.1,9./,4.IndOff::::dst r
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do_dst (_SD, cia, Source, rBase, &GPR(Base), m, sz, S, rIndOff);
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do_dst (_SD, Source, rBase, &GPR(Base), m, sz, S, rIndOff);
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31.Source,26.Base,21.0b110110,15.m,14.sz,12.1,11.S,10.1,9./::::dst l
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long_immediate (LongSignedImmediateOffset);
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do_dst (_SD, cia, Source, rBase, &GPR(Base), m, sz, S, LongSignedImmediateOffset);
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do_dst (_SD, Source, rBase, &GPR(Base), m, sz, S, LongSignedImmediateOffset);
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// estop
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@ -380,7 +380,7 @@ void::function::do_dst:instruction_address cia, int Source, unsigned32 Base, uns
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// jsr[.a]
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instruction_address::function::do_jsr:instruction_address cia, instruction_address nia, signed32 *rLink, int annul, unsigned32 offset, unsigned32 base
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instruction_address::function::do_jsr:instruction_address nia, signed32 *rLink, int annul, unsigned32 offset, unsigned32 base
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if (annul)
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{
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*rLink = nia.ip;
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@ -394,16 +394,16 @@ instruction_address::function::do_jsr:instruction_address cia, instruction_addre
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(unsigned long) nia.dp);
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return nia;
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31.Link,26.Base,21.0b100010,15.A,14.SignedOffset::::jsr i
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nia = do_jsr (_SD, cia, nia, rLink, A, vSignedOffset, rBase);
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nia = do_jsr (_SD, nia, rLink, A, vSignedOffset, rBase);
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31.Link,26.Base,21.0b11100010,13.A,12.0,11./,4.Source1::::jsr r
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nia = do_jsr (_SD, cia, nia, rLink, A, rSource1, rBase);
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nia = do_jsr (_SD, nia, rLink, A, rSource1, rBase);
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31.Link,26.Base,21.0b11100010,13.A,12.1,11./::::jsr l
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long_immediate (LongSignedImmediate);
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nia = do_jsr (_SD, cia, nia, rLink, A, LongSignedImmediate, rBase);
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nia = do_jsr (_SD, nia, rLink, A, LongSignedImmediate, rBase);
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// ld[{.b.h.d}]
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void::function::do_ld:instruction_address cia, int Dest, unsigned32 Base, unsigned32 *rBase, int m , int sz, int S, unsigned32 Offset
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void::function::do_ld:int Dest, unsigned32 Base, unsigned32 *rBase, int m , int sz, int S, unsigned32 Offset
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unsigned32 addr;
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switch (sz)
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{
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@ -439,16 +439,16 @@ void::function::do_ld:instruction_address cia, int Dest, unsigned32 Base, unsign
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engine_error (SD, CPU, cia, "ld - invalid sz %d", sz);
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}
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31.Dest,26.Base,21.0b0100,17.m,16.sz,14.SignedOffset::::ld i
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do_ld (_SD, cia, Dest, rBase, &GPR(Base), m, sz, 0, vSignedOffset);
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do_ld (_SD, Dest, rBase, &GPR(Base), m, sz, 0, vSignedOffset);
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31.Dest,26.Base,21.0b110100,15.m,14.sz,12.0,11.S,10.0,9./,4.IndOff::::ld r
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do_ld (_SD, cia, Dest, rBase, &GPR(Base), m, sz, S, rIndOff);
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do_ld (_SD, Dest, rBase, &GPR(Base), m, sz, S, rIndOff);
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31.Dest,26.Base,21.0b110100,15.m,14.sz,12.1,11.S,10.0,9./::::ld l
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long_immediate (LongSignedImmediateOffset);
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do_ld (_SD, cia, Dest, rBase, &GPR(Base), m, sz, S, LongSignedImmediateOffset);
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do_ld (_SD, Dest, rBase, &GPR(Base), m, sz, S, LongSignedImmediateOffset);
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// ld.u[{.b.h.d}]
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void::function::do_ld_u:instruction_address cia, unsigned32 *rDest, unsigned32 Base, unsigned32 *rBase, int m , int sz, int S, unsigned32 Offset
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void::function::do_ld_u:unsigned32 *rDest, unsigned32 Base, unsigned32 *rBase, int m , int sz, int S, unsigned32 Offset
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unsigned32 addr;
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switch (sz)
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{
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@ -467,12 +467,12 @@ void::function::do_ld_u:instruction_address cia, unsigned32 *rDest, unsigned32 B
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if (m)
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*rBase = addr;
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31.Dest,26.Base,21.0b0101,17.m,16.sz,14.SignedOffset::::ld.u i
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do_ld_u (_SD, cia, rDest, rBase, &GPR(Base), m, sz, 0, vSignedOffset);
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do_ld_u (_SD, rDest, rBase, &GPR(Base), m, sz, 0, vSignedOffset);
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31.Dest,26.Base,21.0b110101,15.m,14.sz,12.0,11.S,10.0,9./,4.IndOff::::ld.u r
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do_ld_u (_SD, cia, rDest, rBase, &GPR(Base), m, sz, S, rIndOff);
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do_ld_u (_SD, rDest, rBase, &GPR(Base), m, sz, S, rIndOff);
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31.Dest,26.Base,21.0b110101,15.m,14.sz,12.1,11.S,10.0,9./::::ld.u l
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long_immediate (LongSignedImmediateOffset);
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do_ld_u (_SD, cia, rDest, rBase, &GPR(Base), m, sz, S, LongSignedImmediateOffset);
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do_ld_u (_SD, rDest, rBase, &GPR(Base), m, sz, S, LongSignedImmediateOffset);
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// lmo
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@ -527,16 +527,16 @@ void::function::do_or:unsigned32 *rDest, unsigned32 Source1, unsigned32 Source2
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// rdcr
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void::function::do_rdcr:instruction_address cia, unsigned32 Dest, int cr
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void::function::do_rdcr:unsigned32 Dest, int cr
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if (Dest != 0)
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engine_error (SD, CPU, cia, "rdcr unimplement");
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31.Dest,26.0,21.0b0000100,14.UCRN::::rdcr i
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do_rdcr (_SD, cia, Dest, UCRN);
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do_rdcr (_SD, Dest, UCRN);
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31.Dest,26.0,21.0b110000100,12.0,11./,4.INDCR::::rdcr r
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do_rdcr (_SD, cia, Dest, UCRN);
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do_rdcr (_SD, Dest, UCRN);
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31.Dest,26.0,21.0b110000100,12.1,11./::::rdcr l
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long_immediate (UnsignedControlRegisterNumber);
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do_rdcr (_SD, cia, Dest, UnsignedControlRegisterNumber);
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do_rdcr (_SD, Dest, UnsignedControlRegisterNumber);
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// rmo
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@ -553,7 +553,7 @@ void::function::do_rdcr:instruction_address cia, unsigned32 Dest, int cr
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// sl.{d|e|i}{m|s|z}
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void::function::do_shift:instruction_address cia, int Dest, int Source, int Merge, int i, int n, int EndMask, int Rotate
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void::function::do_shift:int Dest, int Source, int Merge, int i, int n, int EndMask, int Rotate
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/* see 10-30 for a reasonable description */
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unsigned32 rotated;
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unsigned32 endmask;
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@ -624,7 +624,7 @@ void::function::do_shift:instruction_address cia, int Dest, int Source, int Merg
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}
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31.Dest,26.Source,21.0b0001,17.Merge,14./,11.i,10.n,9.EndMask,4.Rotate::::sl i
|
||||
do_shift (_SD, cia, Dest, Source, Merge, i, n, EndMask, Rotate);
|
||||
do_shift (_SD, Dest, Source, Merge, i, n, EndMask, Rotate);
|
||||
31.Dest,26.Source,21.0b110001,15.Merge,12.0,11.i,10.n,9.EndMask,4.RotReg::::sl r
|
||||
int endmask;
|
||||
if (EndMask == 0)
|
||||
|
|
@ -637,7 +637,7 @@ void::function::do_shift:instruction_address cia, int Dest, int Source, int Merg
|
|||
cia.ip, Source);
|
||||
endmask = GPR (Source + 1) & 31;
|
||||
}
|
||||
do_shift (_SD, cia, Dest, Source, Merge, i, n, endmask, GPR (RotReg) & 31);
|
||||
do_shift (_SD, Dest, Source, Merge, i, n, endmask, GPR (RotReg) & 31);
|
||||
|
||||
|
||||
// sli.{d|e|i}{m|s|z}
|
||||
|
|
@ -662,7 +662,7 @@ void::function::do_shift:instruction_address cia, int Dest, int Source, int Merg
|
|||
|
||||
|
||||
// st[{.b|.h|.d}]
|
||||
void::function::do_st:instruction_address cia, int Source, unsigned32 Base, unsigned32 *rBase, int m , int sz, int S, unsigned32 Offset
|
||||
void::function::do_st:int Source, unsigned32 Base, unsigned32 *rBase, int m , int sz, int S, unsigned32 Offset
|
||||
unsigned32 addr;
|
||||
switch (sz)
|
||||
{
|
||||
|
|
@ -692,12 +692,12 @@ void::function::do_st:instruction_address cia, int Source, unsigned32 Base, unsi
|
|||
if (m)
|
||||
*rBase = addr;
|
||||
31.Source,26.Base,21.0b0110,17.m,16.sz,14.SignedOffset::::st i
|
||||
do_st (_SD, cia, Source, rBase, &GPR(Base), m, sz, 0, vSignedOffset);
|
||||
do_st (_SD, Source, rBase, &GPR(Base), m, sz, 0, vSignedOffset);
|
||||
31.Source,26.Base,21.0b110110,15.m,14.sz,12.0,11.S,10.0,9./,4.IndOff::::st r
|
||||
do_st (_SD, cia, Source, rBase, &GPR(Base), m, sz, S, rIndOff);
|
||||
do_st (_SD, Source, rBase, &GPR(Base), m, sz, S, rIndOff);
|
||||
31.Source,26.Base,21.0b110110,15.m,14.sz,12.1,11.S,10.0,9./::::st l
|
||||
long_immediate (LongSignedImmediateOffset);
|
||||
do_st (_SD, cia, Source, rBase, &GPR(Base), m, sz, S, LongSignedImmediateOffset);
|
||||
do_st (_SD, Source, rBase, &GPR(Base), m, sz, S, LongSignedImmediateOffset);
|
||||
|
||||
|
||||
// sub
|
||||
|
|
@ -738,7 +738,7 @@ void::function::do_subu:signed32 *rDest, signed32 Source1, signed32 Source2
|
|||
|
||||
|
||||
// trap
|
||||
void::function::do_trap:instruction_address cia, unsigned32 trap_number
|
||||
void::function::do_trap:unsigned32 trap_number
|
||||
switch (trap_number)
|
||||
{
|
||||
case 72:
|
||||
|
|
@ -779,12 +779,12 @@ void::function::do_trap:instruction_address cia, unsigned32 trap_number
|
|||
(unsigned long) cia.ip, trap_number);
|
||||
}
|
||||
31./,27.0,26./,21.0b0000001,14.UTN::::trap i
|
||||
do_trap (_SD, cia, UTN);
|
||||
do_trap (_SD, UTN);
|
||||
31./,27.0,26./,21.0b110000001,12.0,11./,4.INDTR::::trap r
|
||||
do_trap (_SD, cia, UTN);
|
||||
do_trap (_SD, UTN);
|
||||
31./,27.0,26./,21.0b110000001,12.1,11./::::trap l
|
||||
long_immediate (UTN);
|
||||
do_trap (_SD, cia, UTN);
|
||||
do_trap (_SD, UTN);
|
||||
|
||||
|
||||
// vadd.{s|d}{s|d}
|
||||
|
|
|
|||
|
|
@ -27,6 +27,14 @@
|
|||
|
||||
#include <signal.h>
|
||||
|
||||
#ifdef HAVE_STRING_H
|
||||
#include <string.h>
|
||||
#else
|
||||
#ifdef HAVE_STRINGS_H
|
||||
#include <strings.h>
|
||||
#endif
|
||||
#endif
|
||||
|
||||
void
|
||||
engine_init (SIM_DESC sd)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -26,7 +26,8 @@
|
|||
|
||||
#include "bfd.h"
|
||||
#include "sim-main.h"
|
||||
|
||||
#include "sim-utils.h"
|
||||
#include "sim-options.h"
|
||||
|
||||
#ifdef HAVE_STDLIB_H
|
||||
#include <stdlib.h>
|
||||
|
|
@ -51,10 +52,6 @@ struct sim_state simulation = { 0 };
|
|||
SIM_DESC
|
||||
sim_open (SIM_OPEN_KIND kind, char **argv)
|
||||
{
|
||||
/*FIXME - later make these configurable */
|
||||
static void *eit_ram;
|
||||
static int sizeof_eit_ram = 0x1000;
|
||||
|
||||
STATE_OPEN_KIND (&simulation) = kind;
|
||||
|
||||
/* establish the simulator configuration */
|
||||
|
|
|
|||
|
|
@ -24,32 +24,26 @@
|
|||
#define _SIM_MAIN_H_
|
||||
|
||||
#include "sim-basics.h"
|
||||
#include "sim-inline.h"
|
||||
#include "sim-types.h"
|
||||
#include "sim-bits.h"
|
||||
#include "sim-endian.h"
|
||||
|
||||
#include <signal.h>
|
||||
|
||||
/* These are generated files. */
|
||||
#include "itable.h"
|
||||
#include "idecode.h"
|
||||
#include "idecode.h"
|
||||
|
||||
typedef instruction_address sim_cia;
|
||||
static const sim_cia null_cia = {0}; /* Dummy */
|
||||
#define NULL_CIA null_cia
|
||||
|
||||
#include "sim-base.h"
|
||||
|
||||
#include "cpu.h"
|
||||
#include "alu.h"
|
||||
|
||||
#include "sim-core.h"
|
||||
#include "sim-events.h"
|
||||
#include "sim-io.h"
|
||||
|
||||
|
||||
struct sim_state {
|
||||
|
||||
/* real time */
|
||||
sim_events events;
|
||||
|
||||
/* memory and IO */
|
||||
sim_core core;
|
||||
|
||||
/* escape route for inner functions */
|
||||
int halt_ok;
|
||||
jmp_buf path_to_halt;
|
||||
|
|
|
|||
Loading…
Reference in a new issue