darkkirb/old-cross-binutils
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

New header file for PowerPC opcode table.

Browse source
This commit is contained in:
Ian Lance Taylor 1994-01-22 00:13:02 +00:00
parent 89221bd5f4
commit d8de27f90d
1 changed files with 196 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

196
include/opcode/ppc.h Normal file
View file

@ -0,0 +1,196 @@
/* ppc.h -- Header file for PowerPC opcode table
Copyright 1994 Free Software Foundation, Inc.
Written by Ian Lance Taylor, Cygnus Support
This file is part of GDB, GAS, and the GNU binutils.
GDB, GAS, and the GNU binutils are free software; you can redistribute
them and/or modify them under the terms of the GNU General Public
License as published by the Free Software Foundation; either version
1, or (at your option) any later version.
GDB, GAS, and the GNU binutils are distributed in the hope that they
will be useful, but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
the GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this file; see the file COPYING. If not, write to the Free
Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
#ifndef PPC_H
#define PPC_H
/* The opcode table is an array of struct powerpc_opcode. */
struct powerpc_opcode
{
/* The opcode name. */
const char *name;
/* The opcode itself. Those bits which will be filled in with
operands are zeroes. */
unsigned long opcode;
/* The opcode mask. This is used by the disassembler. This is a
mask containing ones indicating those bits which must match the
opcode field, and zeroes indicating those bits which need not
match (and are presumably filled in by operands). */
unsigned long mask;
/* One bit flags for the opcode. These are used to indicate which
specific processors support the instructions. The defined values
are listed below. */
unsigned long flags;
/* An array of operand codes. Each code is an index into the
operand table. They appear in the order which the operands must
appear in assembly code, and are terminated by a zero. */
char operands[8];
};
/* The table itself is sorted by major opcode number, and is otherwise
in the order in which the disassembler should consider
instructions. */
extern const struct powerpc_opcode powerpc_opcodes[];
extern const int powerpc_num_opcodes;
/* Values defined for the flags field of a struct powerpc_opcode. */
/* Opcode is defined for the PowerPC architecture. */
#define PPC_OPCODE_PPC (01)
/* Opcode is defined for the POWER (RS/6000) architecture. */
#define PPC_OPCODE_POWER (02)
/* Opcode is defined for the POWER2 (Rios 2) architecture. */
#define PPC_OPCODE_POWER2 (04)
/* Opcode is only defined on 32 bit architectures. */
#define PPC_OPCODE_32 (010)
/* Opcode is only defined on 64 bit architectures. */
#define PPC_OPCODE_64 (020)
/* A macro to extract the major opcode from an instruction. */
#define PPC_OP(i) (((i) >> 26) & 0x3f)
/* The operands table is an array of struct powerpc_operand. */
struct powerpc_operand
{
/* The number of bits in the operand. */
int bits;
/* How far the operand is left shifted in the instruction. */
int shift;
/* Non zero if the operand is signed (this is zero for most
operands). */
int signedp;
/* Insertion function. This is used by the assembler. To insert an
operand value into an instruction, check this field.
If it is NULL, execute
i |= (op & ((1 << o->bits) - 1)) << o->shift;
(i is the instruction which we are filling in, o is a pointer to
this structure, and op is the opcode value; this assumes twos
complement arithmetic).
If this field is not NULL, then simply call it with the
instruction and the operand value. It will return the new value
of the instruction. If the ERRMSG argument is not NULL, then if
the operand value is illegal, *ERRMSG will be set to a warning
string (the operand will be inserted in any case). If the
operand value is legal, *ERRMSG will be unchanged (most operands
can accept any value). */
unsigned long (*insert) PARAMS ((unsigned long instruction, long op,
const char **errmsg));
/* Extraction function. This is used by the disassembler. To
extract this operand type from an instruction, check this field.
If it is NULL, compute
op = ((i) >> o->shift) & ((1 << o->bits) - 1);
if (o->signedp
&& (op & (1 << (o->bits - 1))) != 0)
op -= 1 << o->bits;
(i is the instruction, o is a pointer to this structure, and op
is the result; this assumes twos complement arithmetic).
If this field is not NULL, then simply call it with the
instruction value. It will return the value of the operand. If
the INVALID argument is not NULL, *INVALID will be set to
non-zero if this operand type can not actually be extracted from
this operand (i.e., the instruction does not match). If the
operand is valid, *INVALID will not be changed. */
long (*extract) PARAMS ((unsigned long instruction, int *invalid));
/* One bit syntax flags. */
unsigned long flags;
};
/* Elements in the table are retrieved by indexing with values from
the operands field of the powerpc_opcodes table. */
extern const struct powerpc_operand powerpc_operands[];
/* Values defined for the flags field of a struct powerpc_operand. */
/* This operand does not actually exist in the assembler input. This
is used to support extended mnemonics such as mr, for which two
operands fields are identical. The assembler should call the
insert function with any op value. The disassembler should call
the extract function, ignore the return value, and check the value
placed in the valid argument. */
#define PPC_OPERAND_FAKE (01)
/* The next operand should be wrapped in parentheses rather than
separated from this one by a comma. This is used for the load and
store instructions which want their operands to look like
reg,displacement(reg)
*/
#define PPC_OPERAND_PARENS (02)
/* This operand may use the symbolic names for the CR fields, which
are
lt 0 gt 1 eq 2 so 3 un 3
cr0 0 cr1 1 cr2 2 cr3 3
cr4 4 cr5 5 cr6 6 cr7 7
These may be combined arithmetically, as in cr2*4+gt. These are
only supported on the PowerPC, not the POWER. */
#define PPC_OPERAND_CR (04)
/* This operand names a register. The disassembler uses this to print
register names with a leading 'r'. */
#define PPC_OPERAND_GPR (010)
/* This operand names a floating point register. The disassembler
prints these with a leading 'f'. */
#define PPC_OPERAND_FPR (020)
/* This operand is a relative branch displacement. The disassembler
prints these symbolically if possible. */
#define PPC_OPERAND_RELATIVE (0100)
/* This operand is an absolute branch address. The disassembler
prints these symbolically if possible. */
#define PPC_OPERAND_ABSOLUTE (0200)
/* This operand is optional, and is zero if omitted. This is used for
the optional BF and L fields in the comparison instructions. The
assembler must count the number of operands remaining on the line,
and the number of operands remaining for the opcode, and decide
whether this operand is present or not. The disassembler should
print this operand out only if it is not zero. */
#define PPC_OPERAND_OPTIONAL (0400)
/* This operand should be regarded as a negative number for the
purposes of overflow checking (i.e., the normal most negative
number is disallowed and one more than the normal most positive
number is allowed). This flag will only be set for a signed
operand. */
#define PPC_OPERAND_NEGATIVE (01000)
#endif /* PPC_H */