* Makefile.in (IGEN_INCLUDE): Add missing includes for m16e.igen and
mips3264r2.igen. Add missing dependency rules. * m16e.igen: Support for mips16e save/restore instructions.
This commit is contained in:
Thiemo Seufer
parent
6b637da758
commit
d85c3a10ae
3 changed files with 281 additions and 1 deletions
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@ -1,3 +1,10 @@
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2006-08-29 Thiemo Seufer <ths@mips.com>
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David Ung <davidu@mips.com>
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* Makefile.in (IGEN_INCLUDE): Add missing includes for m16e.igen and
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mips3264r2.igen. Add missing dependency rules.
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* m16e.igen: Support for mips16e save/restore instructions.
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2006-06-13 Richard Earnshaw <rearnsha@arm.com>
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* configure: Regenerated.
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@ -92,12 +92,14 @@ IGEN_DC=$(srcdir)/mips.dc
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M16_DC=$(srcdir)/m16.dc
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IGEN_INCLUDE=\
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$(srcdir)/m16.igen \
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$(srcdir)/m16e.igen \
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$(srcdir)/mdmx.igen \
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$(srcdir)/mips3d.igen \
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$(srcdir)/sb1.igen \
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$(srcdir)/tx.igen \
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$(srcdir)/vr.igen \
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$(srcdir)/dsp.igen \
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$(srcdir)/mips3264r2.igen \
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# NB: Since these can be built by a number of generators, care
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# must be taken to ensure that they are only dependant on
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@ -184,8 +186,15 @@ support.o: sim-main.h support.c $(SIM_EXTRA_DEPS)
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idecode.o: sim-main.h idecode.c $(SIM_EXTRA_DEPS)
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itable.o: sim-main.h itable.c $(SIM_EXTRA_DEPS)
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m16_semantics.o: sim-main.h m16_semantics.c $(SIM_EXTRA_DEPS)
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m16_support.o: sim-main.h m16_support.c $(SIM_EXTRA_DEPS)
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m16_idecode.o: sim-main.h m16_idecode.c $(SIM_EXTRA_DEPS)
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m16_icache.o: sim-main.h m16_icache.c $(SIM_EXTRA_DEPS)
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m32_semantics.o: sim-main.h m32_semantics.c $(SIM_EXTRA_DEPS)
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m32_support.o: sim-main.h m32_support.c $(SIM_EXTRA_DEPS)
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m32_idecode.o: sim-main.h m32_idecode.c $(SIM_EXTRA_DEPS)
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m32_icache.o: sim-main.h m32_icache.c $(SIM_EXTRA_DEPS)
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BUILT_SRC_FROM_M16 = \
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m16_icache.h \
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@ -103,3 +103,267 @@
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RA = NIA;
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NIA = GPR[TRX];
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}
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// format routines for save/restore
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:%s::::RAS:int ras
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*mips16e
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{
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static char buf[10];
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buf[0] = '\0';
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if (ras & 4)
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strcat (buf,"ra,");
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if (ras & 2)
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strcat (buf,"s0,");
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if (ras & 1)
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strcat (buf,"s1,");
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return (buf);
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}
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:%s::::XSREGS:int xsregs
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*mips16e
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{
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if (xsregs > 6)
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return "s2,s3,s4,s5,s6,s7,s8,";
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if (xsregs > 5)
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return "s2,s3,s4,s5,s6,s7,";
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if (xsregs > 4)
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return "s2,s3,s4,s5,s6,";
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if (xsregs > 3)
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return "s2,s3,s4,s5,";
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if (xsregs > 2)
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return "s2,s3,s4,";
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if (xsregs > 1)
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return "s2,s3,";
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if (xsregs > 0)
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return "s2,";
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return "";
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}
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:%s::::AREGS:int aregs
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*mips16e
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{
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// Fixme: how is the arg/static distinction made by the assembler?
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static const char * const aregstr[16] = {
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"",
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"A3,",
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"A2,A3,",
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"A1,A2,A3,",
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"A0,A1,A2,A3,",
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"a0,",
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"a0,A3,",
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"a0,A2,A3,",
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"a0,A1,A2,A3,",
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"a0,a1,",
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"a0,a1,A3,",
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"a0,a1,A2,A3,",
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"a0,a1,a2,",
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"a0,a1,a2,A3,",
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"?,"
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};
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return aregstr[aregs];
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}
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:compute:::int:SFRAME:FS:((FS == 0) ? 128 \: (FS << 3))
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:compute:::int:BFRAME:FSHI,FSLO:(((FSHI << 4) | FSLO) << 3)
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:function:::void:do_save:int xsregs, int aregs, int ras0s1, int framesize
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{
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unsigned_word temp;
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int args, astatic;
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temp = GPR[29];
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/* writes are in the same order as the hardware description... */
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switch (aregs) {
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case 0: case 1: case 2: case 3: case 11:
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args = 0;
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break;
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case 4: case 5: case 6: case 7:
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args = 1;
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break;
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case 8: case 9: case 10:
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args = 2;
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break;
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case 12: case 13:
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args = 3;
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break;
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case 14:
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args = 4;
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break;
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default:
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sim_engine_abort (SD, CPU, CIA, "save: aregs=%d causes unpredictable results\n", aregs);
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}
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if (args > 0) {
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do_store (SD_, AccessLength_WORD, temp, 0, GPR[4]);
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if (args > 1) {
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do_store (SD_,AccessLength_WORD, temp, 4 , GPR[5]);
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if (args > 2) {
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do_store (SD_,AccessLength_WORD, temp, 8 , GPR[6]);
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if (args > 3) {
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do_store (SD_,AccessLength_WORD, temp, 12, GPR[7]);
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}
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}
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}
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}
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if (ras0s1 & 4)
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do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[31]);
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switch (xsregs) {
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case 7:
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do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[30]);
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case 6:
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do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[23]);
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case 5:
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do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[22]);
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case 4:
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do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[21]);
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case 3:
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do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[20]);
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case 2:
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do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[19]);
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case 1:
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do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[18]);
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}
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if (ras0s1 & 1)
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do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[17]);
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if (ras0s1 & 2)
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do_store (SD_,AccessLength_WORD, temp -= 4, 0, GPR[16]);
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switch (aregs) {
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case 0: case 4: case 8: case 12: case 14:
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astatic = 0;
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break;
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case 1: case 5: case 9: case 13:
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astatic = 1;
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break;
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case 2: case 6: case 10:
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astatic = 2;
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break;
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case 3: case 7:
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astatic = 3;
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break;
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case 11:
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astatic = 4;
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break;
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default:
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sim_engine_abort (SD, CPU, CIA, "save: aregs=%d causes unpredictable results\n", aregs);
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}
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if (astatic > 0) {
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do_store (SD_, AccessLength_WORD, temp -= 4, 0, GPR[7]);
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if (astatic > 1) {
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do_store (SD_, AccessLength_WORD, temp -= 4, 0, GPR[6]);
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if (astatic > 2) {
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do_store (SD_, AccessLength_WORD, temp -= 4, 0, GPR[5]);
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if (astatic > 3) {
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do_store (SD_, AccessLength_WORD, temp -= 4, 0, GPR[4]);
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}
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}
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}
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}
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GPR[29] -= framesize;
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}
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01100,100,1,3.RAS,4.FS:I8:16::SAVE
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"save %s<RAS>,<SFRAME>"
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*mips16e
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{
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do_save (SD_, 0, 0, RAS, SFRAME);
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}
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11110,3.XSREGS,4.FSHI,4.AREGS + 01100,100,1,3.RAS,4.FSLO:EXT-I8:16::SAVE
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"save %s<RAS>%s<XSREGS>%s<AREGS><BFRAME>"
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*mips16e
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{
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do_save (SD_, XSREGS, AREGS, RAS, BFRAME);
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}
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:function:::void:do_restore:int xsregs, int aregs, int ras0s1, int framesize
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*mips16e
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{
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unsigned_word temp, temp2;
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int astatic;
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temp = GPR[29] + framesize;
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temp2 = temp;
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/* reads are in the same order as the hardware description... */
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if (ras0s1 & 4)
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GPR[31] = EXTEND32 (do_load(SD_, AccessLength_WORD, temp -= 4, 0));
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switch (xsregs) {
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case 7:
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GPR[30] = EXTEND32 (do_load (SD_,AccessLength_WORD, temp -= 4, 0));
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case 6:
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GPR[23] = EXTEND32 (do_load (SD_,AccessLength_WORD, temp -= 4, 0));
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case 5:
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GPR[22] = EXTEND32 (do_load (SD_,AccessLength_WORD, temp -= 4, 0));
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case 4:
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GPR[21] = EXTEND32 (do_load (SD_,AccessLength_WORD, temp -= 4, 0));
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case 3:
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GPR[20] = EXTEND32 (do_load (SD_,AccessLength_WORD, temp -= 4, 0));
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case 2:
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GPR[19] = EXTEND32 (do_load (SD_,AccessLength_WORD, temp -= 4, 0));
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case 1:
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GPR[18] = EXTEND32 (do_load (SD_,AccessLength_WORD, temp -= 4, 0));
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}
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if (ras0s1 & 1)
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GPR[17] = EXTEND32 (do_load (SD_,AccessLength_WORD, temp -= 4, 0));
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if (ras0s1 & 2)
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GPR[16] = EXTEND32 (do_load (SD_,AccessLength_WORD, temp -= 4, 0));
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switch (aregs) {
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case 0: case 4: case 8: case 12: case 14:
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astatic = 0;
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break;
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case 1: case 5: case 9: case 13:
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astatic = 1;
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break;
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case 2: case 6: case 10:
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astatic = 2;
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break;
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case 3: case 7:
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astatic = 3;
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break;
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case 11:
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astatic = 4;
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break;
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default:
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sim_engine_abort (SD, CPU, CIA, "save: aregs=%d causes unpredictable results\n", aregs);
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}
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if (astatic > 0) {
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GPR[7] = EXTEND32 (do_load (SD_,AccessLength_WORD, temp -= 4, 0));
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if (astatic > 1) {
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GPR[6] = EXTEND32 (do_load (SD_,AccessLength_WORD, temp -= 4, 0));
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if (astatic > 2) {
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GPR[5] = EXTEND32 (do_load (SD_,AccessLength_WORD, temp -= 4, 0));
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if (astatic > 3) {
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GPR[4] = EXTEND32 (do_load (SD_,AccessLength_WORD, temp -= 4, 0));
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}
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}
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}
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}
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GPR[29] = temp2;
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}
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01100,100,0,3.RAS,4.FS:I8:16::RESTORE
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"restore %s<RAS>,<SFRAME>"
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*mips16e
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{
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do_restore (SD_,0,0,RAS,SFRAME);
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}
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11110,3.XSREGS,4.FSHI,4.AREGS + 01100,100,0,3.RAS,4.FSLO:EXT-I8:16::RESTORE
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"restore %s<RAS>%s<XSREGS>%s<AREGS><BFRAME>"
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*mips16e
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{
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do_restore (SD_,XSREGS,AREGS,RAS,BFRAME);
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}
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