2007-05-08 Paul Gilliam <pgilliam@us.ibm.com>
Luis Machado <luisgpm@br.ibm.com> * rs6000-tdep.c: (LWARX_MASK, LWARX_INSTRUCTION, LDARX_INSTRUCTION, STWCX_MASK, STWCX_INSTRUCTION, STDCX_INSTRUCTION, BC_MASK, BC_INSTRUCTION): Define. (deal_with_atomic_sequence): New function. (rs6000_software_single_step): Call deal_with_atomic_sequence. (rs6000_gdbarch_init): Install deal_with_atomic_sequence as gdbarch_software_single_step routine.
This commit is contained in:
Ulrich Weigand
parent
e46ab5135e
commit
ce5eab59d8
2 changed files with 106 additions and 1 deletions
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@ -1,3 +1,14 @@
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2007-05-08 Paul Gilliam <pgilliam@us.ibm.com>
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Luis Machado <luisgpm@br.ibm.com>
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* rs6000-tdep.c: (LWARX_MASK, LWARX_INSTRUCTION, LDARX_INSTRUCTION,
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STWCX_MASK, STWCX_INSTRUCTION, STDCX_INSTRUCTION, BC_MASK,
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BC_INSTRUCTION): Define.
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(deal_with_atomic_sequence): New function.
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(rs6000_software_single_step): Call deal_with_atomic_sequence.
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(rs6000_gdbarch_init): Install deal_with_atomic_sequence as
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gdbarch_software_single_step routine.
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2007-05-07 Ulrich Weigand <uweigand@de.ibm.com>
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* spu-linux-nat.c (fetch_ppc_register, fetch_ppc_memory_1,
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@ -707,7 +707,95 @@ rs6000_breakpoint_from_pc (CORE_ADDR *bp_addr, int *bp_size)
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}
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/* AIX does not support PT_STEP. Simulate it. */
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/* Instruction masks used during single-stepping of atomic sequences. */
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#define LWARX_MASK 0xfc0007fe
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#define LWARX_INSTRUCTION 0x7c000028
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#define LDARX_INSTRUCTION 0x7c0000A8
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#define STWCX_MASK 0xfc0007ff
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#define STWCX_INSTRUCTION 0x7c00012d
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#define STDCX_INSTRUCTION 0x7c0001ad
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#define BC_MASK 0xfc000000
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#define BC_INSTRUCTION 0x40000000
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/* Checks for an atomic sequence of instructions beginning with a LWARX/LDARX
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instruction and ending with a STWCX/STDCX instruction. If such a sequence
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is found, attempt to step through it. A breakpoint is placed at the end of
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the sequence. */
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static int
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deal_with_atomic_sequence (struct regcache *regcache)
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{
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CORE_ADDR pc = read_pc ();
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CORE_ADDR breaks[2] = {-1, -1};
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CORE_ADDR loc = pc;
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CORE_ADDR branch_bp; /* Breakpoint at branch instruction's destination. */
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int insn = read_memory_integer (loc, PPC_INSN_SIZE);
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int insn_count;
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int index;
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int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */
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const int atomic_sequence_length = 16; /* Instruction sequence length. */
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const int opcode = BC_INSTRUCTION; /* Branch instruction's OPcode. */
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int bc_insn_count = 0; /* Conditional branch instruction count. */
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/* Assume all atomic sequences start with a lwarx/ldarx instruction. */
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if ((insn & LWARX_MASK) != LWARX_INSTRUCTION
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&& (insn & LWARX_MASK) != LDARX_INSTRUCTION)
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return 0;
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/* Assume that no atomic sequence is longer than "atomic_sequence_length"
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instructions. */
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for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count)
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{
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loc += PPC_INSN_SIZE;
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insn = read_memory_integer (loc, PPC_INSN_SIZE);
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/* Assume that there is at most one conditional branch in the atomic
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sequence. If a conditional branch is found, put a breakpoint in
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its destination address. */
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if ((insn & BC_MASK) == BC_INSTRUCTION)
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{
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if (bc_insn_count >= 1)
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return 0; /* More than one conditional branch found, fallback
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to the standard single-step code. */
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branch_bp = branch_dest (opcode, insn, pc, breaks[0]);
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if (branch_bp != -1)
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{
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breaks[1] = branch_bp;
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bc_insn_count++;
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last_breakpoint++;
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}
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}
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if ((insn & STWCX_MASK) == STWCX_INSTRUCTION
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|| (insn & STWCX_MASK) == STDCX_INSTRUCTION)
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break;
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}
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/* Assume that the atomic sequence ends with a stwcx/stdcx instruction. */
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if ((insn & STWCX_MASK) != STWCX_INSTRUCTION
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&& (insn & STWCX_MASK) != STDCX_INSTRUCTION)
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return 0;
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loc += PPC_INSN_SIZE;
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insn = read_memory_integer (loc, PPC_INSN_SIZE);
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/* Insert a breakpoint right after the end of the atomic sequence. */
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breaks[0] = loc;
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/* Check for duplicated breakpoints. */
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if (last_breakpoint && (breaks[1] == breaks[0]))
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last_breakpoint = 0;
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/* Effectively inserts the breakpoints. */
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for (index = 0; index <= last_breakpoint; index++)
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insert_single_step_breakpoint (breaks[index]);
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return 1;
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}
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/* AIX does not support PT_STEP. Simulate it. */
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int
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rs6000_software_single_step (struct regcache *regcache)
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@ -724,6 +812,9 @@ rs6000_software_single_step (struct regcache *regcache)
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insn = read_memory_integer (loc, 4);
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if (deal_with_atomic_sequence (regcache))
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return 1;
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breaks[0] = loc + breakp_sz;
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opcode = insn >> 26;
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breaks[1] = branch_dest (opcode, insn, loc, breaks[0]);
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@ -3448,6 +3539,9 @@ rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
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set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
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set_gdbarch_breakpoint_from_pc (gdbarch, rs6000_breakpoint_from_pc);
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/* Handles single stepping of atomic sequences. */
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set_gdbarch_software_single_step (gdbarch, deal_with_atomic_sequence);
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/* Handle the 64-bit SVR4 minimal-symbol convention of using "FN"
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for the descriptor and ".FN" for the entry-point -- a user
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specifying "break FN" will unexpectedly end up with a breakpoint
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