* aix-thread.c (ops_prepare_to_store): Eliminate.
(init_ops): Don't initialize ops.prepare_to_store. (store_regs_kern): Pre-fetch register buffers from child, because some registers may not be in the cache. Copy regs from register cache only if they are cached. (store_regs_lib): Copy regs from register cache only if they are cached. (fill_sprs32, (fill_sprs64, fill_fprs, fill_gprs32, fill_gprs64): Ditto.
This commit is contained in:
parent
61c5da0b4f
commit
cbe92db47b
2 changed files with 77 additions and 53 deletions
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@ -1,3 +1,15 @@
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2002-07-18 Michael Snyder <msnyder@redhat.com>
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* aix-thread.c (ops_prepare_to_store): Eliminate.
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(init_ops): Don't initialize ops.prepare_to_store.
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(store_regs_kern): Pre-fetch register buffers from child,
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because some registers may not be in the cache. Copy
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regs from register cache only if they are cached.
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(store_regs_lib): Copy regs from register cache only
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if they are cached.
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(fill_sprs32, (fill_sprs64, fill_fprs, fill_gprs32,
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fill_gprs64): Ditto.
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2002-07-22 Kevin Buettner <kevinb@redhat.com>
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* aix-thread.c (gdb_assert.h): Include.
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118
gdb/aix-thread.c
118
gdb/aix-thread.c
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@ -1220,7 +1220,8 @@ fill_gprs64 (uint64_t *vals)
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int regno;
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for (regno = 0; regno < FP0_REGNUM; regno++)
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regcache_collect (regno, vals + regno);
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if (register_cached (regno))
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regcache_collect (regno, vals + regno);
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}
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static void
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@ -1229,7 +1230,8 @@ fill_gprs32 (uint32_t *vals)
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int regno;
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for (regno = 0; regno < FP0_REGNUM; regno++)
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regcache_collect (regno, vals + regno);
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if (register_cached (regno))
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regcache_collect (regno, vals + regno);
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}
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/* Store the floating point registers into a double array. */
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@ -1239,7 +1241,8 @@ fill_fprs (double *vals)
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int regno;
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for (regno = FP0_REGNUM; regno < FPLAST_REGNUM; regno++)
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regcache_collect (regno, vals + regno);
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if (register_cached (regno))
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regcache_collect (regno, vals + regno);
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}
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/* Store the special registers into the specified 64-bit and 32-bit
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@ -1253,12 +1256,18 @@ fill_sprs64 (uint64_t *iar, uint64_t *msr, uint32_t *cr,
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gdb_assert (sizeof (*iar) == REGISTER_RAW_SIZE (regno));
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regcache_collect (regno, iar);
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regcache_collect (regno + 1, msr);
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regcache_collect (regno + 2, cr);
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regcache_collect (regno + 3, lr);
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regcache_collect (regno + 4, ctr);
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regcache_collect (regno + 5, xer);
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if (register_cached (regno))
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regcache_collect (regno, iar);
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if (register_cached (regno + 1))
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regcache_collect (regno + 1, msr);
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if (register_cached (regno + 2))
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regcache_collect (regno + 2, cr);
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if (register_cached (regno + 3))
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regcache_collect (regno + 3, lr);
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if (register_cached (regno + 4))
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regcache_collect (regno + 4, ctr);
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if (register_cached (regno + 5))
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regcache_collect (regno + 5, xer);
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}
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static void
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@ -1273,12 +1282,18 @@ fill_sprs32 (unsigned long *iar, unsigned long *msr, unsigned long *cr,
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sizeof (long) == 4). */
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gdb_assert (sizeof (*iar) == REGISTER_RAW_SIZE (regno));
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regcache_collect (regno, iar);
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regcache_collect (regno + 1, msr);
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regcache_collect (regno + 2, cr);
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regcache_collect (regno + 3, lr);
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regcache_collect (regno + 4, ctr);
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regcache_collect (regno + 5, xer);
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if (register_cached (regno))
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regcache_collect (regno, iar);
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if (register_cached (regno + 1))
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regcache_collect (regno + 1, msr);
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if (register_cached (regno + 2))
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regcache_collect (regno + 2, cr);
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if (register_cached (regno + 3))
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regcache_collect (regno + 3, lr);
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if (register_cached (regno + 4))
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regcache_collect (regno + 4, ctr);
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if (register_cached (regno + 5))
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regcache_collect (regno + 5, xer);
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}
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/* Store all registers into pthread PDTID, which doesn't have a kernel
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@ -1310,18 +1325,19 @@ store_regs_lib (pthdb_pthread_t pdtid)
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/* Collect general-purpose register values from the regcache. */
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for (i = 0; i < 32; i++)
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{
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if (arch64)
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{
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regcache_collect (i, (void *) &int64);
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ctx.gpr[i] = int64;
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}
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else
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{
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regcache_collect (i, (void *) &int32);
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ctx.gpr[i] = int32;
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}
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}
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if (register_cached (i))
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{
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if (arch64)
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{
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regcache_collect (i, (void *) &int64);
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ctx.gpr[i] = int64;
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}
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else
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{
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regcache_collect (i, (void *) &int32);
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ctx.gpr[i] = int32;
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}
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}
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/* Collect floating-point register values from the regcache. */
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fill_fprs (ctx.fpr);
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@ -1340,12 +1356,18 @@ store_regs_lib (pthdb_pthread_t pdtid)
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unsigned long tmp_iar, tmp_msr, tmp_cr, tmp_lr, tmp_ctr, tmp_xer;
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fill_sprs32 (&tmp_iar, &tmp_msr, &tmp_cr, &tmp_lr, &tmp_ctr, &tmp_xer);
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ctx.iar = tmp_iar;
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ctx.msr = tmp_msr;
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ctx.cr = tmp_cr;
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ctx.lr = tmp_lr;
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ctx.ctr = tmp_ctr;
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ctx.xer = tmp_xer;
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if (register_cached (FIRST_UISA_SP_REGNUM))
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ctx.iar = tmp_iar;
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if (register_cached (FIRST_UISA_SP_REGNUM + 1))
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ctx.msr = tmp_msr;
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if (register_cached (FIRST_UISA_SP_REGNUM + 2))
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ctx.cr = tmp_cr;
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if (register_cached (FIRST_UISA_SP_REGNUM + 3))
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ctx.lr = tmp_lr;
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if (register_cached (FIRST_UISA_SP_REGNUM + 4))
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ctx.ctr = tmp_ctr;
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if (register_cached (FIRST_UISA_SP_REGNUM + 5))
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ctx.xer = tmp_xer;
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}
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status = pthdb_pthread_setcontext (pd_session, pdtid, &ctx);
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@ -1381,11 +1403,15 @@ store_regs_kern (int regno, pthdb_tid_t tid)
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{
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if (arch64)
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{
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/* Pre-fetch: some regs may not be in the cache. */
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ptrace64aix (PTT_READ_GPRS, tid, (unsigned long) gprs64, 0, NULL);
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fill_gprs64 (gprs64);
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ptrace64aix (PTT_WRITE_GPRS, tid, (unsigned long) gprs64, 0, NULL);
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}
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else
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{
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/* Pre-fetch: some regs may not be in the cache. */
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ptrace32 (PTT_READ_GPRS, tid, gprs32, 0, NULL);
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fill_gprs32 (gprs32);
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ptrace32 (PTT_WRITE_GPRS, tid, gprs32, 0, NULL);
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}
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@ -1395,6 +1421,8 @@ store_regs_kern (int regno, pthdb_tid_t tid)
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if (regno == -1 || (regno >= FP0_REGNUM && regno <= FPLAST_REGNUM))
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{
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/* Pre-fetch: some regs may not be in the cache. */
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ptrace32 (PTT_READ_FPRS, tid, (int *) fprs, 0, NULL);
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fill_fprs (fprs);
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ptrace32 (PTT_WRITE_FPRS, tid, (int *) fprs, 0, NULL);
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}
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{
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if (arch64)
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{
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/* Must read first, not all of it's in the cache. */
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/* Pre-fetch: some registers won't be in the cache. */
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ptrace64aix (PTT_READ_SPRS, tid,
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(unsigned long) &sprs64, 0, NULL);
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fill_sprs64 (&sprs64.pt_iar, &sprs64.pt_msr, &sprs64.pt_cr,
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}
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else
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{
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/* Must read first, not all of it's in the cache. */
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/* Pre-fetch: some registers won't be in the cache. */
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ptrace32 (PTT_READ_SPRS, tid, (int *) &sprs32, 0, NULL);
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fill_sprs32 (&sprs32.pt_iar, &sprs32.pt_msr, &sprs32.pt_cr,
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&sprs32.pt_lr, &sprs32.pt_ctr, &sprs32.pt_xer);
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if (REGISTER_RAW_SIZE (LAST_UISA_SP_REGNUM))
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regcache_collect (LAST_UISA_SP_REGNUM, &sprs32.pt_mq);
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if (register_cached (LAST_UISA_SP_REGNUM))
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regcache_collect (LAST_UISA_SP_REGNUM, &sprs32.pt_mq);
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ptrace32 (PTT_WRITE_SPRS, tid, (int *) &sprs32, 0, NULL);
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}
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}
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}
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/* Prepare to copy the register cache to the child:
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The register cache must be fully fetched and up to date. */
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static void
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ops_prepare_to_store (void)
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{
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int regno;
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if (!PD_TID (inferior_ptid))
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base_ops.to_prepare_to_store ();
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else
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for (regno = 0; regno < NUM_REGS; regno++)
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if (!register_cached (regno))
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target_fetch_registers (regno);
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}
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/* Transfer LEN bytes of memory from GDB address MYADDR to target
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address MEMADDR if WRITE and vice versa otherwise. */
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ops.to_wait = ops_wait;
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ops.to_fetch_registers = ops_fetch_registers;
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ops.to_store_registers = ops_store_registers;
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ops.to_prepare_to_store = ops_prepare_to_store;
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ops.to_xfer_memory = ops_xfer_memory;
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/* No need for ops.to_create_inferior, because we activate thread
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debugging when the inferior reaches pd_brk_addr. */
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