cpu/
* frv.cpu (nsdiv, nudiv, nsdivi, nudivi): Remove fr400 profiling unit. (scutss): Change unit to I0. (calll, callil, ccalll): Add missing FR550-MAJOR and profile unit. (mqsaths): Fix FR400-MAJOR categorization. (media-quad-multiply-cross-acc, media-quad-cross-multiply-cross-acc) (media-quad-cross-multiply-acc): Change unit from MDUALACC to FMALL. * frv.opc (fr400_check_insn_major_constraints): Check for (M-2,M-1) combinations. opcodes/ * frv-desc.c, frv-opc.c: Regenerate. sim/frv/ * cache.c (frv_cache_init): Change fr400 cache statistics to match the fr405. (non_cache_access): Add missing breaks. * interrupts.c (set_exception_status_registers): Always set EAR15 for data_access_errors. * memory.c (fr400_check_write_address): Remove redundant alignment check. * model.c: Regenerate.
This commit is contained in:
parent
8b73069fed
commit
c7a48b9ac9
11 changed files with 100 additions and 93 deletions
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@ -1,3 +1,14 @@
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2004-03-01 Richard Sandiford <rsandifo@redhat.com>
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* frv.cpu (nsdiv, nudiv, nsdivi, nudivi): Remove fr400 profiling unit.
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(scutss): Change unit to I0.
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(calll, callil, ccalll): Add missing FR550-MAJOR and profile unit.
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(mqsaths): Fix FR400-MAJOR categorization.
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(media-quad-multiply-cross-acc, media-quad-cross-multiply-cross-acc)
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(media-quad-cross-multiply-acc): Change unit from MDUALACC to FMALL.
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* frv.opc (fr400_check_insn_major_constraints): Check for (M-2,M-1)
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combinations.
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2004-03-01 Richard Sandiford <rsandifo@redhat.com>
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* frv.cpu (r-store, r-store-dual, r-store-quad): Delete.
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38
cpu/frv.cpu
38
cpu/frv.cpu
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@ -3032,8 +3032,7 @@
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(c-call VOID "@cpu@_signed_integer_divide"
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GRi GRj (index-of GRk) 1)
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(clobber GRk))
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((fr400 (unit u-idiv))
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(fr500 (unit u-idiv)) (fr550 (unit u-idiv)))
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((fr500 (unit u-idiv)) (fr550 (unit u-idiv)))
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)
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(dni udiv
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@ -3059,8 +3058,7 @@
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(c-call VOID "@cpu@_unsigned_integer_divide"
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GRi GRj (index-of GRk) 1)
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(clobber GRk))
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((fr400 (unit u-idiv))
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(fr500 (unit u-idiv)) (fr550 (unit u-idiv)))
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((fr500 (unit u-idiv)) (fr550 (unit u-idiv)))
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)
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; Multiplication
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@ -3158,7 +3156,7 @@
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(dni scutss
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"Integer accumulator cut with saturation"
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((UNIT IALL) (FR400-MAJOR I-1) (MACH fr400))
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((UNIT I0) (FR400-MAJOR I-1) (MACH fr400))
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"scutss$pack $GRj,$GRk"
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(+ pack GRk OP_46 (rs-null) OPE1_04 GRj)
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(set GRk (c-call SI "@cpu@_iacc_cut" (reg h-iacc0 0) GRj))
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@ -3562,8 +3560,7 @@
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(c-call VOID "@cpu@_signed_integer_divide"
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GRi s12 (index-of GRk) 1)
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(clobber GRk))
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((fr400 (unit u-idiv))
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(fr500 (unit u-idiv)) (fr550 (unit u-idiv)))
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((fr500 (unit u-idiv)) (fr550 (unit u-idiv)))
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)
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(dni udivi
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@ -3589,8 +3586,7 @@
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(c-call VOID "@cpu@_unsigned_integer_divide"
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GRi s12 (index-of GRk) 1)
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(clobber GRk))
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((fr400 (unit u-idiv))
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(fr500 (unit u-idiv)) (fr550 (unit u-idiv)))
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((fr500 (unit u-idiv)) (fr550 (unit u-idiv)))
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)
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(define-pmacro (multiply-r-simm name signop op comment)
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@ -5537,12 +5533,12 @@
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(dni calll
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"call and link"
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((UNIT I0) (FR500-MAJOR I-5) (FR400-MAJOR I-5))
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((UNIT I0) (FR500-MAJOR I-5) (FR550-MAJOR I-6) (FR400-MAJOR I-5))
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"calll$pack @($GRi,$GRj)"
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(+ pack (misc-null-1) (LI-on) OP_0C GRi (misc-null-2) GRj)
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(jump-and-link-semantics GRi GRj LI)
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((fr400 (unit u-branch))
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(fr500 (unit u-branch)))
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(fr500 (unit u-branch)) (fr550 (unit u-branch)))
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)
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(dni jmpil
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@ -5557,12 +5553,12 @@
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(dni callil
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"call immediate and link"
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((UNIT I0) (FR500-MAJOR I-5) (FR400-MAJOR I-5))
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((UNIT I0) (FR500-MAJOR I-5) (FR550-MAJOR I-6) (FR400-MAJOR I-5))
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"callil$pack @($GRi,$s12)"
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(+ pack (misc-null-1) (LI-on) OP_0D GRi s12)
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(jump-and-link-semantics GRi s12 LI)
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((fr400 (unit u-branch))
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(fr500 (unit u-branch)))
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(fr500 (unit u-branch)) (fr550 (unit u-branch)))
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)
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(dni call
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@ -6084,7 +6080,8 @@
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(dni cjmpl
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"conditional jump and link"
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((UNIT I0) (FR500-MAJOR I-5) (FR550-MAJOR I-6) (FR400-MAJOR I-5) CONDITIONAL)
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((UNIT I0) (FR500-MAJOR I-5) (FR550-MAJOR I-6)
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(FR400-MAJOR I-5) CONDITIONAL)
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"cjmpl$pack @($GRi,$GRj),$CCi,$cond"
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(+ pack (misc-null-1) (LI-off) OP_6A GRi CCi cond OPE4_2 GRj)
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(if (eq CCi (or cond 2))
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@ -6095,13 +6092,14 @@
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(dni ccalll
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"conditional call and link"
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((UNIT I0) (FR500-MAJOR I-5) (FR400-MAJOR I-5) CONDITIONAL)
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((UNIT I0) (FR500-MAJOR I-5) (FR550-MAJOR I-6)
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(FR400-MAJOR I-5) CONDITIONAL)
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"ccalll$pack @($GRi,$GRj),$CCi,$cond"
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(+ pack (misc-null-1) (LI-on) OP_6A GRi CCi cond OPE4_2 GRj)
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(if (eq CCi (or cond 2))
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(jump-and-link-semantics GRi GRj LI))
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((fr400 (unit u-branch))
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(fr500 (unit u-branch)))
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(fr500 (unit u-branch)) (fr550 (unit u-branch)))
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)
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(define-pmacro (cache-invalidate name cache all op ope profile comment)
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@ -7379,7 +7377,7 @@
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(dni mqsaths
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"Media quad saturation signed"
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((UNIT FMALL) (MACH fr400,fr550) (FR550-MAJOR M-2) (FR400-MAJOR M-1))
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((UNIT FMALL) (MACH fr400,fr550) (FR550-MAJOR M-2) (FR400-MAJOR M-2))
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"mqsaths$pack $FRintieven,$FRintjeven,$FRintkeven"
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(+ pack FRintkeven OP_78 FRintieven OPE1_0F FRintjeven)
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(if (orif (register-unaligned FRintieven 2)
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@ -8060,7 +8058,7 @@
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name mode conv addop rhw res max min op ope comment)
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(dni name
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(comment)
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((UNIT MDUALACC) (MACH fr400,fr550) (FR550-MAJOR M-4) (FR400-MAJOR M-2))
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((UNIT FMALL) (MACH fr400,fr550) (FR550-MAJOR M-4) (FR400-MAJOR M-2))
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(.str name "$pack $FRintieven,$FRintjeven,$" res)
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(+ pack res op FRintieven ope FRintjeven)
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(media-quad-multiply-cross-acc-semantics 1 mode conv addop rhw res
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@ -8110,7 +8108,7 @@
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name mode conv addop rhw res max min op ope comment)
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(dni name
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(comment)
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((UNIT MDUALACC) (MACH fr400,fr550) (FR550-MAJOR M-4) (FR400-MAJOR M-2))
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((UNIT FMALL) (MACH fr400,fr550) (FR550-MAJOR M-4) (FR400-MAJOR M-2))
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(.str name "$pack $FRintieven,$FRintjeven,$" res)
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(+ pack res op FRintieven ope FRintjeven)
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(media-quad-cross-multiply-cross-acc-semantics 1 mode conv addop rhw res
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@ -8160,7 +8158,7 @@
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name mode conv addop rhw res max min op ope comment)
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(dni name
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(comment)
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((UNIT MDUALACC) (MACH fr400,fr550) (FR550-MAJOR M-4) (FR400-MAJOR M-2))
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((UNIT FMALL) (MACH fr400,fr550) (FR550-MAJOR M-4) (FR400-MAJOR M-2))
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(.str name "$pack $FRintieven,$FRintjeven,$" res)
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(+ pack res op FRintieven ope FRintjeven)
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(media-quad-cross-multiply-acc-semantics 1 mode conv addop rhw res
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@ -499,6 +499,8 @@ fr400_check_insn_major_constraints (
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case FR400_MAJOR_M_2:
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return ! find_major_in_vliw (vliw, FR400_MAJOR_M_1)
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&& ! find_major_in_vliw (vliw, FR400_MAJOR_M_2);
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case FR400_MAJOR_M_1:
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return !find_major_in_vliw (vliw, FR400_MAJOR_M_2);
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default:
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break;
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}
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@ -1,3 +1,7 @@
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2004-03-01 Richard Sandiford <rsandifo@redhat.com>
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* frv-desc.c, frv-opc.c: Regenerate.
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2004-03-01 Richard Sandiford <rsandifo@redhat.com>
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* frv-desc.c, frv-opc.c, frv-opc.h: Regenerate.
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@ -2433,7 +2433,7 @@ static const CGEN_IBASE frv_cgen_insn_table[MAX_INSNS] =
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/* scutss$pack $GRj,$GRk */
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{
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FRV_INSN_SCUTSS, "scutss", "scutss", 32,
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{ 0, { (1<<MACH_FR400), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_NONE, FR550_MAJOR_NONE } }
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{ 0, { (1<<MACH_FR400), UNIT_I0, FR400_MAJOR_I_1, FR500_MAJOR_NONE, FR550_MAJOR_NONE } }
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},
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/* scan$pack $GRi,$GRj,$GRk */
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{
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@ -4128,7 +4128,7 @@ static const CGEN_IBASE frv_cgen_insn_table[MAX_INSNS] =
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/* calll$pack @($GRi,$GRj) */
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{
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FRV_INSN_CALLL, "calll", "calll", 32,
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{ 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR500_MAJOR_I_5, FR550_MAJOR_NONE } }
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{ 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR500_MAJOR_I_5, FR550_MAJOR_I_6 } }
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},
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/* jmpil$pack @($GRi,$s12) */
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{
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@ -4138,7 +4138,7 @@ static const CGEN_IBASE frv_cgen_insn_table[MAX_INSNS] =
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/* callil$pack @($GRi,$s12) */
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{
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FRV_INSN_CALLIL, "callil", "callil", 32,
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{ 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR500_MAJOR_I_5, FR550_MAJOR_NONE } }
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{ 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR500_MAJOR_I_5, FR550_MAJOR_I_6 } }
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},
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/* call$pack $label24 */
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{
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@ -4863,7 +4863,7 @@ static const CGEN_IBASE frv_cgen_insn_table[MAX_INSNS] =
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/* ccalll$pack @($GRi,$GRj),$CCi,$cond */
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{
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FRV_INSN_CCALLL, "ccalll", "ccalll", 32,
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{ 0|A(CONDITIONAL)|A(COND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR500_MAJOR_I_5, FR550_MAJOR_NONE } }
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{ 0|A(CONDITIONAL)|A(COND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR500_MAJOR_I_5, FR550_MAJOR_I_6 } }
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},
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/* ici$pack @($GRi,$GRj) */
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{
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@ -5578,7 +5578,7 @@ static const CGEN_IBASE frv_cgen_insn_table[MAX_INSNS] =
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/* mqsaths$pack $FRintieven,$FRintjeven,$FRintkeven */
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{
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FRV_INSN_MQSATHS, "mqsaths", "mqsaths", 32,
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{ 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_NONE, FR550_MAJOR_M_2 } }
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{ 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_NONE, FR550_MAJOR_M_2 } }
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},
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/* msathu$pack $FRinti,$FRintj,$FRintk */
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{
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@ -5823,17 +5823,17 @@ static const CGEN_IBASE frv_cgen_insn_table[MAX_INSNS] =
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/* mqxmachs$pack $FRintieven,$FRintjeven,$ACC40Sk */
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{
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FRV_INSN_MQXMACHS, "mqxmachs", "mqxmachs", 32,
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{ 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_MDUALACC, FR400_MAJOR_M_2, FR500_MAJOR_NONE, FR550_MAJOR_M_4 } }
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{ 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_NONE, FR550_MAJOR_M_4 } }
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},
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/* mqxmacxhs$pack $FRintieven,$FRintjeven,$ACC40Sk */
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{
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FRV_INSN_MQXMACXHS, "mqxmacxhs", "mqxmacxhs", 32,
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{ 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_MDUALACC, FR400_MAJOR_M_2, FR500_MAJOR_NONE, FR550_MAJOR_M_4 } }
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{ 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_NONE, FR550_MAJOR_M_4 } }
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},
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/* mqmacxhs$pack $FRintieven,$FRintjeven,$ACC40Sk */
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{
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FRV_INSN_MQMACXHS, "mqmacxhs", "mqmacxhs", 32,
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{ 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_MDUALACC, FR400_MAJOR_M_2, FR500_MAJOR_NONE, FR550_MAJOR_M_4 } }
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{ 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_NONE, FR550_MAJOR_M_4 } }
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},
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/* mcpxrs$pack $FRinti,$FRintj,$ACC40Sk */
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{
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|
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@ -453,6 +453,8 @@ fr400_check_insn_major_constraints (
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case FR400_MAJOR_M_2:
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return ! find_major_in_vliw (vliw, FR400_MAJOR_M_1)
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&& ! find_major_in_vliw (vliw, FR400_MAJOR_M_2);
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case FR400_MAJOR_M_1:
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return !find_major_in_vliw (vliw, FR400_MAJOR_M_2);
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default:
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break;
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}
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|
|
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@ -1,3 +1,14 @@
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2004-03-01 Richard Sandiford <rsandifo@redhat.com>
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* cache.c (frv_cache_init): Change fr400 cache statistics to match
|
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the fr405.
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(non_cache_access): Add missing breaks.
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* interrupts.c (set_exception_status_registers): Always set EAR15
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for data_access_errors.
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* memory.c (fr400_check_write_address): Remove redundant alignment
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check.
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* model.c: Regenerate.
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2004-03-01 Richard Sandiford <rsandifo@redhat.com>
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* frv.c (frvbf_iacc_cut): Rework, taking rounding into account.
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|
|
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@ -39,7 +39,7 @@ frv_cache_init (SIM_CPU *cpu, FRV_CACHE *cache)
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{
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case bfd_mach_fr400:
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if (cache->configured_sets == 0)
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cache->configured_sets = 128;
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cache->configured_sets = 512;
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if (cache->configured_ways == 0)
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cache->configured_ways = 2;
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if (cache->line_size == 0)
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@ -208,6 +208,7 @@ non_cache_access (FRV_CACHE *cache, USI address)
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if (address >= 0xff000000
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|| address >= 0xfe000000 && address <= 0xfeffffff)
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return 1; /* non-cache access */
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break;
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case bfd_mach_fr550:
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if (address >= 0xff000000
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|| address >= 0xfeff0000 && address <= 0xfeffffff)
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@ -219,6 +220,7 @@ non_cache_access (FRV_CACHE *cache, USI address)
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}
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else if (address >= 0xfe400000 && address <= 0xfe407fff)
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return 1; /* non-cache access */
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break;
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default:
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if (address >= 0xff000000
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|| address >= 0xfeff0000 && address <= 0xfeffffff)
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|
@ -230,6 +232,7 @@ non_cache_access (FRV_CACHE *cache, USI address)
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}
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else if (address >= 0xfe400000 && address <= 0xfe403fff)
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return 1; /* non-cache access */
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break;
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||||
}
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||||
hsr0 = GET_HSR0 ();
|
||||
|
|
|
@ -845,8 +845,7 @@ set_exception_status_registers (
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|||
break;
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||||
case FRV_DATA_ACCESS_ERROR:
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reg_index = 15; /* Use ESR15, EPCR15. */
|
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if (STATE_ARCHITECTURE (sd)->mach != bfd_mach_fr400)
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set_ear = 1;
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set_ear = 1;
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break;
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case FRV_DATA_ACCESS_EXCEPTION:
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set_daec = 1;
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||||
|
|
|
@ -679,18 +679,6 @@ frvbf_read_imem_USI (SIM_CPU *current_cpu, PCADDR vpc)
|
|||
static SI
|
||||
fr400_check_write_address (SIM_CPU *current_cpu, SI address, int align_mask)
|
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{
|
||||
if (address & align_mask)
|
||||
{
|
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/* On the fr400, this causes a data_access_error. */
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||||
/* Make sure that this exception is not masked. */
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USI isr = GET_ISR ();
|
||||
if (! GET_ISR_EMAM (isr))
|
||||
{
|
||||
/* Bad alignment causes a data_access_error on fr400. */
|
||||
frv_queue_data_access_error_interrupt (current_cpu, address);
|
||||
}
|
||||
address &= ~align_mask;
|
||||
}
|
||||
if (align_mask == 7
|
||||
&& address >= 0xfe800000 && address <= 0xfeffffff)
|
||||
frv_queue_program_interrupt (current_cpu, FRV_DATA_STORE_ERROR);
|
||||
|
|
|
@ -20263,7 +20263,16 @@ model_fr550_calll (SIM_CPU *current_cpu, void *sem_arg)
|
|||
{
|
||||
int referenced = 0;
|
||||
int UNUSED insn_referenced = abuf->written;
|
||||
cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
|
||||
INT in_GRi = -1;
|
||||
INT in_GRj = -1;
|
||||
INT in_ICCi_2 = -1;
|
||||
INT in_FCCi_2 = -1;
|
||||
in_GRi = FLD (in_GRi);
|
||||
in_GRj = FLD (in_GRj);
|
||||
referenced |= 1 << 0;
|
||||
referenced |= 1 << 1;
|
||||
referenced |= 1 << 4;
|
||||
cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
|
||||
}
|
||||
return cycles;
|
||||
#undef FLD
|
||||
|
@ -20302,7 +20311,14 @@ model_fr550_callil (SIM_CPU *current_cpu, void *sem_arg)
|
|||
{
|
||||
int referenced = 0;
|
||||
int UNUSED insn_referenced = abuf->written;
|
||||
cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
|
||||
INT in_GRi = -1;
|
||||
INT in_GRj = -1;
|
||||
INT in_ICCi_2 = -1;
|
||||
INT in_FCCi_2 = -1;
|
||||
in_GRi = FLD (in_GRi);
|
||||
referenced |= 1 << 0;
|
||||
referenced |= 1 << 4;
|
||||
cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
|
||||
}
|
||||
return cycles;
|
||||
#undef FLD
|
||||
|
@ -23424,7 +23440,16 @@ model_fr550_ccalll (SIM_CPU *current_cpu, void *sem_arg)
|
|||
{
|
||||
int referenced = 0;
|
||||
int UNUSED insn_referenced = abuf->written;
|
||||
cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
|
||||
INT in_GRi = -1;
|
||||
INT in_GRj = -1;
|
||||
INT in_ICCi_2 = -1;
|
||||
INT in_FCCi_2 = -1;
|
||||
in_GRi = FLD (in_GRi);
|
||||
in_GRj = FLD (in_GRj);
|
||||
if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
|
||||
if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
|
||||
if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
|
||||
cycles += frvbf_model_fr550_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
|
||||
}
|
||||
return cycles;
|
||||
#undef FLD
|
||||
|
@ -57775,17 +57800,7 @@ model_fr400_nsdiv (SIM_CPU *current_cpu, void *sem_arg)
|
|||
{
|
||||
int referenced = 0;
|
||||
int UNUSED insn_referenced = abuf->written;
|
||||
INT in_GRi = -1;
|
||||
INT in_GRj = -1;
|
||||
INT out_GRk = -1;
|
||||
INT out_ICCi_1 = -1;
|
||||
in_GRi = FLD (in_GRi);
|
||||
in_GRj = FLD (in_GRj);
|
||||
out_GRk = FLD (out_GRk);
|
||||
referenced |= 1 << 0;
|
||||
referenced |= 1 << 1;
|
||||
referenced |= 1 << 2;
|
||||
cycles += frvbf_model_fr400_u_idiv (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
|
||||
cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
|
||||
}
|
||||
return cycles;
|
||||
#undef FLD
|
||||
|
@ -57827,17 +57842,7 @@ model_fr400_nudiv (SIM_CPU *current_cpu, void *sem_arg)
|
|||
{
|
||||
int referenced = 0;
|
||||
int UNUSED insn_referenced = abuf->written;
|
||||
INT in_GRi = -1;
|
||||
INT in_GRj = -1;
|
||||
INT out_GRk = -1;
|
||||
INT out_ICCi_1 = -1;
|
||||
in_GRi = FLD (in_GRi);
|
||||
in_GRj = FLD (in_GRj);
|
||||
out_GRk = FLD (out_GRk);
|
||||
referenced |= 1 << 0;
|
||||
referenced |= 1 << 1;
|
||||
referenced |= 1 << 2;
|
||||
cycles += frvbf_model_fr400_u_idiv (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
|
||||
cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
|
||||
}
|
||||
return cycles;
|
||||
#undef FLD
|
||||
|
@ -59267,15 +59272,7 @@ model_fr400_nsdivi (SIM_CPU *current_cpu, void *sem_arg)
|
|||
{
|
||||
int referenced = 0;
|
||||
int UNUSED insn_referenced = abuf->written;
|
||||
INT in_GRi = -1;
|
||||
INT in_GRj = -1;
|
||||
INT out_GRk = -1;
|
||||
INT out_ICCi_1 = -1;
|
||||
in_GRi = FLD (in_GRi);
|
||||
out_GRk = FLD (out_GRk);
|
||||
referenced |= 1 << 0;
|
||||
referenced |= 1 << 2;
|
||||
cycles += frvbf_model_fr400_u_idiv (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
|
||||
cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
|
||||
}
|
||||
return cycles;
|
||||
#undef FLD
|
||||
|
@ -59315,15 +59312,7 @@ model_fr400_nudivi (SIM_CPU *current_cpu, void *sem_arg)
|
|||
{
|
||||
int referenced = 0;
|
||||
int UNUSED insn_referenced = abuf->written;
|
||||
INT in_GRi = -1;
|
||||
INT in_GRj = -1;
|
||||
INT out_GRk = -1;
|
||||
INT out_ICCi_1 = -1;
|
||||
in_GRi = FLD (in_GRi);
|
||||
out_GRk = FLD (out_GRk);
|
||||
referenced |= 1 << 0;
|
||||
referenced |= 1 << 2;
|
||||
cycles += frvbf_model_fr400_u_idiv (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
|
||||
cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
|
||||
}
|
||||
return cycles;
|
||||
#undef FLD
|
||||
|
@ -86433,9 +86422,9 @@ static const INSN_TIMING fr550_timing[] = {
|
|||
{ FRVBF_INSN_FCBULR, model_fr550_fcbulr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
|
||||
{ FRVBF_INSN_FCBOLR, model_fr550_fcbolr, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
|
||||
{ FRVBF_INSN_JMPL, model_fr550_jmpl, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
|
||||
{ FRVBF_INSN_CALLL, model_fr550_calll, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
|
||||
{ FRVBF_INSN_CALLL, model_fr550_calll, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
|
||||
{ FRVBF_INSN_JMPIL, model_fr550_jmpil, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
|
||||
{ FRVBF_INSN_CALLIL, model_fr550_callil, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
|
||||
{ FRVBF_INSN_CALLIL, model_fr550_callil, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
|
||||
{ FRVBF_INSN_CALL, model_fr550_call, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
|
||||
{ FRVBF_INSN_RETT, model_fr550_rett, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
|
||||
{ FRVBF_INSN_REI, model_fr550_rei, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
|
||||
|
@ -86580,7 +86569,7 @@ static const INSN_TIMING fr550_timing[] = {
|
|||
{ FRVBF_INSN_CFCKU, model_fr550_cfcku, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } },
|
||||
{ FRVBF_INSN_CFCKO, model_fr550_cfcko, { { (int) UNIT_FR550_U_CHECK, 1, 1 } } },
|
||||
{ FRVBF_INSN_CJMPL, model_fr550_cjmpl, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
|
||||
{ FRVBF_INSN_CCALLL, model_fr550_ccalll, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
|
||||
{ FRVBF_INSN_CCALLL, model_fr550_ccalll, { { (int) UNIT_FR550_U_BRANCH, 1, 1 } } },
|
||||
{ FRVBF_INSN_ICI, model_fr550_ici, { { (int) UNIT_FR550_U_ICI, 1, 1 } } },
|
||||
{ FRVBF_INSN_DCI, model_fr550_dci, { { (int) UNIT_FR550_U_DCI, 1, 1 } } },
|
||||
{ FRVBF_INSN_ICEI, model_fr550_icei, { { (int) UNIT_FR550_U_ICI, 1, 1 } } },
|
||||
|
@ -88323,9 +88312,9 @@ static const INSN_TIMING fr400_timing[] = {
|
|||
{ FRVBF_INSN_XOR, model_fr400_xor, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } },
|
||||
{ FRVBF_INSN_NOT, model_fr400_not, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } },
|
||||
{ FRVBF_INSN_SDIV, model_fr400_sdiv, { { (int) UNIT_FR400_U_IDIV, 1, 1 } } },
|
||||
{ FRVBF_INSN_NSDIV, model_fr400_nsdiv, { { (int) UNIT_FR400_U_IDIV, 1, 1 } } },
|
||||
{ FRVBF_INSN_NSDIV, model_fr400_nsdiv, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
|
||||
{ FRVBF_INSN_UDIV, model_fr400_udiv, { { (int) UNIT_FR400_U_IDIV, 1, 1 } } },
|
||||
{ FRVBF_INSN_NUDIV, model_fr400_nudiv, { { (int) UNIT_FR400_U_IDIV, 1, 1 } } },
|
||||
{ FRVBF_INSN_NUDIV, model_fr400_nudiv, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
|
||||
{ FRVBF_INSN_SMUL, model_fr400_smul, { { (int) UNIT_FR400_U_IMUL, 1, 1 } } },
|
||||
{ FRVBF_INSN_UMUL, model_fr400_umul, { { (int) UNIT_FR400_U_IMUL, 1, 1 } } },
|
||||
{ FRVBF_INSN_SMU, model_fr400_smu, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } },
|
||||
|
@ -88381,9 +88370,9 @@ static const INSN_TIMING fr400_timing[] = {
|
|||
{ FRVBF_INSN_ORI, model_fr400_ori, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } },
|
||||
{ FRVBF_INSN_XORI, model_fr400_xori, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } },
|
||||
{ FRVBF_INSN_SDIVI, model_fr400_sdivi, { { (int) UNIT_FR400_U_IDIV, 1, 1 } } },
|
||||
{ FRVBF_INSN_NSDIVI, model_fr400_nsdivi, { { (int) UNIT_FR400_U_IDIV, 1, 1 } } },
|
||||
{ FRVBF_INSN_NSDIVI, model_fr400_nsdivi, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
|
||||
{ FRVBF_INSN_UDIVI, model_fr400_udivi, { { (int) UNIT_FR400_U_IDIV, 1, 1 } } },
|
||||
{ FRVBF_INSN_NUDIVI, model_fr400_nudivi, { { (int) UNIT_FR400_U_IDIV, 1, 1 } } },
|
||||
{ FRVBF_INSN_NUDIVI, model_fr400_nudivi, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
|
||||
{ FRVBF_INSN_SMULI, model_fr400_smuli, { { (int) UNIT_FR400_U_IMUL, 1, 1 } } },
|
||||
{ FRVBF_INSN_UMULI, model_fr400_umuli, { { (int) UNIT_FR400_U_IMUL, 1, 1 } } },
|
||||
{ FRVBF_INSN_SLLI, model_fr400_slli, { { (int) UNIT_FR400_U_INTEGER, 1, 1 } } },
|
||||
|
|
Loading…
Reference in a new issue