gdb: ARM: Add support for thumb32 instructions recording
gdb/ChangeLog: 2014-01-15 Omair Javaid <omair.javaid@linaro.org> * arm-tdep.c (enum arm_record_result): New enum. (arm_record_unsupported_insn): New function. (arm_record_coproc_data_proc): Removed. (thumb2_record_ld_st_multiple): New function. (thumb2_record_ld_st_dual_ex_tbb): New function. (thumb2_record_data_proc_sreg_mimm): New function. (thumb2_record_ps_dest_generic): New function. (thumb2_record_branch_misc_cntrl): New function. (thumb2_record_str_single_data): New function. (thumb2_record_ld_mem_hints): New function. (thumb2_record_ld_word): New function. (thumb2_record_lmul_lmla_div): New function. (thumb2_record_decode_insn_handler): New function. (decode_insn): Add thumb32 instruction handlers.
This commit is contained in:
Omair Javaid
Will Newton
parent
97dfe20617
commit
c6ec2b3055
2 changed files with 614 additions and 7 deletions
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@ -1,3 +1,20 @@
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2014-01-15 Omair Javaid <omair.javaid@linaro.org>
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* arm-tdep.c (enum arm_record_result): New enum.
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(arm_record_unsupported_insn): New function.
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(arm_record_coproc_data_proc): Removed.
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(thumb2_record_ld_st_multiple): New function.
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(thumb2_record_ld_st_dual_ex_tbb): New function.
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(thumb2_record_data_proc_sreg_mimm): New function.
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(thumb2_record_ps_dest_generic): New function.
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(thumb2_record_branch_misc_cntrl): New function.
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(thumb2_record_str_single_data): New function.
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(thumb2_record_ld_mem_hints): New function.
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(thumb2_record_ld_word): New function.
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(thumb2_record_lmul_lmla_div): New function.
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(thumb2_record_decode_insn_handler): New function.
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(decode_insn): Add thumb32 instruction handlers.
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2014-01-15 Omair Javaid <omair.javaid@linaro.org>
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* arm-linux-tdep.c: Include "record-full.h" and "linux-record.h".
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604
gdb/arm-tdep.c
604
gdb/arm-tdep.c
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@ -10658,6 +10658,12 @@ sbo_sbz (uint32_t insn, uint32_t bit_num, uint32_t len, uint32_t sbo)
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return 1;
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}
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enum arm_record_result
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{
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ARM_RECORD_SUCCESS = 0,
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ARM_RECORD_FAILURE = 1
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};
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typedef enum
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{
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ARM_RECORD_STRH=1,
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@ -11900,7 +11906,7 @@ arm_record_b_bl (insn_decode_record *arm_insn_r)
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/* Handling opcode 110 insns. */
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static int
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arm_record_coproc (insn_decode_record *arm_insn_r)
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arm_record_unsupported_insn (insn_decode_record *arm_insn_r)
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{
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printf_unfiltered (_("Process record does not support instruction "
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"0x%0x at address %s.\n"),arm_insn_r->arm_insn,
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@ -12393,6 +12399,581 @@ thumb_record_branch (insn_decode_record *thumb_insn_r)
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return 0;
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}
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/* Handler for thumb2 load/store multiple instructions. */
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static int
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thumb2_record_ld_st_multiple (insn_decode_record *thumb2_insn_r)
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{
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struct regcache *reg_cache = thumb2_insn_r->regcache;
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uint32_t reg_rn, op;
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uint32_t register_bits = 0, register_count = 0;
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uint32_t index = 0, start_address = 0;
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uint32_t record_buf[24], record_buf_mem[48];
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ULONGEST u_regval = 0;
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reg_rn = bits (thumb2_insn_r->arm_insn, 16, 19);
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op = bits (thumb2_insn_r->arm_insn, 23, 24);
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if (0 == op || 3 == op)
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{
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if (bit (thumb2_insn_r->arm_insn, INSN_S_L_BIT_NUM))
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{
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/* Handle RFE instruction. */
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record_buf[0] = ARM_PS_REGNUM;
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thumb2_insn_r->reg_rec_count = 1;
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}
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else
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{
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/* Handle SRS instruction after reading banked SP. */
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return arm_record_unsupported_insn (thumb2_insn_r);
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}
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}
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else if (1 == op || 2 == op)
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{
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if (bit (thumb2_insn_r->arm_insn, INSN_S_L_BIT_NUM))
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{
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/* Handle LDM/LDMIA/LDMFD and LDMDB/LDMEA instructions. */
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register_bits = bits (thumb2_insn_r->arm_insn, 0, 15);
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while (register_bits)
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{
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if (register_bits & 0x00000001)
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record_buf[index++] = register_count;
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register_count++;
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register_bits = register_bits >> 1;
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}
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record_buf[index++] = reg_rn;
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record_buf[index++] = ARM_PS_REGNUM;
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thumb2_insn_r->reg_rec_count = index;
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}
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else
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{
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/* Handle STM/STMIA/STMEA and STMDB/STMFD. */
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register_bits = bits (thumb2_insn_r->arm_insn, 0, 15);
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regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval);
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while (register_bits)
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{
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if (register_bits & 0x00000001)
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register_count++;
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register_bits = register_bits >> 1;
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}
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if (1 == op)
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{
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/* Start address calculation for LDMDB/LDMEA. */
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start_address = u_regval;
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}
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else if (2 == op)
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{
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/* Start address calculation for LDMDB/LDMEA. */
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start_address = u_regval - register_count * 4;
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}
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thumb2_insn_r->mem_rec_count = register_count;
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while (register_count)
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{
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record_buf_mem[register_count * 2 - 1] = start_address;
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record_buf_mem[register_count * 2 - 2] = 4;
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start_address = start_address + 4;
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register_count--;
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}
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record_buf[0] = reg_rn;
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record_buf[1] = ARM_PS_REGNUM;
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thumb2_insn_r->reg_rec_count = 2;
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}
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}
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MEM_ALLOC (thumb2_insn_r->arm_mems, thumb2_insn_r->mem_rec_count,
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record_buf_mem);
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REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
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record_buf);
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return ARM_RECORD_SUCCESS;
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}
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/* Handler for thumb2 load/store (dual/exclusive) and table branch
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instructions. */
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static int
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thumb2_record_ld_st_dual_ex_tbb (insn_decode_record *thumb2_insn_r)
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{
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struct regcache *reg_cache = thumb2_insn_r->regcache;
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uint32_t reg_rd, reg_rn, offset_imm;
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uint32_t reg_dest1, reg_dest2;
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uint32_t address, offset_addr;
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uint32_t record_buf[8], record_buf_mem[8];
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uint32_t op1, op2, op3;
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LONGEST s_word;
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ULONGEST u_regval[2];
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op1 = bits (thumb2_insn_r->arm_insn, 23, 24);
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op2 = bits (thumb2_insn_r->arm_insn, 20, 21);
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op3 = bits (thumb2_insn_r->arm_insn, 4, 7);
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if (bit (thumb2_insn_r->arm_insn, INSN_S_L_BIT_NUM))
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{
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if(!(1 == op1 && 1 == op2 && (0 == op3 || 1 == op3)))
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{
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reg_dest1 = bits (thumb2_insn_r->arm_insn, 12, 15);
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record_buf[0] = reg_dest1;
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record_buf[1] = ARM_PS_REGNUM;
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thumb2_insn_r->reg_rec_count = 2;
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}
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if (3 == op2 || (op1 & 2) || (1 == op1 && 1 == op2 && 7 == op3))
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{
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reg_dest2 = bits (thumb2_insn_r->arm_insn, 8, 11);
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record_buf[2] = reg_dest2;
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thumb2_insn_r->reg_rec_count = 3;
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}
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}
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else
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{
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reg_rn = bits (thumb2_insn_r->arm_insn, 16, 19);
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regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval[0]);
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if (0 == op1 && 0 == op2)
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{
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/* Handle STREX. */
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offset_imm = bits (thumb2_insn_r->arm_insn, 0, 7);
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address = u_regval[0] + (offset_imm * 4);
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record_buf_mem[0] = 4;
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record_buf_mem[1] = address;
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thumb2_insn_r->mem_rec_count = 1;
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reg_rd = bits (thumb2_insn_r->arm_insn, 0, 3);
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record_buf[0] = reg_rd;
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thumb2_insn_r->reg_rec_count = 1;
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}
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else if (1 == op1 && 0 == op2)
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{
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reg_rd = bits (thumb2_insn_r->arm_insn, 0, 3);
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record_buf[0] = reg_rd;
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thumb2_insn_r->reg_rec_count = 1;
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address = u_regval[0];
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record_buf_mem[1] = address;
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if (4 == op3)
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{
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/* Handle STREXB. */
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record_buf_mem[0] = 1;
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thumb2_insn_r->mem_rec_count = 1;
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}
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else if (5 == op3)
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{
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/* Handle STREXH. */
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record_buf_mem[0] = 2 ;
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thumb2_insn_r->mem_rec_count = 1;
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}
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else if (7 == op3)
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{
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/* Handle STREXD. */
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address = u_regval[0];
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record_buf_mem[0] = 4;
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record_buf_mem[2] = 4;
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record_buf_mem[3] = address + 4;
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thumb2_insn_r->mem_rec_count = 2;
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}
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}
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else
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{
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offset_imm = bits (thumb2_insn_r->arm_insn, 0, 7);
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if (bit (thumb2_insn_r->arm_insn, 24))
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{
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if (bit (thumb2_insn_r->arm_insn, 23))
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offset_addr = u_regval[0] + (offset_imm * 4);
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else
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offset_addr = u_regval[0] - (offset_imm * 4);
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address = offset_addr;
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}
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else
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address = u_regval[0];
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record_buf_mem[0] = 4;
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record_buf_mem[1] = address;
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record_buf_mem[2] = 4;
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record_buf_mem[3] = address + 4;
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thumb2_insn_r->mem_rec_count = 2;
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record_buf[0] = reg_rn;
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thumb2_insn_r->reg_rec_count = 1;
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}
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}
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REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
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record_buf);
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MEM_ALLOC (thumb2_insn_r->arm_mems, thumb2_insn_r->mem_rec_count,
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record_buf_mem);
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return ARM_RECORD_SUCCESS;
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}
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/* Handler for thumb2 data processing (shift register and modified immediate)
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instructions. */
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static int
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thumb2_record_data_proc_sreg_mimm (insn_decode_record *thumb2_insn_r)
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{
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uint32_t reg_rd, op;
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uint32_t record_buf[8];
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op = bits (thumb2_insn_r->arm_insn, 21, 24);
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reg_rd = bits (thumb2_insn_r->arm_insn, 8, 11);
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if ((0 == op || 4 == op || 8 == op || 13 == op) && 15 == reg_rd)
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{
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record_buf[0] = ARM_PS_REGNUM;
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thumb2_insn_r->reg_rec_count = 1;
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}
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else
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{
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record_buf[0] = reg_rd;
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record_buf[1] = ARM_PS_REGNUM;
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thumb2_insn_r->reg_rec_count = 2;
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}
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REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
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record_buf);
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return ARM_RECORD_SUCCESS;
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}
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/* Generic handler for thumb2 instructions which effect destination and PS
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registers. */
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static int
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thumb2_record_ps_dest_generic (insn_decode_record *thumb2_insn_r)
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{
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uint32_t reg_rd;
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uint32_t record_buf[8];
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reg_rd = bits (thumb2_insn_r->arm_insn, 8, 11);
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record_buf[0] = reg_rd;
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record_buf[1] = ARM_PS_REGNUM;
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thumb2_insn_r->reg_rec_count = 2;
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REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
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record_buf);
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return ARM_RECORD_SUCCESS;
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}
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/* Handler for thumb2 branch and miscellaneous control instructions. */
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static int
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thumb2_record_branch_misc_cntrl (insn_decode_record *thumb2_insn_r)
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{
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uint32_t op, op1, op2;
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uint32_t record_buf[8];
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op = bits (thumb2_insn_r->arm_insn, 20, 26);
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op1 = bits (thumb2_insn_r->arm_insn, 12, 14);
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op2 = bits (thumb2_insn_r->arm_insn, 8, 11);
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/* Handle MSR insn. */
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if (!(op1 & 0x2) && 0x38 == op)
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{
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if (!(op2 & 0x3))
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{
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/* CPSR is going to be changed. */
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record_buf[0] = ARM_PS_REGNUM;
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thumb2_insn_r->reg_rec_count = 1;
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}
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else
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{
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arm_record_unsupported_insn(thumb2_insn_r);
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return -1;
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}
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}
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else if (4 == (op1 & 0x5) || 5 == (op1 & 0x5))
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{
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/* BLX. */
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record_buf[0] = ARM_PS_REGNUM;
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record_buf[1] = ARM_LR_REGNUM;
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thumb2_insn_r->reg_rec_count = 2;
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}
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REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
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record_buf);
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return ARM_RECORD_SUCCESS;
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}
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/* Handler for thumb2 store single data item instructions. */
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static int
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thumb2_record_str_single_data (insn_decode_record *thumb2_insn_r)
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{
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struct regcache *reg_cache = thumb2_insn_r->regcache;
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uint32_t reg_rn, reg_rm, offset_imm, shift_imm;
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uint32_t address, offset_addr;
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uint32_t record_buf[8], record_buf_mem[8];
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uint32_t op1, op2;
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ULONGEST u_regval[2];
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op1 = bits (thumb2_insn_r->arm_insn, 21, 23);
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op2 = bits (thumb2_insn_r->arm_insn, 6, 11);
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reg_rn = bits (thumb2_insn_r->arm_insn, 16, 19);
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regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval[0]);
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if (bit (thumb2_insn_r->arm_insn, 23))
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{
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/* T2 encoding. */
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offset_imm = bits (thumb2_insn_r->arm_insn, 0, 11);
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offset_addr = u_regval[0] + offset_imm;
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address = offset_addr;
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}
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else
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{
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/* T3 encoding. */
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if ((0 == op1 || 1 == op1 || 2 == op1) && !(op2 & 0x20))
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{
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/* Handle STRB (register). */
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reg_rm = bits (thumb2_insn_r->arm_insn, 0, 3);
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regcache_raw_read_unsigned (reg_cache, reg_rm, &u_regval[1]);
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shift_imm = bits (thumb2_insn_r->arm_insn, 4, 5);
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offset_addr = u_regval[1] << shift_imm;
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address = u_regval[0] + offset_addr;
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}
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else
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{
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offset_imm = bits (thumb2_insn_r->arm_insn, 0, 7);
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if (bit (thumb2_insn_r->arm_insn, 10))
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{
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if (bit (thumb2_insn_r->arm_insn, 9))
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offset_addr = u_regval[0] + offset_imm;
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else
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offset_addr = u_regval[0] - offset_imm;
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address = offset_addr;
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}
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else
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address = u_regval[0];
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}
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}
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switch (op1)
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{
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/* Store byte instructions. */
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case 4:
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case 0:
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record_buf_mem[0] = 1;
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break;
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/* Store half word instructions. */
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case 1:
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case 5:
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record_buf_mem[0] = 2;
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break;
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/* Store word instructions. */
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case 2:
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case 6:
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record_buf_mem[0] = 4;
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break;
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default:
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gdb_assert_not_reached ("no decoding pattern found");
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break;
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}
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record_buf_mem[1] = address;
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thumb2_insn_r->mem_rec_count = 1;
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record_buf[0] = reg_rn;
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||||
thumb2_insn_r->reg_rec_count = 1;
|
||||
|
||||
REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
|
||||
record_buf);
|
||||
MEM_ALLOC (thumb2_insn_r->arm_mems, thumb2_insn_r->mem_rec_count,
|
||||
record_buf_mem);
|
||||
return ARM_RECORD_SUCCESS;
|
||||
}
|
||||
|
||||
/* Handler for thumb2 load memory hints instructions. */
|
||||
|
||||
static int
|
||||
thumb2_record_ld_mem_hints (insn_decode_record *thumb2_insn_r)
|
||||
{
|
||||
uint32_t record_buf[8];
|
||||
uint32_t reg_rt, reg_rn;
|
||||
|
||||
reg_rt = bits (thumb2_insn_r->arm_insn, 12, 15);
|
||||
reg_rn = bits (thumb2_insn_r->arm_insn, 16, 19);
|
||||
|
||||
if (ARM_PC_REGNUM != reg_rt)
|
||||
{
|
||||
record_buf[0] = reg_rt;
|
||||
record_buf[1] = reg_rn;
|
||||
record_buf[2] = ARM_PS_REGNUM;
|
||||
thumb2_insn_r->reg_rec_count = 3;
|
||||
|
||||
REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
|
||||
record_buf);
|
||||
return ARM_RECORD_SUCCESS;
|
||||
}
|
||||
|
||||
return ARM_RECORD_FAILURE;
|
||||
}
|
||||
|
||||
/* Handler for thumb2 load word instructions. */
|
||||
|
||||
static int
|
||||
thumb2_record_ld_word (insn_decode_record *thumb2_insn_r)
|
||||
{
|
||||
uint32_t opcode1 = 0, opcode2 = 0;
|
||||
uint32_t record_buf[8];
|
||||
|
||||
record_buf[0] = bits (thumb2_insn_r->arm_insn, 12, 15);
|
||||
record_buf[1] = ARM_PS_REGNUM;
|
||||
thumb2_insn_r->reg_rec_count = 2;
|
||||
|
||||
REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
|
||||
record_buf);
|
||||
return ARM_RECORD_SUCCESS;
|
||||
}
|
||||
|
||||
/* Handler for thumb2 long multiply, long multiply accumulate, and
|
||||
divide instructions. */
|
||||
|
||||
static int
|
||||
thumb2_record_lmul_lmla_div (insn_decode_record *thumb2_insn_r)
|
||||
{
|
||||
uint32_t opcode1 = 0, opcode2 = 0;
|
||||
uint32_t record_buf[8];
|
||||
uint32_t reg_src1 = 0;
|
||||
|
||||
opcode1 = bits (thumb2_insn_r->arm_insn, 20, 22);
|
||||
opcode2 = bits (thumb2_insn_r->arm_insn, 4, 7);
|
||||
|
||||
if (0 == opcode1 || 2 == opcode1 || (opcode1 >= 4 && opcode1 <= 6))
|
||||
{
|
||||
/* Handle SMULL, UMULL, SMULAL. */
|
||||
/* Handle SMLAL(S), SMULL(S), UMLAL(S), UMULL(S). */
|
||||
record_buf[0] = bits (thumb2_insn_r->arm_insn, 16, 19);
|
||||
record_buf[1] = bits (thumb2_insn_r->arm_insn, 12, 15);
|
||||
record_buf[2] = ARM_PS_REGNUM;
|
||||
thumb2_insn_r->reg_rec_count = 3;
|
||||
}
|
||||
else if (1 == opcode1 || 3 == opcode2)
|
||||
{
|
||||
/* Handle SDIV and UDIV. */
|
||||
record_buf[0] = bits (thumb2_insn_r->arm_insn, 16, 19);
|
||||
record_buf[1] = bits (thumb2_insn_r->arm_insn, 12, 15);
|
||||
record_buf[2] = ARM_PS_REGNUM;
|
||||
thumb2_insn_r->reg_rec_count = 3;
|
||||
}
|
||||
else
|
||||
return ARM_RECORD_FAILURE;
|
||||
|
||||
REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count,
|
||||
record_buf);
|
||||
return ARM_RECORD_SUCCESS;
|
||||
}
|
||||
|
||||
/* Decodes thumb2 instruction type and invokes its record handler. */
|
||||
|
||||
static unsigned int
|
||||
thumb2_record_decode_insn_handler (insn_decode_record *thumb2_insn_r)
|
||||
{
|
||||
uint32_t op, op1, op2;
|
||||
|
||||
op = bit (thumb2_insn_r->arm_insn, 15);
|
||||
op1 = bits (thumb2_insn_r->arm_insn, 27, 28);
|
||||
op2 = bits (thumb2_insn_r->arm_insn, 20, 26);
|
||||
|
||||
if (op1 == 0x01)
|
||||
{
|
||||
if (!(op2 & 0x64 ))
|
||||
{
|
||||
/* Load/store multiple instruction. */
|
||||
return thumb2_record_ld_st_multiple (thumb2_insn_r);
|
||||
}
|
||||
else if (!((op2 & 0x64) ^ 0x04))
|
||||
{
|
||||
/* Load/store (dual/exclusive) and table branch instruction. */
|
||||
return thumb2_record_ld_st_dual_ex_tbb (thumb2_insn_r);
|
||||
}
|
||||
else if (!((op2 & 0x20) ^ 0x20))
|
||||
{
|
||||
/* Data-processing (shifted register). */
|
||||
return thumb2_record_data_proc_sreg_mimm (thumb2_insn_r);
|
||||
}
|
||||
else if (op2 & 0x40)
|
||||
{
|
||||
/* Co-processor instructions. */
|
||||
arm_record_unsupported_insn (thumb2_insn_r);
|
||||
}
|
||||
}
|
||||
else if (op1 == 0x02)
|
||||
{
|
||||
if (op)
|
||||
{
|
||||
/* Branches and miscellaneous control instructions. */
|
||||
return thumb2_record_branch_misc_cntrl (thumb2_insn_r);
|
||||
}
|
||||
else if (op2 & 0x20)
|
||||
{
|
||||
/* Data-processing (plain binary immediate) instruction. */
|
||||
return thumb2_record_ps_dest_generic (thumb2_insn_r);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Data-processing (modified immediate). */
|
||||
return thumb2_record_data_proc_sreg_mimm (thumb2_insn_r);
|
||||
}
|
||||
}
|
||||
else if (op1 == 0x03)
|
||||
{
|
||||
if (!(op2 & 0x71 ))
|
||||
{
|
||||
/* Store single data item. */
|
||||
return thumb2_record_str_single_data (thumb2_insn_r);
|
||||
}
|
||||
else if (!((op2 & 0x71) ^ 0x10))
|
||||
{
|
||||
/* Advanced SIMD or structure load/store instructions. */
|
||||
return arm_record_unsupported_insn (thumb2_insn_r);
|
||||
}
|
||||
else if (!((op2 & 0x67) ^ 0x01))
|
||||
{
|
||||
/* Load byte, memory hints instruction. */
|
||||
return thumb2_record_ld_mem_hints (thumb2_insn_r);
|
||||
}
|
||||
else if (!((op2 & 0x67) ^ 0x03))
|
||||
{
|
||||
/* Load halfword, memory hints instruction. */
|
||||
return thumb2_record_ld_mem_hints (thumb2_insn_r);
|
||||
}
|
||||
else if (!((op2 & 0x67) ^ 0x05))
|
||||
{
|
||||
/* Load word instruction. */
|
||||
return thumb2_record_ld_word (thumb2_insn_r);
|
||||
}
|
||||
else if (!((op2 & 0x70) ^ 0x20))
|
||||
{
|
||||
/* Data-processing (register) instruction. */
|
||||
return thumb2_record_ps_dest_generic (thumb2_insn_r);
|
||||
}
|
||||
else if (!((op2 & 0x78) ^ 0x30))
|
||||
{
|
||||
/* Multiply, multiply accumulate, abs diff instruction. */
|
||||
return thumb2_record_ps_dest_generic (thumb2_insn_r);
|
||||
}
|
||||
else if (!((op2 & 0x78) ^ 0x38))
|
||||
{
|
||||
/* Long multiply, long multiply accumulate, and divide. */
|
||||
return thumb2_record_lmul_lmla_div (thumb2_insn_r);
|
||||
}
|
||||
else if (op2 & 0x40)
|
||||
{
|
||||
/* Co-processor instructions. */
|
||||
return arm_record_unsupported_insn (thumb2_insn_r);
|
||||
}
|
||||
}
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* Extracts arm/thumb/thumb2 insn depending on the size, and returns 0 on success
|
||||
and positive val on fauilure. */
|
||||
|
|
@ -12431,7 +13012,7 @@ decode_insn (insn_decode_record *arm_record, record_type_t record_type,
|
|||
arm_record_ld_st_reg_offset, /* 011. */
|
||||
arm_record_ld_st_multiple, /* 100. */
|
||||
arm_record_b_bl, /* 101. */
|
||||
arm_record_coproc, /* 110. */
|
||||
arm_record_unsupported_insn, /* 110. */
|
||||
arm_record_coproc_data_proc /* 111. */
|
||||
};
|
||||
|
||||
|
|
@ -12482,11 +13063,20 @@ decode_insn (insn_decode_record *arm_record, record_type_t record_type,
|
|||
}
|
||||
else if (THUMB2_RECORD == record_type)
|
||||
{
|
||||
printf_unfiltered (_("Process record doesnt support thumb32 instruction "
|
||||
"0x%0x at address %s.\n"),arm_record->arm_insn,
|
||||
paddress (arm_record->gdbarch,
|
||||
arm_record->this_addr));
|
||||
ret = -1;
|
||||
/* As thumb does not have condition codes, we set negative. */
|
||||
arm_record->cond = -1;
|
||||
|
||||
/* Swap first half of 32bit thumb instruction with second half. */
|
||||
arm_record->arm_insn
|
||||
= (arm_record->arm_insn >> 16) | (arm_record->arm_insn << 16);
|
||||
|
||||
insn_id = thumb2_record_decode_insn_handler (arm_record);
|
||||
|
||||
if (insn_id != ARM_RECORD_SUCCESS)
|
||||
{
|
||||
arm_record_unsupported_insn (arm_record);
|
||||
ret = -1;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
|
|
|
|||
Loading…
Reference in a new issue