mostly whitespace/comment changes
This commit is contained in:
Ken Raeburn
parent
082e9570f1
commit
c5dd66a13a
2 changed files with 72 additions and 81 deletions
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@ -681,10 +681,10 @@ md_assemble (line)
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/* There may be operands to parse. */
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if (*l != END_OF_INSN &&
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/* For string instructions, we ignore any operands if given. This
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kludges, for example, 'rep/movsb %ds:(%esi), %es:(%edi)' where
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the operands are always going to be the same, and are not really
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encoded in machine code. */
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/* For string instructions, we ignore any operands if given. This
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kludges, for example, 'rep/movsb %ds:(%esi), %es:(%edi)' where
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the operands are always going to be the same, and are not really
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encoded in machine code. */
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!IS_STRING_INSTRUCTION (current_templates->
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start->base_opcode))
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{
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@ -778,10 +778,11 @@ md_assemble (line)
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}
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/* Now we've parsed the opcode into a set of templates, and have the
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operands at hand.
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Next, we find a template that matches the given insn,
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making sure the overlap of the given operands types is consistent
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with the template operand types. */
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operands at hand.
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Next, we find a template that matches the given insn,
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making sure the overlap of the given operands types is consistent
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with the template operand types. */
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#define MATCH(overlap,given_type) \
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(overlap && \
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@ -789,18 +790,18 @@ md_assemble (line)
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== (given_type & (JumpAbsolute|BaseIndex|Mem8)))
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/* If m0 and m1 are register matches they must be consistent
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with the expected operand types t0 and t1.
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That is, if both m0 & m1 are register matches
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i.e. ( ((m0 & (Reg)) && (m1 & (Reg)) ) ?
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then, either 1. or 2. must be true:
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1. the expected operand type register overlap is null:
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(t0 & t1 & Reg) == 0
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AND
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the given register overlap is null:
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(m0 & m1 & Reg) == 0
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2. the expected operand type register overlap == the given
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operand type overlap: (t0 & t1 & m0 & m1 & Reg).
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*/
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with the expected operand types t0 and t1.
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That is, if both m0 & m1 are register matches
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i.e. ( ((m0 & (Reg)) && (m1 & (Reg)) ) ?
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then, either 1. or 2. must be true:
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1. the expected operand type register overlap is null:
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(t0 & t1 & Reg) == 0
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AND
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the given register overlap is null:
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(m0 & m1 & Reg) == 0
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2. the expected operand type register overlap == the given
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operand type overlap: (t0 & t1 & m0 & m1 & Reg).
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*/
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#define CONSISTENT_REGISTER_MATCH(m0, m1, t0, t1) \
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( ((m0 & (Reg)) && (m1 & (Reg))) ? \
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( ((t0 & t1 & (Reg)) == 0 && (m0 & m1 & (Reg)) == 0) || \
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@ -875,7 +876,7 @@ md_assemble (line)
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continue;
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}
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/* found either forward/reverse 2 or 3 operand match here:
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slip through to break */
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slip through to break */
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}
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break; /* we've found a match; break out of loop */
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} /* for (t = ... */
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@ -890,12 +891,12 @@ md_assemble (line)
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t = &i.tm; /* alter new copy of template */
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/* If there's no opcode suffix we try to invent one based on register
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operands. */
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operands. */
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if (!i.suffix && i.reg_operands)
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{
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/* We take i.suffix from the LAST register operand specified. This
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assumes that the last register operands is the destination register
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operand. */
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assumes that the last register operands is the destination register
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operand. */
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int o;
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for (o = 0; o < MAX_OPERANDS; o++)
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if (i.types[o] & Reg)
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@ -907,8 +908,8 @@ md_assemble (line)
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}
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/* Make still unresolved immediate matches conform to size of immediate
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given in i.suffix. Note: overlap2 cannot be an immediate!
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We assume this. */
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given in i.suffix. Note: overlap2 cannot be an immediate!
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We assume this. */
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if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32))
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&& overlap0 != Imm8 && overlap0 != Imm8S
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&& overlap0 != Imm16 && overlap0 != Imm32)
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@ -956,8 +957,8 @@ md_assemble (line)
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}
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/* Finalize opcode. First, we change the opcode based on the operand
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size given by i.suffix: we never have to change things for byte insns,
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or when no opcode suffix is need to size the operands. */
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size given by i.suffix: we never have to change things for byte insns,
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or when no opcode suffix is need to size the operands. */
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if (!i.suffix && (t->opcode_modifier & W))
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{
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@ -988,28 +989,28 @@ md_assemble (line)
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if (i.operands)
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{
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/* If we found a reverse match we must alter the opcode direction bit
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found_reverse_match holds bit to set (different for int &
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float insns). */
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found_reverse_match holds bit to set (different for int &
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float insns). */
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if (found_reverse_match)
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{
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t->base_opcode |= found_reverse_match;
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}
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/*
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The imul $imm, %reg instruction is converted into
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imul $imm, %reg, %reg. */
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/* The imul $imm, %reg instruction is converted into
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imul $imm, %reg, %reg. */
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if (t->opcode_modifier & imulKludge)
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{
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i.regs[2] = i.regs[1]; /* Pretend we saw the 3 operand case. */
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/* Pretend we saw the 3 operand case. */
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i.regs[2] = i.regs[1];
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i.reg_operands = 2;
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}
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/* Certain instructions expect the destination to be in the i.rm.reg
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field. This is by far the exceptional case. For these instructions,
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if the source operand is a register, we must reverse the i.rm.reg
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and i.rm.regmem fields. We accomplish this by faking that the
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two register operands were given in the reverse order. */
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field. This is by far the exceptional case. For these
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instructions, if the source operand is a register, we must reverse
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the i.rm.reg and i.rm.regmem fields. We accomplish this by faking
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that the two register operands were given in the reverse order. */
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if ((t->opcode_modifier & ReverseRegRegmem) && i.reg_operands == 2)
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{
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unsigned int first_reg_operand = (i.types[0] & Reg) ? 0 : 1;
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@ -1046,30 +1047,31 @@ md_assemble (line)
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else if (t->opcode_modifier & Seg3ShortForm)
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{
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/* 'push %fs' is 0x0fa0; 'pop %fs' is 0x0fa1.
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'push %gs' is 0x0fa8; 'pop %fs' is 0x0fa9.
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So, only if i.regs[0]->reg_num == 5 (%gs) do we need
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to change the opcode. */
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'push %gs' is 0x0fa8; 'pop %fs' is 0x0fa9.
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So, only if i.regs[0]->reg_num == 5 (%gs) do we need
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to change the opcode. */
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if (i.regs[0]->reg_num == 5)
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t->base_opcode |= 0x08;
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}
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else if (t->opcode_modifier & Modrm)
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{
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/* The opcode is completed (modulo t->extension_opcode which must
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be put into the modrm byte.
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Now, we make the modrm & index base bytes based on all the info
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we've collected. */
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be put into the modrm byte.
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Now, we make the modrm & index base bytes based on all the info
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we've collected. */
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/* i.reg_operands MUST be the number of real register operands;
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implicit registers do not count. */
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implicit registers do not count. */
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if (i.reg_operands == 2)
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{
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unsigned int source, dest;
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source = (i.types[0] & (Reg | SReg2 | SReg3 | Control | Debug | Test)) ? 0 : 1;
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dest = source + 1;
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i.rm.mode = 3;
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/* We must be careful to make sure that all segment/control/test/
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debug registers go into the i.rm.reg field (despite the whether
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they are source or destination operands). */
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/* We must be careful to make sure that all
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segment/control/test/debug registers go into the i.rm.reg
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field (despite the whether they are source or destination
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operands). */
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if (i.regs[dest]->reg_type & (SReg2 | SReg3 | Control | Debug | Test))
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{
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i.rm.reg = i.regs[dest]->reg_num;
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@ -1115,11 +1117,11 @@ md_assemble (line)
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else if (!i.base_reg && (i.types[o] & BaseIndex))
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{
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/* There are three cases here.
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Case 1: '<32bit disp>(,1)' -- indirect absolute.
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(Same as cases 2 & 3 with NO index register)
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Case 2: <32bit disp> (,<index>) -- no base register with disp
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Case 3: (, <index>) --- no base register;
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no disp (must add 32bit 0 disp). */
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Case 1: '<32bit disp>(,1)' -- indirect absolute.
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(Same as cases 2 & 3 with NO index register)
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Case 2: <32bit disp> (,<index>) -- no base register with disp
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Case 3: (, <index>) --- no base register;
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no disp (must add 32bit 0 disp). */
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i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
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i.rm.mode = 0; /* 32bit mode */
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i.bi.base = NO_BASE_REGISTER;
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@ -1167,8 +1169,8 @@ md_assemble (line)
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}
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if (fake_zero_displacement)
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{
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/* Fakes a zero displacement assuming that i.types[o] holds
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the correct displacement size. */
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/* Fakes a zero displacement assuming that i.types[o]
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holds the correct displacement size. */
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exp = &disp_expressions[i.disp_operands++];
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i.disps[o] = exp;
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exp->X_seg = SEG_ABSOLUTE;
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@ -1194,7 +1196,7 @@ md_assemble (line)
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default_seg = one_byte_segment_defaults[seg_index];
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}
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/* If the specified segment is not the default, use an
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opcode prefix to select it */
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opcode prefix to select it */
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if (i.seg != default_seg)
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{
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if (i.prefixes == MAX_PREFIXES)
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@ -1209,24 +1211,24 @@ md_assemble (line)
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}
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/* Fill in i.rm.reg or i.rm.regmem field with register operand
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(if any) based on t->extension_opcode. Again, we must be careful
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to make sure that segment/control/debug/test registers are coded
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into the i.rm.reg field. */
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(if any) based on t->extension_opcode. Again, we must be
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careful to make sure that segment/control/debug/test
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registers are coded into the i.rm.reg field. */
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if (i.reg_operands)
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{
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unsigned int o =
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(i.types[0] & (Reg | SReg2 | SReg3 | Control | Debug | Test)) ? 0 :
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(i.types[1] & (Reg | SReg2 | SReg3 | Control | Debug | Test)) ? 1 : 2;
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/* If there is an extension opcode to put here, the register number
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must be put into the regmem field. */
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/* If there is an extension opcode to put here, the
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register number must be put into the regmem field. */
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if (t->extension_opcode != None)
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i.rm.regmem = i.regs[o]->reg_num;
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else
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i.rm.reg = i.regs[o]->reg_num;
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/* Now, if no memory operand has set i.rm.mode = 0, 1, 2
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we must set it to 3 to indicate this is a register operand
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int the regmem field */
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we must set it to 3 to indicate this is a register
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operand int the regmem field */
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if (!i.mem_operands)
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i.rm.mode = 3;
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}
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@ -1294,10 +1296,10 @@ md_assemble (line)
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break;
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default:
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/* It's a symbol; end frag & setup for relax.
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Make sure there are 6 chars left in the current frag; if not
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we'll have to start a new one. */
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Make sure there are 6 chars left in the current frag; if not
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we'll have to start a new one. */
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/* I caught it failing with obstack_room == 6,
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so I changed to <= pace */
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so I changed to <= pace */
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if (obstack_room (&frags) <= 6)
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{
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frag_wane (frag_now);
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@ -2457,10 +2459,4 @@ tc_coff_fix2rtype (fixP)
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#endif
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/*
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* Local Variables:
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* comment-column: 0
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* End:
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*/
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/* end of tc-i386.c */
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@ -31,16 +31,11 @@
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#endif /* CROSS_COMPILE */
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#define OBJ_COFF_OMIT_OPTIONAL_HEADER
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#define LOCAL_LABEL(name) ( (name[0] =='L') \
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#define LOCAL_LABEL(name) ((name[0] =='L') \
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|| (name[0] =='.' \
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&& (name[1]=='C' || name[1]=='I' || name[1]=='.')))
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&& (name[1]=='C' \
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|| name[1]=='I' \
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|| name[1]=='.')))
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#include "obj-format.h"
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/*
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* Local Variables:
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* comment-column: 0
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* fill-column: 131
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* End:
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*/
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/* end of te-ic960.h */
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