* sim-main.h: add vif registers
* interp.c: incorporate vif register load/store
* sky-pke.[ch]: add register load/store routines
* sku-vu.c: P register is float
This commit is contained in:
Ron Unrau
parent
69d5a56645
commit
c567d0b941
2 changed files with 167 additions and 146 deletions
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@ -197,6 +197,68 @@ pke_attach(SIM_DESC sd, struct pke_device* me)
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}
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}
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/* Read PKE Pseudo-PC into buf in target order */
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int
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read_pke_pc (struct pke_device *me, void *buf)
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{
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*((int *) buf) = H2T_4( me->fifo_pc );
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return 4;
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}
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/* Read PKE reg into buf in target order */
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int
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read_pke_reg (struct pke_device *me, int reg_num, void *buf)
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{
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/* handle reads to individual registers; clear `readable' on error */
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switch (reg_num)
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{
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/* handle common case of register reading, side-effect free */
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/* PKE1-only registers*/
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case PKE_REG_BASE:
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case PKE_REG_OFST:
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case PKE_REG_TOPS:
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case PKE_REG_TOP:
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case PKE_REG_DBF:
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if (me->pke_number == 0)
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{
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*((int *) buf) = 0;
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break;
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}
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/* fall through */
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/* PKE0 & PKE1 common registers*/
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case PKE_REG_STAT:
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case PKE_REG_ERR:
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case PKE_REG_MARK:
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case PKE_REG_CYCLE:
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case PKE_REG_MODE:
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case PKE_REG_NUM:
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case PKE_REG_MASK:
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case PKE_REG_CODE:
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case PKE_REG_ITOPS:
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case PKE_REG_ITOP:
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case PKE_REG_R0:
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case PKE_REG_R1:
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case PKE_REG_R2:
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case PKE_REG_R3:
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case PKE_REG_C0:
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case PKE_REG_C1:
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case PKE_REG_C2:
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case PKE_REG_C3:
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*((int *) buf) = H2T_4(me->regs[reg_num][0]);
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break;
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/* handle common case of write-only registers */
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case PKE_REG_FBRST:
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*((int *) buf) = 0;
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break;
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default:
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ASSERT(0); /* tests above should prevent this possibility */
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}
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return 4;
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}
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/* Handle a PKE read; return no. of bytes read */
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@ -231,68 +293,15 @@ pke_io_read_buffer(device *me_,
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/* register bank */
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int reg_num = ADDR_TRUNC_QW(addr - my_reg_start) >> 4;
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int reg_byte = ADDR_OFFSET_QW(addr); /* find byte-offset inside register bank */
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int readable = 1;
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quadword result;
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/* clear result */
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result[0] = result[1] = result[2] = result[3] = 0;
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/* handle reads to individual registers; clear `readable' on error */
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switch(reg_num)
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{
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/* handle common case of register reading, side-effect free */
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/* PKE1-only registers*/
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case PKE_REG_BASE:
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case PKE_REG_OFST:
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case PKE_REG_TOPS:
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case PKE_REG_TOP:
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case PKE_REG_DBF:
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if(me->pke_number == 0)
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readable = 0;
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/* fall through */
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/* PKE0 & PKE1 common registers*/
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case PKE_REG_STAT:
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case PKE_REG_ERR:
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case PKE_REG_MARK:
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case PKE_REG_CYCLE:
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case PKE_REG_MODE:
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case PKE_REG_NUM:
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case PKE_REG_MASK:
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case PKE_REG_CODE:
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case PKE_REG_ITOPS:
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case PKE_REG_ITOP:
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case PKE_REG_R0:
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case PKE_REG_R1:
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case PKE_REG_R2:
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case PKE_REG_R3:
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case PKE_REG_C0:
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case PKE_REG_C1:
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case PKE_REG_C2:
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case PKE_REG_C3:
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result[0] = H2T_4(me->regs[reg_num][0]);
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break;
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/* handle common case of write-only registers */
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case PKE_REG_FBRST:
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readable = 0;
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break;
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default:
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ASSERT(0); /* test above should prevent this possibility */
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}
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read_pke_reg (me, reg_num, result);
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/* perform transfer & return */
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if(readable)
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{
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/* copy the bits */
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memcpy(dest, ((unsigned_1*) &result) + reg_byte, nr_bytes);
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/* okay */
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}
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else
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{
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/* return zero bits */
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memset(dest, 0, nr_bytes);
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}
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memcpy(dest, ((unsigned_1*) &result) + reg_byte, nr_bytes);
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return nr_bytes;
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/* NOTREACHED */
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@ -311,8 +320,102 @@ pke_io_read_buffer(device *me_,
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return 0;
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}
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/* Write PKE reg from buf, which is in target order */
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int
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write_pke_reg (struct pke_device *me, int reg_num, const void *buf)
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{
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int writeable = 1;
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/* make words host-endian */
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unsigned_4 input = T2H_4( *((unsigned_4 *) buf) );
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/* Handle a PKE read; return no. of bytes written */
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/* handle writes to individual registers; clear `writeable' on error */
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switch (reg_num)
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{
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case PKE_REG_FBRST:
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/* Order these tests from least to most overriding, in case
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multiple bits are set. */
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if(BIT_MASK_GET(input, PKE_REG_FBRST_STC_B, PKE_REG_FBRST_STC_E))
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{
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/* clear a bunch of status bits */
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PKE_REG_MASK_SET(me, STAT, PSS, 0);
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PKE_REG_MASK_SET(me, STAT, PFS, 0);
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PKE_REG_MASK_SET(me, STAT, PIS, 0);
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PKE_REG_MASK_SET(me, STAT, INT, 0);
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PKE_REG_MASK_SET(me, STAT, ER0, 0);
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PKE_REG_MASK_SET(me, STAT, ER1, 0);
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me->flags &= ~PKE_FLAG_PENDING_PSS;
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/* will allow resumption of possible stalled instruction */
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}
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if(BIT_MASK_GET(input, PKE_REG_FBRST_STP_B, PKE_REG_FBRST_STP_E))
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{
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me->flags |= PKE_FLAG_PENDING_PSS;
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}
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if(BIT_MASK_GET(input, PKE_REG_FBRST_FBK_B, PKE_REG_FBRST_FBK_E))
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{
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PKE_REG_MASK_SET(me, STAT, PFS, 1);
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}
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if(BIT_MASK_GET(input, PKE_REG_FBRST_RST_B, PKE_REG_FBRST_RST_E))
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{
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pke_reset(me);
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}
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break;
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case PKE_REG_ERR:
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/* copy bottom three bits */
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BIT_MASK_SET(me->regs[PKE_REG_ERR][0], 0, 2, BIT_MASK_GET(input, 0, 2));
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break;
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case PKE_REG_MARK:
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/* copy bottom sixteen bits */
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PKE_REG_MASK_SET(me, MARK, MARK, BIT_MASK_GET(input, 0, 15));
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/* reset MRK bit in STAT */
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PKE_REG_MASK_SET(me, STAT, MRK, 0);
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break;
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/* handle common case of read-only registers */
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/* PKE1-only registers - not really necessary to handle separately */
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case PKE_REG_BASE:
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case PKE_REG_OFST:
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case PKE_REG_TOPS:
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case PKE_REG_TOP:
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case PKE_REG_DBF:
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if(me->pke_number == 0)
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writeable = 0;
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/* fall through */
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/* PKE0 & PKE1 common registers*/
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case PKE_REG_STAT:
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/* ignore FDR bit for PKE1_STAT -- simulator does not implement PKE->RAM transfers */
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case PKE_REG_CYCLE:
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case PKE_REG_MODE:
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case PKE_REG_NUM:
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case PKE_REG_MASK:
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case PKE_REG_CODE:
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case PKE_REG_ITOPS:
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case PKE_REG_ITOP:
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case PKE_REG_R0:
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case PKE_REG_R1:
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case PKE_REG_R2:
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case PKE_REG_R3:
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case PKE_REG_C0:
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case PKE_REG_C1:
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case PKE_REG_C2:
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case PKE_REG_C3:
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writeable = 0;
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break;
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default:
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ASSERT(0); /* test above should prevent this possibility */
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}
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/* perform return */
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if(! writeable)
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{
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return 0; /* error */
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}
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return 4;
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}
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/* Handle a PKE write; return no. of bytes written */
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int
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pke_io_write_buffer(device *me_,
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@ -344,7 +447,6 @@ pke_io_write_buffer(device *me_,
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/* register bank */
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int reg_num = ADDR_TRUNC_QW(addr - my_reg_start) >> 4;
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int reg_byte = ADDR_OFFSET_QW(addr); /* find byte-offset inside register bank */
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int writeable = 1;
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quadword input;
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/* clear input */
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@ -353,95 +455,7 @@ pke_io_write_buffer(device *me_,
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/* write user-given bytes into input */
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memcpy(((unsigned_1*) &input) + reg_byte, src, nr_bytes);
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/* make words host-endian */
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input[0] = T2H_4(input[0]);
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/* we may ignore other words */
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/* handle writes to individual registers; clear `writeable' on error */
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switch(reg_num)
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{
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case PKE_REG_FBRST:
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/* Order these tests from least to most overriding, in case
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multiple bits are set. */
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if(BIT_MASK_GET(input[0], PKE_REG_FBRST_STC_B, PKE_REG_FBRST_STC_E))
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{
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/* clear a bunch of status bits */
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PKE_REG_MASK_SET(me, STAT, PSS, 0);
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PKE_REG_MASK_SET(me, STAT, PFS, 0);
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PKE_REG_MASK_SET(me, STAT, PIS, 0);
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PKE_REG_MASK_SET(me, STAT, INT, 0);
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PKE_REG_MASK_SET(me, STAT, ER0, 0);
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PKE_REG_MASK_SET(me, STAT, ER1, 0);
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me->flags &= ~PKE_FLAG_PENDING_PSS;
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/* will allow resumption of possible stalled instruction */
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}
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if(BIT_MASK_GET(input[0], PKE_REG_FBRST_STP_B, PKE_REG_FBRST_STP_E))
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{
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me->flags |= PKE_FLAG_PENDING_PSS;
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}
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if(BIT_MASK_GET(input[0], PKE_REG_FBRST_FBK_B, PKE_REG_FBRST_FBK_E))
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{
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PKE_REG_MASK_SET(me, STAT, PFS, 1);
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}
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if(BIT_MASK_GET(input[0], PKE_REG_FBRST_RST_B, PKE_REG_FBRST_RST_E))
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{
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pke_reset(me);
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}
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break;
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case PKE_REG_ERR:
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/* copy bottom three bits */
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BIT_MASK_SET(me->regs[PKE_REG_ERR][0], 0, 2, BIT_MASK_GET(input[0], 0, 2));
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break;
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case PKE_REG_MARK:
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/* copy bottom sixteen bits */
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PKE_REG_MASK_SET(me, MARK, MARK, BIT_MASK_GET(input[0], 0, 15));
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/* reset MRK bit in STAT */
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PKE_REG_MASK_SET(me, STAT, MRK, 0);
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break;
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/* handle common case of read-only registers */
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/* PKE1-only registers - not really necessary to handle separately */
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case PKE_REG_BASE:
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case PKE_REG_OFST:
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case PKE_REG_TOPS:
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case PKE_REG_TOP:
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case PKE_REG_DBF:
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if(me->pke_number == 0)
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writeable = 0;
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/* fall through */
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/* PKE0 & PKE1 common registers*/
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case PKE_REG_STAT:
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/* ignore FDR bit for PKE1_STAT -- simulator does not implement PKE->RAM transfers */
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case PKE_REG_CYCLE:
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case PKE_REG_MODE:
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case PKE_REG_NUM:
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case PKE_REG_MASK:
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case PKE_REG_CODE:
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case PKE_REG_ITOPS:
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case PKE_REG_ITOP:
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case PKE_REG_R0:
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case PKE_REG_R1:
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case PKE_REG_R2:
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case PKE_REG_R3:
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case PKE_REG_C0:
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case PKE_REG_C1:
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case PKE_REG_C2:
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case PKE_REG_C3:
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writeable = 0;
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break;
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default:
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ASSERT(0); /* test above should prevent this possibility */
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}
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/* perform return */
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if(! writeable)
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{
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; /* error */
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}
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write_pke_reg (me, reg_num, input);
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return nr_bytes;
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/* NOTREACHED */
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@ -412,6 +412,13 @@ struct pke_device
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int qw_pc; /* 0 .. 3: word index of next instruction */
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};
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extern struct pke_device pke0_device;
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extern struct pke_device pke1_device;
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int read_pke_reg (struct pke_device *device, int regno, void *buf);
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int write_pke_reg (struct pke_device *device, int regno, const void *buf);
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int read_pke_pc (struct pke_device *device, void *buf);
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/* Flags for PKE.flags */
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