Fix the encoding of the MSP430's RRUX instruction.
PR target/19561 opcdoe * msp430-dis.c (print_insn_msp430): Add a special case for decoding an RRC instruction with the ZC bit set in the extension word. include * opcode/msp430.h (IGNORE_CARRY_BIT): New define. (RRUX): Synthesise using case 2 rather than 7. gas * config/tc-msp430.c (msp430_operands): Remove case 7. Use case 2 to handle encoding of RRUX instruction. * testsuite/gas/msp430/msp430x.s: Add more tests of the extended shift instructions. * testsuite/gas/msp430/msp430x.d: Update expected disassembly.
This commit is contained in:
Nick Clifton
parent
1b18aa1e79
commit
c1d9289fef
8 changed files with 81 additions and 94 deletions
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@ -1,12 +1,19 @@
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2016-02-04 Nick Clifton <nickc@redhat.com>
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PR target/19561
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* config/tc-msp430.c (msp430_operands): Remove case 7. Use case 2
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to handle encoding of RRUX instruction.
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* testsuite/gas/msp430/msp430x.s: Add more tests of the extended
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shift instructions.
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* testsuite/gas/msp430/msp430x.d: Update expected disassembly.
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2016-02-03 Max Filippov <jcmvbkbc@gmail.com>
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* config/tc-xtensa.c (md_apply_fix): Mark BFD_RELOC_XTENSA_DIFF*
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substitutions for BFD_RELOC_* as unsigned.
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* gas/testsuite/gas/xtensa/all.exp: Add loc to list of xtensa
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tests.
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* gas/testsuite/gas/xtensa/loc.d: New file: loc test result
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patterns.
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* gas/testsuite/gas/xtensa/loc.s: New file: loc test.
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* testsuite/gas/xtensa/all.exp: Add loc to list of xtensa tests.
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* testsuite/gas/xtensa/loc.d: New file: loc test result patterns.
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* testsuite/gas/xtensa/loc.s: New file: loc test.
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2016-02-03 Kevin Buettner <kevinb@redhat.com>
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@ -3172,63 +3172,6 @@ msp430_operands (struct msp430_opcode_s * opcode, char * line)
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break;
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}
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case 7:
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{
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int reg;
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/* RRUX: Synthetic unsigned right shift of a register by one bit. */
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if (extended & 0xff)
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{
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as_bad (_("repeat count cannot be used with %s"), opcode->name);
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break;
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}
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line = extract_operand (line, l1, sizeof (l1));
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if ((reg = check_reg (l1)) == -1)
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{
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as_bad (_("expected register as argument of %s"),
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opcode->name);
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break;
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}
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if (target_is_430xv2 () && reg == 0)
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{
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as_bad (_("%s: attempt to rotate the PC register"), opcode->name);
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break;
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}
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if (byte_op)
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{
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/* Tricky - there is no single instruction that will do this.
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Encode as: RRA.B rN { BIC.B #0x80, rN */
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op_length = 6;
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frag = frag_more (op_length);
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where = frag - frag_now->fr_literal;
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bin = 0x1140 | reg;
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bfd_putl16 ((bfd_vma) bin, frag);
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dwarf2_emit_insn (2);
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bin = 0xc070 | reg;
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bfd_putl16 ((bfd_vma) bin, frag + 2);
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bin = 0x0080;
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bfd_putl16 ((bfd_vma) bin, frag + 4);
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dwarf2_emit_insn (4);
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}
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else
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{
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/* Encode as RRUM[.A] rN. */
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bin = opcode->bin_opcode;
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if (! addr_op)
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bin |= 0x10;
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bin |= reg;
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op_length = 2;
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frag = frag_more (op_length);
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where = frag - frag_now->fr_literal;
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bfd_putl16 ((bfd_vma) bin, frag);
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dwarf2_emit_insn (op_length);
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}
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break;
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}
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case 8:
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{
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bfd_boolean need_reloc = FALSE;
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@ -3660,6 +3603,9 @@ msp430_operands (struct msp430_opcode_s * opcode, char * line)
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else if (! addr_op)
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extended |= BYTE_OPERATION;
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if (is_opcode ("rrux"))
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extended |= IGNORE_CARRY_BIT;
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if (op1.ol != 0 && ((extended & 0xf) != 0))
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{
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as_bad (_("repeat instruction used with non-register mode instruction"));
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@ -201,27 +201,32 @@ Disassembly of section .text:
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0+039e <[^>]*> 54 0b rrum #3, r4 ;
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0+03a0 <[^>]*> 44 07 rrum.a #2, r4 ;
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0+03a2 <[^>]*> 54 03 rrum #1, r4 ;
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0+03a4 <[^>]*> 54 03 rrum #1, r4 ;
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0+03a6 <[^>]*> 47 03 rrum.a #1, r7 ;
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0+03a8 <[^>]*> 45 11 rra.b r5 ;
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0+03aa <[^>]*> 75 c0 80 00 bic.b #128, r5 ;#0x0080
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0+03ae <[^>]*> 56 03 rrum #1, r6 ;
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0+03b0 <[^>]*> 40 18 81 10 swpbx.w r1 ;
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0+03b4 <[^>]*> 00 18 90 10 00 00 swpbx.a 0x0000 ;PC rel. 0x03b8
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0+03ba <[^>]*> 40 18 8c 10 swpbx.w r12 ;
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0+03be <[^>]*> 40 18 82 11 sxtx.w r2 ;
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0+03c2 <[^>]*> 00 18 92 11 00 00 sxtx.a &0x0000 ;
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0+03c8 <[^>]*> 40 18 82 11 sxtx.w r2 ;
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0+03cc <[^>]*> 04 18 45 11 rpt #5 \{ rrax.a r5 ;
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0+03d0 <[^>]*> 85 18 45 11 rpt r5 \{ rrax.a r5 ;
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0+03d4 <[^>]*> e2 01 adda r1, r2 ;
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0+03d6 <[^>]*> c0 01 mova r1, r0 ;
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0+03d8 <[^>]*> 41 13 calla r1 ;
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0+03da <[^>]*> 40 18 01 43 clrx.w r1 ;
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0+03de <[^>]*> d2 01 cmpa r1, r2 ;
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0+03e0 <[^>]*> 40 18 21 83 decdx.w r1 ;
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0+03e4 <[^>]*> 40 18 21 53 incdx.w r1 ;
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0+03e8 <[^>]*> c2 01 mova r1, r2 ;
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0+03ea <[^>]*> 10 01 reta ;
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0+03ec <[^>]*> f2 01 suba r1, r2 ;
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0+03ee <[^>]*> 40 18 80 93 00 00 cmpx.w #0, 0x00000 ;r3 As==00, PC rel. 0x003f2
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0+03a4 <[^>]*> 40 19 04 10 rrux.w r4 ;
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0+03a8 <[^>]*> 00 19 47 10 rrux.a r7 ;
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0+03ac <[^>]*> 40 19 45 10 rrux.b r5 ;
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0+03b0 <[^>]*> 40 19 06 10 rrux.w r6 ;
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0+03b4 <[^>]*> 40 18 81 10 swpbx.w r1 ;
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0+03b8 <[^>]*> 00 18 90 10 00 00 swpbx.a 0x0000 ;PC rel. 0x03bc
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0+03be <[^>]*> 40 18 8c 10 swpbx.w r12 ;
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0+03c2 <[^>]*> 40 18 82 11 sxtx.w r2 ;
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0+03c6 <[^>]*> 00 18 92 11 00 00 sxtx.a &0x0000 ;
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0+03cc <[^>]*> 40 18 82 11 sxtx.w r2 ;
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0+03d0 <[^>]*> 04 18 45 11 rpt #5 \{ rrax.a r5 ;
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0+03d4 <[^>]*> 85 18 45 11 rpt r5 \{ rrax.a r5 ;
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0+03d8 <[^>]*> e2 01 adda r1, r2 ;
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0+03da <[^>]*> c0 01 mova r1, r0 ;
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0+03dc <[^>]*> 41 13 calla r1 ;
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0+03de <[^>]*> 40 18 01 43 clrx.w r1 ;
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0+03e2 <[^>]*> d2 01 cmpa r1, r2 ;
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0+03e4 <[^>]*> 40 18 21 83 decdx.w r1 ;
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0+03e8 <[^>]*> 40 18 21 53 incdx.w r1 ;
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0+03ec <[^>]*> c2 01 mova r1, r2 ;
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0+03ee <[^>]*> 10 01 reta ;
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0+03f0 <[^>]*> f2 01 suba r1, r2 ;
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0+03f2 <[^>]*> 40 18 80 93 00 00 cmpx.w #0, 0x00000 ;r3 As==00, PC rel. 0x003f6
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0+03f8 <[^>]*> c1 19 01 10 rpt r1 \{ rrux.w r1 ;
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0+03fc <[^>]*> 41 18 02 10 rpt #2 \{ rrcx.w r2 ;
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0+0400 <[^>]*> 42 18 47 11 rpt #3 \{ rrax.b r7 ;
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0+0404 <[^>]*> 84 18 44 11 rpt r4 \{ rrax.a r4 ;
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0+0408 <[^>]*> 44 18 45 55 rpt #5 \{ rlax.b r5 ;
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0+040c <[^>]*> 05 18 46 66 rpt #6 \{ rlcx.a r6 ;
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@ -274,4 +274,10 @@ foo:
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sub.a r1, r2
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tst.a fooz
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;; Check that repeat counts can be used with shift instructions.
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rpt r1 { rrux.w r1
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rpt #2 { rrcx.w r2
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rpt #3 { rrax.b r7
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rpt r4 { rrax.a r4
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rpt #5 { rlax.b r5
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rpt #6 { rlcx.a r6
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@ -1,3 +1,9 @@
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2016-02-04 Nick Clifton <nickc@redhat.com>
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PR target/19561
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* opcode/msp430.h (IGNORE_CARRY_BIT): New define.
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(RRUX): Synthesise using case 2 rather than 7.
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2016-01-19 John Baldwin <jhb@FreeBSD.org>
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* elf/common.h (NT_FREEBSD_THRMISC): Define.
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@ -35,7 +35,13 @@ struct msp430_operand_s
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#endif
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};
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#define BYTE_OPERATION (1 << 6) /* Byte operation flag for all instructions. */
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/* Byte operation flag for all instructions. Also used as the
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A/L bit in the extension word to indicate a 20-bit operation. */
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#define BYTE_OPERATION (1 << 6)
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/* Z/C bit in the extension word. If set the carry bit is ignored
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for the duration of the operation, although it may be changed as
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a result of the operation. */
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#define IGNORE_CARRY_BIT (1 << 8)
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struct msp430_opcode_s
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{
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@ -46,7 +52,7 @@ struct msp430_opcode_s
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int bin_mask;
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};
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#define MSP_INSN(name, size, numb, bin, mask) { #name, size, numb, bin, mask }
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#define MSP_INSN(name, fmt, numb, bin, mask) { #name, fmt, numb, bin, mask }
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static struct msp430_opcode_s msp430_opcodes[] =
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{
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@ -156,7 +162,8 @@ static struct msp430_opcode_s msp430_opcodes[] =
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MSP_INSN (pushx, -3, 1, 0x1200, 0xff80),
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MSP_INSN (rrax, -3, 1, 0x1100, 0xff80),
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MSP_INSN (rrcx, -3, 1, 0x1000, 0xff80),
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MSP_INSN (rrcx, -3, 1, 0x1000, 0xff80), /* Synthesised as RRC but with the Z/C bit clear. */
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MSP_INSN (rrux, -3, 1, 0x1000, 0xff80), /* Synthesised as RRC but with the Z/C bit set. */
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MSP_INSN (swpbx, -3, 1, 0x1080, 0xffc0),
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MSP_INSN (sxtx, -3, 1, 0x1180, 0xffc0),
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@ -173,8 +180,6 @@ static struct msp430_opcode_s msp430_opcodes[] =
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MSP_INSN (rlam, -1, 6, 0x0240, 0xf3e0),
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MSP_INSN (rrum, -1, 6, 0x0340, 0xf3e0),
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MSP_INSN (rrux, -1, 7, 0x0340, 0xffe0), /* Synthesized in terms of RRUM. */
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MSP_INSN (adda, -1, 8, 0x00a0, 0xf0b0),
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MSP_INSN (cmpa, -1, 8, 0x0090, 0xf0b0),
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MSP_INSN (suba, -1, 8, 0x00b0, 0xf0b0),
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@ -1,3 +1,10 @@
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2016-02-04 Nick Clifton <nickc@redhat.com>
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PR target/19561
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* msp430-dis.c (print_insn_msp430): Add a special case for
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decoding an RRC instruction with the ZC bit set in the extension
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word.
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2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
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* cgen-ibld.in (insert_normal): Rework calculation of shift.
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@ -1102,7 +1102,7 @@ print_insn_msp430 (bfd_vma addr, disassemble_info *info)
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}
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else if (extension_word)
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{
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if (extension_word & (1 << 6))
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if (extension_word & BYTE_OPERATION)
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bc = ".w";
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else
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{
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@ -1181,7 +1181,12 @@ print_insn_msp430 (bfd_vma addr, disassemble_info *info)
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prin (stream, "rpt #%d { ", (extension_word & 0xf) + 1);
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}
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if (extension_word && opcode->name[strlen (opcode->name) - 1] != 'x')
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/* Special case: RRC with an extension word and the ZC bit set is actually RRU. */
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if (extension_word
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&& (extension_word & IGNORE_CARRY_BIT)
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&& strcmp (opcode->name, "rrc") == 0)
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(*prin) (stream, "rrux%s", bc);
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else if (extension_word && opcode->name[strlen (opcode->name) - 1] != 'x')
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(*prin) (stream, "%sx%s", opcode->name, bc);
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else
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(*prin) (stream, "%s%s", opcode->name, bc);
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