* doc/c-sparc.texi: Add syntax section.
This commit is contained in:
David S. Miller
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2 changed files with 402 additions and 6 deletions
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@ -1,3 +1,7 @@
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2008-04-18 David S. Miller <davem@davemloft.net>
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* doc/c-sparc.texi: Add syntax section.
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2008-04-18 H.J. Lu <hongjiu.lu@intel.com>
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* config/tc-i386.c (build_modrm_byte): Don't check FMA to swap
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@ -16,6 +16,7 @@
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@menu
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* Sparc-Opts:: Options
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* Sparc-Aligned-Data:: Option to enforce aligned data
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* Sparc-Syntax:: Syntax
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* Sparc-Float:: Floating Point
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* Sparc-Directives:: Sparc Machine Directives
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@end menu
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@ -109,12 +110,403 @@ data structures (structures defined using the @code{packed} attribute).
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You may have to assemble with GAS in order to initialize packed data
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structures in your own code.
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@ignore
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@c FIXME: (sparc) Fill in "syntax" section!
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@c subsection syntax
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I don't know anything about Sparc syntax. Someone who does
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will have to write this section.
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@end ignore
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@cindex SPARC syntax
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@cindex syntax, SPARC
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@node Sparc-Syntax
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@section Sparc Syntax
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The assembler syntax closely follows The Sparc Architecture Manual,
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versions 8 and 9, as well as most extensions defined by Sun
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for their UltraSPARC and Niagara line of processors.
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@menu
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* Sparc-Chars:: Special Characters
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* Sparc-Regs:: Register Names
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* Sparc-Relocs:: Relocations
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@end menu
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@node Sparc-Chars
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@subsection Special Characters
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@cindex line comment character, Sparc
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@cindex Sparc line comment character
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@samp{#} is the line comment character.
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@cindex line separator, Sparc
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@cindex statement separator, Sparc
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@cindex Sparc line separator
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@samp{;} can be used instead of a newline to separate statements.
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@node Sparc-Regs
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@subsection Register Names
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@cindex Sparc registers
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@cindex register names, Sparc
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The Sparc integer register file is broken down into global,
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outgoing, local, and incoming.
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@itemize @bullet
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@item
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The 8 global registers are referred to as @samp{%g@var{n}}.
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@item
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The 8 outgoing registers are referred to as @samp{%o@var{n}}.
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@item
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The 8 local registers are referred to as @samp{%l@var{n}}.
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@item
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The 8 incoming registers are referred to as @samp{%i@var{n}}.
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@item
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The frame pointer register @samp{%i6} can be referenced using
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the alias @samp{%fp}.
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@item
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The stack pointer register @samp{%o6} can be referenced using
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the alias @samp{%sp}.
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@end itemize
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Floating point registers are simply referred to as @samp{%f@var{n}}.
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When assembling for pre-V9, only 32 floating point registers
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are available. For V9 and later there are 64, but there are
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restrictions when referencing the upper 32 registers. They
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can only be accessed as double or quad, and thus only even
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or quad numbered accesses are allowed. For example, @samp{%f34}
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is a legal floating point register, but @samp{%f35} is not.
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Certain V9 instructions allow access to ancillary state registers.
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Most simply they can be referred to as @samp{%asr@var{n}} where
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@var{n} can be from 16 to 31. However, there are some aliased
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defined to reference ASR registers defined for various UltraSPARC
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processors:
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@itemize @bullet
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@item
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The tick compare register is referred to as @samp{%tick_cmpr}.
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@item
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The system tick register is referred to as @samp{%sys_tick}.
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@item
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The system tick compare register is referred to as @samp{%sys_tick_cmpr}.
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@item
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The software interrupt register is referred to as @samp{%softint}.
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@item
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The set software interrupt register is referred to as @samp{%set_softint}.
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@item
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The clear software interrupt register is referred to as
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@samp{%clear_softint}.
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@item
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The performance instrumentation counters register is referred to as
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@samp{%pic}.
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@item
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The performance control register is referred to as @samp{%pcr}.
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@item
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The graphics status register is referred to as @samp{%gsr}.
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@item
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The dispatch control register is referred to as @samp{%dcr}.
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@end itemize
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Various V9 branch and conditional move instructions allow
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specification of which set of integer condition codes to
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test. These are referred to as @samp{%xcc} and @samp{%icc}.
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In V9, there are 4 sets of floating point condition codes
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which are referred to as @samp{%fcc@var{n}}.
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Several special privileged and non-privileged registers
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exist:
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@itemize @bullet
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@item
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The V9 address space identifier register is referred to as @samp{%asi}.
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@item
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The V9 restorable windows register is referred to as @samp{%canrestore}.
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@item
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The V9 savable windows register is referred to as @samp{%cansave}.
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@item
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The V9 clean windows register is referred to as @samp{%cleanwin}.
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@item
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The V9 current window pointer register is referred to as @samp{%cwp}.
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@item
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The floating-point queue register is referred to as @samp{%fq}.
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@item
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The co-processor queue register is referred to as @samp{%cq}.
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@item
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The floating point status register is referred to as @samp{%fsr}.
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@item
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The other windows register is referred to as @samp{%otherwin}.
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@item
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The V9 program counter register is referred to as @samp{%pc}.
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@item
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The V9 next program counter register is referred to as @samp{%npc}.
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@item
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The V9 processor interrupt level register is referred to as @samp{%pil}.
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@item
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The V9 processor state register is referred to as @samp{%pstate}.
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@item
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The trap base address register is referred to as @samp{%tba}.
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@item
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The V9 tick register is referred to as @samp{%tick}.
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@item
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The V9 trap level is referred to as @samp{%tl}.
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@item
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The V9 trap program counter is referred to as @samp{%tpc}.
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@item
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The V9 trap next program counter is referred to as @samp{%tnpc}.
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@item
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The V9 trap state is referred to as @samp{%tstate}.
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@item
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The V9 trap type is referred to as @samp{%tt}.
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@item
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The V9 condition codes is referred to as @samp{%ccr}.
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@item
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The V9 floating-point registers state is referred to as @samp{%fprs}.
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@item
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The V9 version register is referred to as @samp{%ver}.
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@item
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The V9 window state register is referred to as @samp{%wstate}.
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@item
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The Y register is referred to as @samp{%y}.
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@item
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The V8 window invalid mask register is referred to as @samp{%wim}.
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@item
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The V8 processor state register is referred to as @samp{%psr}.
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@item
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The global register level register is referred to as @samp{%gl}.
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@end itemize
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Several special register names exist for hypervisor mode code:
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@itemize @bullet
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@item
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The hyperprivileged processor state register is referred to as
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@samp{%hpstate}.
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@item
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The hyperprivileged trap state register is referred to as @samp{%htstate}.
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@item
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The hyperprivileged interrupt pending register is referred to as
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@samp{%hintp}.
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@item
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The hyperprivileged trap base address register is referred to as
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@samp{%htba}.
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@item
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The hyperprivileged implementation version register is referred
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to as @samp{%hver}.
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@item
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The hyperprivileged system tick compare register is referred
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to as @samp{%hstick_cmpr}.
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@end itemize
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@node Sparc-Relocs
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@subsection Relocations
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@cindex Sparc relocations
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@cindex relocations, Sparc
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ELF relocations are available as defined in the 32-bit and 64-bit
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Sparc ELF specifications.
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@code{R_SPARC_HI22} is obtained using @samp{%hi} and @code{R_SPARC_LO10}
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is obtained using @samp{%lo}. Likewise @code{R_SPARC_HIX22} is
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obtained from @samp{%hix} and @code{R_SPARC_LOX10} is obtained
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using @samp{%lox}. For example:
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@example
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sethi %hi(symbol), %g1
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or %g1, %lo(symbol), %g1
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sethi %hix(symbol), %g1
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xor %g1, %lox(symbol), %g1
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@end example
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These ``high'' mnemonics extract bits 31:10 of their operand,
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and the ``low'' mnemonics extract bits 9:0 of their operand.
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V9 code model relocations can be requested as follows:
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@itemize @bullet
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@item
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@code{R_SPARC_HH22} is requested using @samp{%hh}. It can
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also be generated using @samp{%uhi}.
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@item
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@code{R_SPARC_HM10} is requested using @samp{%hm}. It can
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also be generated using @samp{%ulo}.
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@item
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@code{R_SPARC_LM22} is requested using @samp{%lm}.
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@item
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@code{R_SPARC_H44} is requested using @samp{%h44}.
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@item
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@code{R_SPARC_M44} is requested using @samp{%m44}.
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@item
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@code{R_SPARC_L44} is requested using @samp{%l44}.
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@end itemize
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The PC relative relocation @code{R_SPARC_PC22} can be obtained by
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enclosing an operand inside of @samp{%pc22}. Likewise, the
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@code{R_SPARC_PC10} relocation can be obtained using @samp{%pc10}.
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These are mostly used when assembling PIC code. For example, the
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standard PIC sequence on Sparc to get the base of the global offset
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table, PC relative, into a register, can be performed as:
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@example
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sethi %pc22(_GLOBAL_OFFSET_TABLE_-4), %l7
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add %l7, %pc10(_GLOBAL_OFFSET_TABLE_+4), %l7
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@end example
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Several relocations exist to allow the link editor to potentially
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optimize GOT data references. The @code{R_SPARC_GOTDATA_OP_HIX22}
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relocation can obtained by enclosing an operand inside of
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@samp{%gdop_hix22}. The @code{R_SPARC_GOTDATA_OP_LOX10}
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relocation can obtained by enclosing an operand inside of
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@samp{%gdop_lox10}. Likewise, @code{R_SPARC_GOTDATA_OP} can be
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obtained by enclosing an operand inside of @samp{%gdop}.
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For example, assuming the GOT base is in register @code{%l7}:
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@example
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sethi %gdop_hix22(symbol), %l1
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xor %l1, %gdop_lox10(symbol), %l1
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ld [%l7 + %l1], %l2, %gdop(symbol)
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@end example
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There are many relocations that can be requested for access to
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thread local storage variables. All of the Sparc TLS mnemonics
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are supported:
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@itemize @bullet
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@item
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@code{R_SPARC_TLS_GD_HI22} is requested using @samp{%tgd_hi22}.
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@item
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@code{R_SPARC_TLS_GD_LO10} is requested using @samp{%tgd_lo10}.
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@item
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@code{R_SPARC_TLS_GD_ADD} is requested using @samp{%tgd_add}.
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@item
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@code{R_SPARC_TLS_GD_CALL} is requested using @samp{%tgd_call}.
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@item
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@code{R_SPARC_TLS_LDM_HI22} is requested using @samp{%tldm_hi22}.
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@item
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@code{R_SPARC_TLS_LDM_LO10} is requested using @samp{%tldm_lo10}.
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@item
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@code{R_SPARC_TLS_LDM_ADD} is requested using @samp{%tldm_add}.
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@item
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@code{R_SPARC_TLS_LDM_CALL} is requested using @samp{%tldm_call}.
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@item
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@code{R_SPARC_TLS_LDO_HIX22} is requested using @samp{%tldo_hix22}.
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@item
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@code{R_SPARC_TLS_LDO_LOX10} is requested using @samp{%tldo_lox10}.
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@item
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@code{R_SPARC_TLS_LDO_ADD} is requested using @samp{%tldo_add}.
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@item
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@code{R_SPARC_TLS_IE_HI22} is requested using @samp{%tie_hi22}.
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@item
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@code{R_SPARC_TLS_IE_LO10} is requested using @samp{%tie_lo10}.
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@item
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@code{R_SPARC_TLS_IE_LD} is requested using @samp{%tie_ld}.
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@item
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@code{R_SPARC_TLS_IE_LDX} is requested using @samp{%tie_ldx}.
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@item
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@code{R_SPARC_TLS_IE_ADD} is requested using @samp{%tie_add}.
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@item
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@code{R_SPARC_TLS_LE_HIX22} is requested using @samp{%tle_hix22}.
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@item
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@code{R_SPARC_TLS_LE_LOX10} is requested using @samp{%tle_lox10}.
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@end itemize
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Here are some example TLS model sequences.
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First, General Dynamic:
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@example
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sethi %tgd_hi22(symbol), %l1
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add %l1, %tgd_lo10(symbol), %l1
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add %l7, %l1, %o0, %tgd_add(symbol)
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call __tls_get_addr, %tgd_call(symbol)
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nop
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@end example
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Local Dynamic:
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@example
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sethi %tldm_hi22(symbol), %l1
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add %l1, %tldm_lo10(symbol), %l1
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add %l7, %l1, %o0, %tldm_add(symbol)
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call __tls_get_addr, %tldm_call(symbol)
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nop
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sethi %tldo_hix22(symbol), %l1
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xor %l1, %tldo_lox10(symbol), %l1
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add %o0, %l1, %l1, %tldo_add(symbol)
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@end example
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Initial Exec:
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@example
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sethi %tie_hi22(symbol), %l1
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add %l1, %tie_lo10(symbol), %l1
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ld [%l7 + %l1], %o0, %tie_ld(symbol)
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add %g7, %o0, %o0, %tie_add(symbol)
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sethi %tie_hi22(symbol), %l1
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add %l1, %tie_lo10(symbol), %l1
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ldx [%l7 + %l1], %o0, %tie_ldx(symbol)
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add %g7, %o0, %o0, %tie_add(symbol)
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@end example
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And finally, Local Exec:
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@example
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sethi %tle_hix22(symbol), %l1
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add %l1, %tle_lox10(symbol), %l1
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add %g7, %l1, %l1
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@end example
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When assembling for 64-bit, and a secondary constant addend is
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specified in an address expression that would normally generate
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an @code{R_SPARC_LO10} relocation, the assembler will emit an
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@code{R_SPARC_OLO10} instead.
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@node Sparc-Float
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@section Floating Point
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