darkkirb/old-cross-binutils
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

Patch to update IA-64 port to SDM 2.1.

Browse source 
bfd/ChangeLog
	* cpu-ia64-opc.c: Add operand constant "ar.csd".
gas/ChangeLog
	* config/tc-ia64.c (pseudo_func): Add "@pause" constant for "hint"
	instruction.
	(emit_one_bundle): Handle "hint" instruction.
	(operand_match): Match IA64_OPND_AR_CSD.
gas/testsuite/ChangeLog
	* gas/ia64/opc-b.d: Update for instructions added by SDM2.1.
	* gas/ia64/opc-b.s: Ditto.
	* gas/ia64/opc-f.d: Ditto.
	* gas/ia64/opc-f.s: Ditto.
	* gas/ia64/opc-i.d: Ditto.
	* gas/ia64/opc-i.s: Ditto.
	* gas/ia64/opc-m.d: Ditto.
	* gas/ia64/opc-m.s: Ditto.
	* gas/ia64/opc-x.d: Ditto.
	* gas/ia64/opc-x.s: Ditto.
include/opcode/ChangeLog
	* ia64.h: Fix copyright message.
	(IA64_OPND_AR_CSD): New operand kind.
opcodes/ChangeLog
	* ia64-opc-d.c (ia64_opcodes_d): Add "hint" instruction.
	* ia64-opc-b.c: Add "hint.b" instruction.
	* ia64-opc-f.c: Add "hint.f" instruction.
	* ia64-opc-i.c: Add "hint.i" instruction.
	* ia64-opc-m.c: Add "hint.m", "fc.i", "ld16", "st16", and
	"cmp8xchg16" instructions.
	* ia64-opc-x.c: Add "hint.x" instruction.
	* ia64-opc.h (AR_CSD): New macro.
	* ia64-ic.tbl: Update according to SDM2.1.
	* ia64-raw.tbl: Ditto.
	* ia64-waw.tbl: Ditto.
	* ia64-gen.c (in_iclass): Handle "hint" like "nop".
	(lookup_regindex): Recognize AR[FCR], AR[EFLAG], AR[CSD],
	AR[SSD], AR[CFLG], AR[FSR], AR[FIR], and AR[FDR].
	* ia64-asmtab.c: Regenerate.
This commit is contained in:
Jim Wilson 2002-12-05 02:08:02 +00:00
parent 27e829d037
commit c10d9d8fc3
30 changed files with 6258 additions and 5880 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
bfd/ChangeLog
View file

@ -1,3 +1,7 @@
2002-12-04 David Mosberger <davidm@hpl.hp.com>
* cpu-ia64-opc.c: Add operand constant "ar.csd".
2002-12-04 H.J. Lu <hjl@gnu.org>
* elfxx-ia64.c (get_local_sym_hash): Use section ID instead of

1
bfd/cpu-ia64-opc.c
View file

@ -418,6 +418,7 @@ const struct ia64_operand elf64_ia64_operands[IA64_OPND_COUNT] =
{
/* constants: */
{ CST, ins_const, ext_const, "NIL", {{ 0, 0}}, 0, "<none>" },
{ CST, ins_const, ext_const, "ar.csd", {{ 0, 0}}, 0, "ar.csd" },
{ CST, ins_const, ext_const, "ar.ccv", {{ 0, 0}}, 0, "ar.ccv" },
{ CST, ins_const, ext_const, "ar.pfs", {{ 0, 0}}, 0, "ar.pfs" },
{ CST, ins_const, ext_const, "1", {{ 0, 0}}, 0, "1" },

7
gas/ChangeLog
View file

@ -1,3 +1,10 @@
2002-12-04 David Mosberger <davidm@hpl.hp.com>
* config/tc-ia64.c (pseudo_func): Add "@pause" constant for "hint"
instruction.
(emit_one_bundle): Handle "hint" instruction.
(operand_match): Match IA64_OPND_AR_CSD.
2002-12-04 Alan Modra <amodra@bigpond.net.au>
* dwarf2dbg.c (scale_addr_delta): Correct parameter. Move prototype

11
gas/config/tc-ia64.c
View file

@ -519,6 +519,9 @@ pseudo_func[] =
{ "natval", PSEUDO_FUNC_CONST, { 0x100 } }, /* old usage */
/* hint constants: */
{ "pause", PSEUDO_FUNC_CONST, { 0x0 } },
/* unwind-related constants: */
{ "svr4", PSEUDO_FUNC_CONST, { 0 } },
{ "hpux", PSEUDO_FUNC_CONST, { 1 } },
@ -5032,6 +5035,11 @@ operand_match (idesc, index, e)
return OPERAND_MATCH;
break;
case IA64_OPND_AR_CSD:
if (e->X_op == O_register && e->X_add_number == REG_AR + 25)
return OPERAND_MATCH;
break;
case IA64_OPND_AR_PFS:
if (e->X_op == O_register && e->X_add_number == REG_AR + 64)
return OPERAND_MATCH;
@ -6156,10 +6164,11 @@ emit_one_bundle ()
}
required_unit = ia64_templ_desc[template].exec_unit[i];
/* resolve dynamic opcodes such as "break" and "nop": */
/* resolve dynamic opcodes such as "break", "hint", and "nop": */
if (idesc->type == IA64_TYPE_DYN)
{
if ((strcmp (idesc->name, "nop") == 0)
|| (strcmp (idesc->name, "hint") == 0)
|| (strcmp (idesc->name, "break") == 0))
insn_unit = required_unit;
else if (strcmp (idesc->name, "chk.s") == 0)

13
gas/testsuite/ChangeLog
View file

@ -1,3 +1,16 @@
2002-12-04 David Mosberger <davidm@hpl.hp.com>
* gas/ia64/opc-b.d: Update for instructions added by SDM2.1.
* gas/ia64/opc-b.s: Ditto.
* gas/ia64/opc-f.d: Ditto.
* gas/ia64/opc-f.s: Ditto.
* gas/ia64/opc-i.d: Ditto.
* gas/ia64/opc-i.s: Ditto.
* gas/ia64/opc-m.d: Ditto.
* gas/ia64/opc-m.s: Ditto.
* gas/ia64/opc-x.d: Ditto.
* gas/ia64/opc-x.s: Ditto.
2002-12-03 Richard Henderson <rth@redhat.com>
* gas/ia64/ldxmov-1.[ds]: New.

6
gas/testsuite/gas/ia64/opc-b.d
View file

@ -1012,3 +1012,9 @@ Disassembly of section .text:
2be0: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0
2be6: 00 00 00 00 10 00 nop\.b 0x0
2bec: 00 00 40 00 epc;;
2bf0: 16 f8 ff 0f 00 00 \[BBB\] break\.b 0x1ffff
2bf6: 00 00 00 02 10 e0 hint\.b 0x0
2bfc: ff 3f 04 20 hint\.b 0x1ffff
2c00: 1d 00 00 00 01 00 \[MFB\] nop\.m 0x0
2c06: 00 00 00 02 00 e0 nop\.f 0x0
2c0c: ff 3f 00 20 nop\.b 0x1ffff;;

7
gas/testsuite/gas/ia64/opc-b.s
View file

@ -824,3 +824,10 @@
{ .bbb; nop.b 0; nop.b 0; epc ;; }
.L1:
# instructions added by SDM2.1:
break.b 0x1ffff
hint.b @pause
hint.b 0x1ffff
nop.b 0x1ffff

9
gas/testsuite/gas/ia64/opc-f.d
View file

@ -1560,3 +1560,12 @@ Disassembly of section \.text:
2050: 1d 00 00 00 01 00 \[MFB\] nop\.m 0x0
2056: 00 00 00 02 00 00 nop\.f 0x0
205c: 00 00 00 20 nop\.b 0x0;;
2060: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0
2066: 00 00 00 03 00 00 hint\.f 0x0
206c: 00 00 00 20 nop\.b 0x0
2070: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0
2076: 00 00 00 03 00 00 hint\.f 0x0
207c: 00 00 00 20 nop\.b 0x0
2080: 1d 00 00 00 01 00 \[MFB\] nop\.m 0x0
2086: f0 ff 1f 03 00 00 hint\.f 0x1ffff
208c: 00 00 00 20 nop\.b 0x0;;

5
gas/testsuite/gas/ia64/opc-f.s
View file

@ -605,3 +605,8 @@ _start:
break.f 0
nop.f 0;;
# instructions added by SDM2.1:
hint.f 0
hint.f @pause
hint.f 0x1ffff

6
gas/testsuite/gas/ia64/opc-i.d
View file

@ -243,3 +243,9 @@ Disassembly of section \.text:
976: 30 20 18 84 03 60 mov\.ret\.dptk b3=r4,a70 <_start\+0xa70>
97c: 40 70 08 07 mov\.ret\.dptk\.imp b3=r4,a70 <_start\+0xa70>;;
\.\.\.
a70: 00 00 00 80 01 00 \[MII\] hint\.m 0x0
a76: 00 00 00 03 00 00 hint\.i 0x0
a7c: 00 00 06 00 hint\.i 0x0
a80: 0d 00 00 00 01 00 \[MFI\] nop\.m 0x0
a86: 00 00 00 02 00 e0 nop\.f 0x0
a8c: ff ff 07 08 hint\.i 0x1fffff;;

6
gas/testsuite/gas/ia64/opc-i.s
View file

@ -206,3 +206,9 @@ _start:
.space 240
.L6:
# instructions added by SDM2.1:
hint @pause
hint.i 0
hint.i @pause
hint.i 0x1fffff

36
gas/testsuite/gas/ia64/opc-m.d
View file

@ -1285,7 +1285,7 @@ Disassembly of section \.text:
1a96: f0 ff 1f 00 00 00 break\.m 0x1ffff
1a9c: 00 00 00 20 nop\.b 0x0
1aa0: 18 00 00 00 01 00 \[MMB\] nop\.m 0x0
1aa6: f0 ff 1f 00 00 00 break\.m 0x1ffff
1aa6: f0 ff 1f 02 00 00 nop\.m 0x1ffff
1aac: 00 00 00 20 nop\.b 0x0
1ab0: 18 20 18 0a 38 04 \[MMB\] probe\.r r4=r5,r6
1ab6: 40 30 14 72 08 00 probe\.w r4=r5,r6
@ -1323,6 +1323,36 @@ Disassembly of section \.text:
1b60: 18 20 00 0a 1a 04 \[MMB\] thash r4=r5
1b66: 40 00 14 36 08 00 ttag r4=r5
1b6c: 00 00 00 20 nop\.b 0x0
1b70: 19 20 00 0a 1e 04 \[MMB\] tpa r4=r5
1b70: 18 20 00 0a 1e 04 \[MMB\] tpa r4=r5
1b76: 40 00 14 3e 08 00 tak r4=r5
1b7c: 00 00 00 20 nop\.b 0x0;;
1b7c: 00 00 00 20 nop\.b 0x0
1b80: 18 00 00 80 01 00 \[MMB\] hint\.m 0x0
1b86: 00 00 00 03 00 00 hint\.m 0x0
1b8c: 00 00 00 20 nop\.b 0x0
1b90: 18 f8 ff 8f 01 00 \[MMB\] hint\.m 0x1ffff
1b96: 40 30 14 02 22 00 cmp8xchg16\.acq r4=\[r5\],r6,ar\.csd,ar\.ccv
1b9c: 00 00 00 20 nop\.b 0x0
1ba0: 18 20 18 0a 03 11 \[MMB\] cmp8xchg16\.acq\.nt1 r4=\[r5\],r6,ar\.csd,ar\.ccv
1ba6: 40 30 14 0e 22 00 cmp8xchg16\.acq\.nta r4=\[r5\],r6,ar\.csd,ar\.ccv
1bac: 00 00 00 20 nop\.b 0x0
1bb0: 18 20 18 0a 21 11 \[MMB\] cmp8xchg16\.rel r4=\[r5\],r6,ar\.csd,ar\.ccv
1bb6: 40 30 14 46 22 00 cmp8xchg16\.rel\.nt1 r4=\[r5\],r6,ar\.csd,ar\.ccv
1bbc: 00 00 00 20 nop\.b 0x0
1bc0: 18 20 18 0a 27 11 \[MMB\] cmp8xchg16\.rel\.nta r4=\[r5\],r6,ar\.csd,ar\.ccv
1bc6: 00 00 10 60 0c 00 fc\.i r4
1bcc: 00 00 00 20 nop\.b 0x0
1bd0: 18 20 00 0a 41 11 \[MMB\] ld16 r4,ar\.csd=\[r5\]
1bd6: 40 00 14 86 22 00 ld16\.nt1 r4,ar\.csd=\[r5\]
1bdc: 00 00 00 20 nop\.b 0x0
1be0: 18 20 00 0a 47 11 \[MMB\] ld16\.nta r4,ar\.csd=\[r5\]
1be6: 40 00 14 c2 22 00 ld16\.acq r4,ar\.csd=\[r5\]
1bec: 00 00 00 20 nop\.b 0x0
1bf0: 18 20 00 0a 63 11 \[MMB\] ld16\.acq\.nt1 r4,ar\.csd=\[r5\]
1bf6: 40 00 14 ce 22 00 ld16\.acq\.nta r4,ar\.csd=\[r5\]
1bfc: 00 00 00 20 nop\.b 0x0
1c00: 18 00 14 08 81 11 \[MMB\] st16 \[r4\]=r5,ar\.csd
1c06: 00 28 10 0e 23 00 st16\.nta \[r4\]=r5,ar\.csd
1c0c: 00 00 00 20 nop\.b 0x0
1c10: 19 00 14 08 a1 11 \[MMB\] st16\.rel \[r4\]=r5,ar\.csd
1c16: 00 28 10 4e 23 00 st16\.rel\.nta \[r4\]=r5,ar\.csd
1c1c: 00 00 00 20 nop\.b 0x0;;

32
gas/testsuite/gas/ia64/opc-m.s
View file

@ -1,7 +1,6 @@
.text
.type _start,@function
_start:
ld1 r4 = [r5]
ld1 r4 = [r5], r6
ld1 r4 = [r5], -256
@ -976,7 +975,7 @@ _start:
break.m 0x1ffff
nop.m 0
break.m 0x1ffff
nop.m 0x1ffff
probe.r r4 = r5, r6
probe.w r4 = r5, r6
@ -1007,3 +1006,32 @@ _start:
tpa r4 = r5
tak r4 = r5
# instructions added by SDM2.1:
hint.m 0
hint.m @pause
hint.m 0x1ffff
cmp8xchg16.acq r4 = [r5], r6, ar25, ar.ccv
cmp8xchg16.acq.nt1 r4 = [r5], r6, ar.csd, ar.ccv
cmp8xchg16.acq.nta r4 = [r5], r6, ar.csd, ar.ccv
cmp8xchg16.rel r4 = [r5], r6, ar.csd, ar.ccv
cmp8xchg16.rel.nt1 r4 = [r5], r6, ar.csd, ar.ccv
cmp8xchg16.rel.nta r4 = [r5], r6, ar.csd, ar.ccv
fc.i r4
ld16 r4, ar25 = [r5]
ld16.nt1 r4, ar.csd = [r5]
ld16.nta r4, ar.csd = [r5]
ld16.acq r4, ar25 = [r5]
ld16.acq.nt1 r4, ar.csd = [r5]
ld16.acq.nta r4, ar.csd = [r5]
st16 [r4] = r5, ar25
st16.nta [r4] = r5, ar.csd
st16.rel [r4] = r5, ar.csd
st16.rel.nta [r4] = r5, ar.csd

15
gas/testsuite/gas/ia64/opc-x.d
View file

@ -23,7 +23,16 @@ Disassembly of section .text:
4e: 00 60 04 00
52: 00 00 01 c0 ff ff \[MLX\] nop\.m 0x0
58: ff ff 7f 80 f0 f7 movl r4=0xffffffffffffffff
5e: ff 6f 05 00
5e: ff 6f 04 00
62: 00 00 01 80 90 78 \[MLX\] nop\.m 0x0
68: 56 34 12 80 f0 76 movl r4=0x1234567890abcdef;;
6e: 6d 66 00 00
68: 56 34 12 80 f0 76 movl r4=0x1234567890abcdef
6e: 6d 66 04 00
72: 00 00 01 00 00 00 \[MLX\] nop\.m 0x0
78: 00 00 00 00 00 00 hint\.x 0x0
7e: 06 00 04 00
82: 00 00 01 00 00 00 \[MLX\] nop\.m 0x0
88: 00 00 00 00 00 00 hint\.x 0x0
8e: 06 00 05 00
92: 00 00 01 c0 ff ff \[MLX\] nop\.m 0x0
98: ff ff 7f e0 ff ff hint\.x 0x3fffffffffffffff;;
9e: 07 08 00 00

7
gas/testsuite/gas/ia64/opc-x.s
View file

@ -4,7 +4,7 @@ _start:
break.x 0
break.x 0x3fffffffffffffff
nop.x 0
nop.x 0x3fffffffffffffff
@ -12,3 +12,8 @@ _start:
movl r4 = 0xffffffffffffffff
movl r4 = 0x1234567890abcdef
# instructions added by SDM2.1:
hint.x 0
hint.x @pause
hint.x 0x3fffffffffffffff

5
include/opcode/ChangeLog
View file

@ -1,3 +1,8 @@
2002-12-04 David Mosberger <davidm@hpl.hp.com>
* ia64.h: Fix copyright message.
(IA64_OPND_AR_CSD): New operand kind.
2002-12-03 Richard Henderson <rth@redhat.com>
* ia64.h (enum ia64_opnd): Add IA64_OPND_LDXMOV.

12
include/opcode/ia64.h
View file

@ -1,7 +1,6 @@
/* ia64.h -- Header file for ia64 opcode table
Copyright (C) 1998, 1999, 2002 David Mosberger-Tang <davidm@hpl.hp.com>
See the file HP-COPYRIGHT for additional information. */
Copyright (C) 1998, 1999, 2002 Free Software Foundation, Inc.
Contributed by David Mosberger-Tang <davidm@hpl.hp.com> */
#ifndef opcode_ia64_h
#define opcode_ia64_h
@ -39,13 +38,14 @@ enum ia64_unit
};
/* Changes to this enumeration must be propagated to the operand table in
bfd/cpu-ia64-opc.c
*/
bfd/cpu-ia64-opc.c
*/
enum ia64_opnd
{
IA64_OPND_NIL, /* no operand---MUST BE FIRST!*/
/* constants */
IA64_OPND_AR_CSD, /* application register csd (ar.csd) */
IA64_OPND_AR_CCV, /* application register ccv (ar.ccv) */
IA64_OPND_AR_PFS, /* application register pfs (ar.pfs) */
IA64_OPND_C1, /* the constant 1 */
@ -288,7 +288,7 @@ struct ia64_opcode
/* Used by ia64_find_next_opcode (). */
short ent_index;
/* Opcode dependencies. */
/* Opcode dependencies. */
const struct ia64_opcode_dependency *dependencies;
};

21
opcodes/ChangeLog
View file

@ -1,3 +1,24 @@
2002-12-04 David Mosberger <davidm@hpl.hp.com>
* ia64-opc-d.c (ia64_opcodes_d): Add "hint" instruction.
* ia64-opc-b.c: Add "hint.b" instruction.
* ia64-opc-f.c: Add "hint.f" instruction.
* ia64-opc-i.c: Add "hint.i" instruction.
* ia64-opc-m.c: Add "hint.m", "fc.i", "ld16", "st16", and
"cmp8xchg16" instructions.
* ia64-opc-x.c: Add "hint.x" instruction.
* ia64-opc.h (AR_CSD): New macro.
* ia64-ic.tbl: Update according to SDM2.1.
* ia64-raw.tbl: Ditto.
* ia64-waw.tbl: Ditto.
* ia64-gen.c (in_iclass): Handle "hint" like "nop".
(lookup_regindex): Recognize AR[FCR], AR[EFLAG], AR[CSD],
AR[SSD], AR[CFLG], AR[FSR], AR[FIR], and AR[FDR].
* ia64-asmtab.c: Regenerate.
2002-11-25 Aldy Hernandez <aldyh@redhat.com>
* ppc-opc.c: Remove evmwlssf, evmwlssfa, evmwlsmf, evmwlsmfa,

11815
opcodes/ia64-asmtab.c
View file

File diff suppressed because it is too large Load diff

21
opcodes/ia64-gen.c
View file

@ -1061,10 +1061,11 @@ in_iclass (struct ia64_opcode *idesc, struct iclass *ic,
&& (idesc->name[len] == '\0'
|| idesc->name[len] == '.'));
/* All break and nop variations must match exactly. */
/* All break, nop, and hint variations must match exactly. */
if (resolved &&
(strcmp (ic->name, "break") == 0
|| strcmp (ic->name, "nop") == 0))
|| strcmp (ic->name, "nop") == 0
|| strcmp (ic->name, "hint") == 0))
resolved = strcmp (ic->name, idesc->name) == 0;
/* Assume restrictions in the FORMAT/FIELD negate resolution,
@ -1257,6 +1258,22 @@ lookup_regindex (const char *name, int specifier)
return 18;
else if (strstr (name, "[RNAT]"))
return 19;
else if (strstr (name, "[FCR]"))
return 21;
else if (strstr (name, "[EFLAG]"))
return 24;
else if (strstr (name, "[CSD]"))
return 25;
else if (strstr (name, "[SSD]"))
return 26;
else if (strstr (name, "[CFLG]"))
return 27;
else if (strstr (name, "[FSR]"))
return 28;
else if (strstr (name, "[FIR]"))
return 29;
else if (strstr (name, "[FDR]"))
return 30;
else if (strstr (name, "[CCV]"))
return 32;
else if (strstr (name, "[ITC]"))

26
opcodes/ia64-ic.tbl
View file

@ -3,7 +3,7 @@ all; IC:predicatable-instructions, IC:unpredicatable-instructions
branches; IC:indirect-brs, IC:ip-rel-brs
cfm-readers; IC:fr-readers, IC:fr-writers, IC:gr-readers, IC:gr-writers, IC:mod-sched-brs, IC:predicatable-instructions, IC:pr-writers, alloc, br.call, brl.call, br.ret, cover, loadrs, rfi, IC:chk-a, invala.e
chk-a; chk.a.clr, chk.a.nc
cmpxchg; cmpxchg1, cmpxchg2, cmpxchg4, cmpxchg8
cmpxchg; cmpxchg1, cmpxchg2, cmpxchg4, cmpxchg8, cmp8xchg16
czx; czx1, czx2
fcmp-s0; fcmp[Field(sf)==s0]
fcmp-s1; fcmp[Field(sf)==s1]
@ -29,7 +29,7 @@ indirect-brp; brp[Format in {B7}]
indirect-brs; br.call[Format in {B5}], br.cond[Format in {B4}], br.ia, br.ret
invala-all; invala[Format in {M24}], invala.e
ip-rel-brs; IC:mod-sched-brs, br.call[Format in {B3}], brl.call, brl.cond, br.cond[Format in {B1}], br.cloop
ld; ld1, ld2, ld4, ld8, ld8.fill
ld; ld1, ld2, ld4, ld8, ld8.fill, ld16
ld-a; ld1.a, ld2.a, ld4.a, ld8.a
ld-all-postinc; IC:ld[Format in {M2 M3}], IC:ldfp[Format in {M12}], IC:ldf[Format in {M7 M8}]
ld-c; IC:ld-c-nc, IC:ld-c-clr
@ -71,8 +71,15 @@ mov-from-AR; IC:mov-from-AR-M, IC:mov-from-AR-I, IC:mov-from-AR-IM
mov-from-AR-BSP; IC:mov-from-AR-M[Field(ar3) == BSP]
mov-from-AR-BSPSTORE; IC:mov-from-AR-M[Field(ar3) == BSPSTORE]
mov-from-AR-CCV; IC:mov-from-AR-M[Field(ar3) == CCV]
mov-from-AR-CFLG; IC:mov-from-AR-M[Field(ar3) == CFLG]
mov-from-AR-CSD; IC:mov-from-AR-M[Field(ar3) == CSD]
mov-from-AR-EC; IC:mov-from-AR-I[Field(ar3) == EC]
mov-from-AR-EFLAG; IC:mov-from-AR-M[Field(ar3) == EFLAG]
mov-from-AR-FCR; IC:mov-from-AR-M[Field(ar3) == FCR]
mov-from-AR-FDR; IC:mov-from-AR-M[Field(ar3) == FDR]
mov-from-AR-FIR; IC:mov-from-AR-M[Field(ar3) == FIR]
mov-from-AR-FPSR; IC:mov-from-AR-M[Field(ar3) == FPSR]
mov-from-AR-FSR; IC:mov-from-AR-M[Field(ar3) == FSR]
mov-from-AR-I; mov_ar[Format in {I28}]
mov-from-AR-ig; IC:mov-from-AR-IM[Field(ar3) in {48-63 112-127}]
mov-from-AR-IM; mov_ar[Format in {I28 M31}]
@ -84,6 +91,7 @@ mov-from-AR-PFS; IC:mov-from-AR-I[Field(ar3) == PFS]
mov-from-AR-RNAT; IC:mov-from-AR-M[Field(ar3) == RNAT]
mov-from-AR-RSC; IC:mov-from-AR-M[Field(ar3) == RSC]
mov-from-AR-rv; IC:none
mov-from-AR-SSD; IC:mov-from-AR-M[Field(ar3) == SSD]
mov-from-AR-UNAT; IC:mov-from-AR-M[Field(ar3) == UNAT]
mov-from-BR; mov_br[Format in {I22}]
mov-from-CR; mov_cr[Format in {M33}]
@ -129,8 +137,15 @@ mov-to-AR; IC:mov-to-AR-M, IC:mov-to-AR-I
mov-to-AR-BSP; IC:mov-to-AR-M[Field(ar3) == BSP]
mov-to-AR-BSPSTORE; IC:mov-to-AR-M[Field(ar3) == BSPSTORE]
mov-to-AR-CCV; IC:mov-to-AR-M[Field(ar3) == CCV]
mov-to-AR-CFLG; IC:mov-to-AR-M[Field(ar3) == CFLG]
mov-to-AR-CSD; IC:mov-to-AR-M[Field(ar3) == CSD]
mov-to-AR-EC; IC:mov-to-AR-I[Field(ar3) == EC]
mov-to-AR-EFLAG; IC:mov-to-AR-M[Field(ar3) == EFLAG]
mov-to-AR-FCR; IC:mov-to-AR-M[Field(ar3) == FCR]
mov-to-AR-FDR; IC:mov-to-AR-M[Field(ar3) == FDR]
mov-to-AR-FIR; IC:mov-to-AR-M[Field(ar3) == FIR]
mov-to-AR-FPSR; IC:mov-to-AR-M[Field(ar3) == FPSR]
mov-to-AR-FSR; IC:mov-to-AR-M[Field(ar3) == FSR]
mov-to-AR-gr; IC:mov-to-AR-M[Format in {M29}], IC:mov-to-AR-I[Format in {I26}]
mov-to-AR-I; mov_ar[Format in {I26 I27}]
mov-to-AR-ig; IC:mov-to-AR-IM[Field(ar3) in {48-63 112-127}]
@ -142,6 +157,7 @@ mov-to-AR-M; mov_ar[Format in {M29 M30}]
mov-to-AR-PFS; IC:mov-to-AR-I[Field(ar3) == PFS]
mov-to-AR-RNAT; IC:mov-to-AR-M[Field(ar3) == RNAT]
mov-to-AR-RSC; IC:mov-to-AR-M[Field(ar3) == RSC]
mov-to-AR-SSD; IC:mov-to-AR-M[Field(ar3) == SSD]
mov-to-AR-UNAT; IC:mov-to-AR-M[Field(ar3) == UNAT]
mov-to-BR; mov_br[Format in {I21}]
mov-to-CR; mov_cr[Format in {M32}]
@ -200,8 +216,8 @@ pr-gen-writers-int; cmp, cmp4, tbit, tnat
pr-norm-writers-fp; IC:pr-gen-writers-fp[Field(ctype)==]
pr-norm-writers-int; IC:pr-gen-writers-int[Field(ctype)==]
pr-or-writers; IC:pr-gen-writers-int[Field(ctype) in {or orcm}], IC:pr-gen-writers-int[Field(ctype) in {or.andcm and.orcm}]
pr-readers-br; br.call, br.cond, brl.call, brl.cond, br.ret, br.wexit, br.wtop, break.b, nop.b, IC:ReservedBQP
pr-readers-nobr-nomovpr; add, addl, addp4, adds, and, andcm, break.f, break.i, break.m, break.x, chk.s, IC:chk-a, cmp, cmp4, IC:cmpxchg, IC:czx, dep, extr, IC:fp-arith, IC:fp-non-arith, fc, fchkf, fclrf, fcmp, IC:fetchadd, fpcmp, fsetc, fwb, getf, IC:invala-all, itc.i, itc.d, itr.i, itr.d, IC:ld, IC:ldf, IC:ldfp, IC:lfetch-all, mf, IC:mix, IC:mov-from-AR-M, IC:mov-from-AR-IM, IC:mov-from-AR-I, IC:mov-to-AR-M, IC:mov-to-AR-I, IC:mov-to-AR-IM, IC:mov-to-BR, IC:mov-from-BR, IC:mov-to-CR, IC:mov-from-CR, IC:mov-to-IND, IC:mov-from-IND, IC:mov-ip, IC:mov-to-PSR-l, IC:mov-to-PSR-um, IC:mov-from-PSR, IC:mov-from-PSR-um, movl, IC:mux, nop.f, nop.i, nop.m, nop.x, or, IC:pack, IC:padd, IC:pavg, IC:pavgsub, IC:pcmp, IC:pmax, IC:pmin, IC:pmpy, IC:pmpyshr, popcnt, IC:probe-all, IC:psad, IC:pshl, IC:pshladd, IC:pshr, IC:pshradd, IC:psub, ptc.e, ptc.g, ptc.ga, ptc.l, ptr.d, ptr.i, IC:ReservedQP, rsm, setf, shl, shladd, shladdp4, shr, shrp, srlz.i, srlz.d, ssm, IC:st, IC:stf, sub, sum, IC:sxt, sync, tak, tbit, thash, tnat, tpa, ttag, IC:unpack, IC:xchg, xma, xmpy, xor, IC:zxt
pr-readers-br; br.call, br.cond, brl.call, brl.cond, br.ret, br.wexit, br.wtop, break.b, hint.b, nop.b, IC:ReservedBQP
pr-readers-nobr-nomovpr; add, addl, addp4, adds, and, andcm, break.f, break.i, break.m, break.x, chk.s, IC:chk-a, cmp, cmp4, IC:cmpxchg, IC:czx, dep, extr, IC:fp-arith, IC:fp-non-arith, fc, fchkf, fclrf, fcmp, IC:fetchadd, fpcmp, fsetc, fwb, getf, hint.f, hint.i, hint.m, hint.x, IC:invala-all, itc.i, itc.d, itr.i, itr.d, IC:ld, IC:ldf, IC:ldfp, IC:lfetch-all, mf, IC:mix, IC:mov-from-AR-M, IC:mov-from-AR-IM, IC:mov-from-AR-I, IC:mov-to-AR-M, IC:mov-to-AR-I, IC:mov-to-AR-IM, IC:mov-to-BR, IC:mov-from-BR, IC:mov-to-CR, IC:mov-from-CR, IC:mov-to-IND, IC:mov-from-IND, IC:mov-ip, IC:mov-to-PSR-l, IC:mov-to-PSR-um, IC:mov-from-PSR, IC:mov-from-PSR-um, movl, IC:mux, nop.f, nop.i, nop.m, nop.x, or, IC:pack, IC:padd, IC:pavg, IC:pavgsub, IC:pcmp, IC:pmax, IC:pmin, IC:pmpy, IC:pmpyshr, popcnt, IC:probe-all, IC:psad, IC:pshl, IC:pshladd, IC:pshr, IC:pshradd, IC:psub, ptc.e, ptc.g, ptc.ga, ptc.l, ptr.d, ptr.i, IC:ReservedQP, rsm, setf, shl, shladd, shladdp4, shr, shrp, srlz.i, srlz.d, ssm, IC:st, IC:stf, sub, sum, IC:sxt, sync, tak, tbit, thash, tnat, tpa, ttag, IC:unpack, IC:xchg, xma, xmpy, xor, IC:zxt
pr-unc-writers-fp; IC:pr-gen-writers-fp[Field(ctype)==unc]+11, fprcpa+11, fprsqrta+11, frcpa+11, frsqrta+11
pr-unc-writers-int; IC:pr-gen-writers-int[Field(ctype)==unc]+11
pr-writers; IC:pr-writers-int, IC:pr-writers-fp
@ -222,7 +238,7 @@ ReservedBQP; -+15
ReservedQP; -+16
rse-readers; alloc, br.call, br.ia, br.ret, brl.call, cover, flushrs, loadrs, IC:mov-from-AR-BSP, IC:mov-from-AR-BSPSTORE, IC:mov-to-AR-BSPSTORE, IC:mov-from-AR-RNAT, IC:mov-to-AR-RNAT, rfi
rse-writers; alloc, br.call, br.ia, br.ret, brl.call, cover, flushrs, loadrs, IC:mov-to-AR-BSPSTORE, rfi
st; st1, st2, st4, st8, st8.spill
st; st1, st2, st4, st8, st8.spill, st16
st-postinc; IC:stf[Format in {M10}], IC:st[Format in {M5}]
stf; stfs, stfd, stfe, stf8, stf.spill
sxt; sxt1, sxt2, sxt4

3
opcodes/ia64-opc-b.c
View file

@ -189,7 +189,7 @@ struct ia64_opcode ia64_opcodes_b[] =
#undef BR
#undef BRP
#undef BRT
{"cover", B0, OpX6 (0, 0x02), {0, }, NO_PRED | LAST | MOD_RRBS, 0, NULL},
{"clrrrb", B0, OpX6 (0, 0x04), {0, }, NO_PRED | LAST | MOD_RRBS, 0, NULL},
{"clrrrb.pr", B0, OpX6 (0, 0x05), {0, }, NO_PRED | LAST | MOD_RRBS, 0, NULL},
@ -238,6 +238,7 @@ struct ia64_opcode ia64_opcodes_b[] =
#undef BRP
{"nop.b", B0, OpX6 (2, 0x00), {IMMU21}, EMPTY},
{"hint.b", B0, OpX6 (2, 0x01), {IMMU21}, EMPTY},
#define BR(a,b) \
B0, OpBtypePaWhaDPr (4, 0, a, 0, b, 0), {TGT25c}, PSEUDO, 0, NULL

1
opcodes/ia64-opc-d.c
View file

@ -25,6 +25,7 @@ struct ia64_opcode ia64_opcodes_d[] =
{"add", IA64_TYPE_DYN, 1, 0, 0, {IA64_OPND_R1, IA64_OPND_IMM14, IA64_OPND_R3}, 0, 0, NULL},
{"break", IA64_TYPE_DYN, 0, 0, 0, {IA64_OPND_IMMU21}, 0, 0, NULL},
{"chk.s", IA64_TYPE_DYN, 0, 0, 0, {IA64_OPND_R2, IA64_OPND_TGT25b}, 0, 0, NULL},
{"hint", IA64_TYPE_DYN, 0, 0, 0, {IA64_OPND_IMMU21}, 0, 0, NULL},
{"mov", IA64_TYPE_DYN, 1, 0, 0, {IA64_OPND_R1, IA64_OPND_AR3}, 0, 0, NULL},
{"mov", IA64_TYPE_DYN, 1, 0, 0, {IA64_OPND_AR3, IA64_OPND_IMM8}, 0, 0, NULL},
{"mov", IA64_TYPE_DYN, 1, 0, 0, {IA64_OPND_AR3, IA64_OPND_R2}, 0, 0, NULL},

7
opcodes/ia64-opc-f.c
View file

@ -36,6 +36,7 @@
#define bXb(x) (((ia64_insn) ((x) & 0x1)) << 33)
#define bX2(x) (((ia64_insn) ((x) & 0x3)) << 34)
#define bX6(x) (((ia64_insn) ((x) & 0x3f)) << 27)
#define bY(x) (((ia64_insn) ((x) & 0x1)) << 26)
#define mF2 bF2 (-1)
#define mF4 bF4 (-1)
@ -48,6 +49,7 @@
#define mXb bXb (-1)
#define mX2 bX2 (-1)
#define mX6 bX6 (-1)
#define mY bY (-1)
#define OpXa(a,b) (bOp (a) | bXa (b)), (mOp | mXa)
#define OpXaSf(a,b,c) (bOp (a) | bXa (b) | bSf (c)), (mOp | mXa | mSf)
@ -69,6 +71,8 @@
(bOp (a) | bXb (b) | bQ (c) | bSf (d)), (mOp | mXb | mQ | mSf)
#define OpXbX6(a,b,c) \
(bOp (a) | bXb (b) | bX6 (c)), (mOp | mXb | mX6)
#define OpXbX6Y(a,b,c,d) \
(bOp (a) | bXb (b) | bX6 (c) | bY (d)), (mOp | mXb | mX6 | mY)
#define OpXbX6F2(a,b,c,d) \
(bOp (a) | bXb (b) | bX6 (c) | bF2 (d)), (mOp | mXb | mX6 | mF2)
#define OpXbX6Sf(a,b,c,d) \
@ -177,7 +181,8 @@ struct ia64_opcode ia64_opcodes_f[] =
{"fchkf.s3", f0, OpXbX6Sf (0, 0, 0x08, 3), {TGT25}, EMPTY},
{"break.f", f0, OpXbX6 (0, 0, 0x00), {IMMU21}, EMPTY},
{"nop.f", f0, OpXbX6 (0, 0, 0x01), {IMMU21}, EMPTY},
{"nop.f", f0, OpXbX6Y (0, 0, 0x01, 0), {IMMU21}, EMPTY},
{"hint.f", f0, OpXbX6Y (0, 0, 0x01, 1), {IMMU21}, EMPTY},
{"fprcpa.s0", f2, OpXbQSf (1, 1, 0, 0), {F1, P2, F2, F3}, EMPTY},
{"fprcpa", f2, OpXbQSf (1, 1, 0, 0), {F1, P2, F2, F3}, PSEUDO, 0, NULL},

5
opcodes/ia64-opc-i.c
View file

@ -86,6 +86,8 @@
#define OpX3(a,b) (bOp (a) | bX3 (b)), (mOp | mX3)
#define OpX3X6(a,b,c) (bOp (a) | bX3 (b) | bX6(c)), \
(mOp | mX3 | mX6)
#define OpX3X6Yb(a,b,c,d) (bOp (a) | bX3 (b) | bX6(c) | bYb(d)), \
(mOp | mX3 | mX6 | mYb)
#define OpX3XbIhWh(a,b,c,d,e) \
(bOp (a) | bX3 (b) | bXb (c) | bIh (d) | bWh (e)), \
(mOp | mX3 | mXb | mIh | mWh)
@ -102,7 +104,8 @@ struct ia64_opcode ia64_opcodes_i[] =
/* I-type instruction encodings (sorted according to major opcode). */
{"break.i", I0, OpX3X6 (0, 0, 0x00), {IMMU21}, X_IN_MLX, 0, NULL},
{"nop.i", I0, OpX3X6 (0, 0, 0x01), {IMMU21}, X_IN_MLX, 0, NULL},
{"nop.i", I0, OpX3X6Yb (0, 0, 0x01, 0), {IMMU21}, X_IN_MLX, 0, NULL},
{"hint.i", I0, OpX3X6Yb (0, 0, 0x01, 1), {IMMU21}, X_IN_MLX, 0, NULL},
{"chk.s.i", I0, OpX3 (0, 1), {R2, TGT25b}, EMPTY},
{"mov", I, OpX3XbIhWhTag13 (0, 7, 0, 0, 1, 0), {B1, R2}, PSEUDO, 0, NULL},

32
opcodes/ia64-opc-m.c
View file

@ -33,6 +33,8 @@
#define bX4(x) (((ia64_insn) ((x) & 0xf)) << 27)
#define bX6a(x) (((ia64_insn) ((x) & 0x3f)) << 30)
#define bX6b(x) (((ia64_insn) ((x) & 0x3f)) << 27)
#define bX7(x) (((ia64_insn) ((x) & 0x1)) << 36) /* note: alias for bM() */
#define bY(x) (((ia64_insn) ((x) & 0x1)) << 26)
#define bHint(x) (((ia64_insn) ((x) & 0x3)) << 28)
#define mM bM (-1)
@ -42,15 +44,21 @@
#define mX4 bX4 (-1)
#define mX6a bX6a (-1)
#define mX6b bX6b (-1)
#define mX7 bX7 (-1)
#define mY bY (-1)
#define mHint bHint (-1)
#define OpX3(a,b) (bOp (a) | bX3 (b)), (mOp | mX3)
#define OpX3X6b(a,b,c) (bOp (a) | bX3 (b) | bX6b (c)), \
(mOp | mX3 | mX6b)
#define OpX3X6bX7(a,b,c,d) (bOp (a) | bX3 (b) | bX6b (c) | bX7 (d)), \
(mOp | mX3 | mX6b | mX7)
#define OpX3X4(a,b,c) (bOp (a) | bX3 (b) | bX4 (c)), \
(mOp | mX3 | mX4)
#define OpX3X4X2(a,b,c,d) (bOp (a) | bX3 (b) | bX4 (c) | bX2 (d)), \
(mOp | mX3 | mX4 | mX2)
#define OpX3X4X2Y(a,b,c,d,e) (bOp (a) | bX3 (b) | bX4 (c) | bX2 (d) | bY (e)), \
(mOp | mX3 | mX4 | mX2 | mY)
#define OpX6aHint(a,b,c) (bOp (a) | bX6a (b) | bHint (c)), \
(mOp | mX6a | mHint)
#define OpXX6aHint(a,b,c,d) (bOp (a) | bX (b) | bX6a (c) | bHint (d)), \
@ -88,7 +96,8 @@ struct ia64_opcode ia64_opcodes_m[] =
{"mov.m", M, OpX3X4X2 (0, 0, 8, 2), {AR3, IMM8}, EMPTY},
{"break.m", M0, OpX3X4X2 (0, 0, 0, 0), {IMMU21}, EMPTY},
{"nop.m", M0, OpX3X4X2 (0, 0, 1, 0), {IMMU21}, EMPTY},
{"nop.m", M0, OpX3X4X2Y (0, 0, 1, 0, 0), {IMMU21}, EMPTY},
{"hint.m", M0, OpX3X4X2Y (0, 0, 1, 0, 1), {IMMU21}, EMPTY},
{"sum", M0, OpX3X4 (0, 0, 4), {IMMU24}, EMPTY},
{"rum", M0, OpX3X4 (0, 0, 5), {IMMU24}, EMPTY},
@ -149,7 +158,8 @@ struct ia64_opcode ia64_opcodes_m[] =
{"chk.s.m", M0, OpX3 (1, 1), {R2, TGT25b}, EMPTY},
{"chk.s", M0, OpX3 (1, 3), {F2, TGT25b}, EMPTY},
{"fc", M0, OpX3X6b (1, 0, 0x30), {R3}, EMPTY},
{"fc", M0, OpX3X6bX7 (1, 0, 0x30, 0), {R3}, EMPTY},
{"fc.i", M0, OpX3X6bX7 (1, 0, 0x30, 1), {R3}, EMPTY},
{"ptc.e", M0, OpX3X6b (1, 0, 0x34), {R3}, PRIV, 0, NULL},
/* integer load */
@ -165,6 +175,9 @@ struct ia64_opcode ia64_opcodes_m[] =
{"ld8", M, OpMXX6aHint (4, 0, 0, 0x03, 0), {R1, MR3}, EMPTY},
{"ld8.nt1", M, OpMXX6aHint (4, 0, 0, 0x03, 1), {R1, MR3}, EMPTY},
{"ld8.nta", M, OpMXX6aHint (4, 0, 0, 0x03, 3), {R1, MR3}, EMPTY},
{"ld16", M2, OpMXX6aHint (4, 0, 1, 0x28, 0), {R1, AR_CSD, MR3}, EMPTY},
{"ld16.nt1", M2, OpMXX6aHint (4, 0, 1, 0x28, 1), {R1, AR_CSD, MR3}, EMPTY},
{"ld16.nta", M2, OpMXX6aHint (4, 0, 1, 0x28, 3), {R1, AR_CSD, MR3}, EMPTY},
{"ld1.s", M, OpMXX6aHint (4, 0, 0, 0x04, 0), {R1, MR3}, EMPTY},
{"ld1.s.nt1", M, OpMXX6aHint (4, 0, 0, 0x04, 1), {R1, MR3}, EMPTY},
{"ld1.s.nta", M, OpMXX6aHint (4, 0, 0, 0x04, 3), {R1, MR3}, EMPTY},
@ -225,6 +238,9 @@ struct ia64_opcode ia64_opcodes_m[] =
{"ld8.acq", M, OpMXX6aHint (4, 0, 0, 0x17, 0), {R1, MR3}, EMPTY},
{"ld8.acq.nt1", M, OpMXX6aHint (4, 0, 0, 0x17, 1), {R1, MR3}, EMPTY},
{"ld8.acq.nta", M, OpMXX6aHint (4, 0, 0, 0x17, 3), {R1, MR3}, EMPTY},
{"ld16.acq", M2, OpMXX6aHint (4, 0, 1, 0x2c, 0), {R1, AR_CSD, MR3}, EMPTY},
{"ld16.acq.nt1", M2, OpMXX6aHint (4, 0, 1, 0x2c, 1), {R1, AR_CSD, MR3}, EMPTY},
{"ld16.acq.nta", M2, OpMXX6aHint (4, 0, 1, 0x2c, 3), {R1, AR_CSD, MR3}, EMPTY},
{"ld8.fill", M, OpMXX6aHint (4, 0, 0, 0x1b, 0), {R1, MR3}, EMPTY},
{"ld8.fill.nt1", M, OpMXX6aHint (4, 0, 0, 0x1b, 1), {R1, MR3}, EMPTY},
{"ld8.fill.nta", M, OpMXX6aHint (4, 0, 0, 0x1b, 3), {R1, MR3}, EMPTY},
@ -392,6 +408,8 @@ struct ia64_opcode ia64_opcodes_m[] =
{"st4.nta", M, OpMXX6aHint (4, 0, 0, 0x32, 3), {MR3, R2}, EMPTY},
{"st8", M, OpMXX6aHint (4, 0, 0, 0x33, 0), {MR3, R2}, EMPTY},
{"st8.nta", M, OpMXX6aHint (4, 0, 0, 0x33, 3), {MR3, R2}, EMPTY},
{"st16", M, OpMXX6aHint (4, 0, 1, 0x30, 0), {MR3, R2, AR_CSD}, EMPTY},
{"st16.nta", M, OpMXX6aHint (4, 0, 1, 0x30, 3), {MR3, R2, AR_CSD}, EMPTY},
{"st1.rel", M, OpMXX6aHint (4, 0, 0, 0x34, 0), {MR3, R2}, EMPTY},
{"st1.rel.nta", M, OpMXX6aHint (4, 0, 0, 0x34, 3), {MR3, R2}, EMPTY},
{"st2.rel", M, OpMXX6aHint (4, 0, 0, 0x35, 0), {MR3, R2}, EMPTY},
@ -400,10 +418,13 @@ struct ia64_opcode ia64_opcodes_m[] =
{"st4.rel.nta", M, OpMXX6aHint (4, 0, 0, 0x36, 3), {MR3, R2}, EMPTY},
{"st8.rel", M, OpMXX6aHint (4, 0, 0, 0x37, 0), {MR3, R2}, EMPTY},
{"st8.rel.nta", M, OpMXX6aHint (4, 0, 0, 0x37, 3), {MR3, R2}, EMPTY},
{"st16.rel", M, OpMXX6aHint (4, 0, 1, 0x34, 0), {MR3, R2, AR_CSD}, EMPTY},
{"st16.rel.nta", M, OpMXX6aHint (4, 0, 1, 0x34, 3), {MR3, R2, AR_CSD}, EMPTY},
{"st8.spill", M, OpMXX6aHint (4, 0, 0, 0x3b, 0), {MR3, R2}, EMPTY},
{"st8.spill.nta", M, OpMXX6aHint (4, 0, 0, 0x3b, 3), {MR3, R2}, EMPTY},
#define CMPXCHG(c,h) M, OpMXX6aHint (4, 0, 1, c, h), {R1, MR3, R2, AR_CCV}, EMPTY
#define CMPXCHG16(c,h) M, OpMXX6aHint (4, 0, 1, c, h), {R1, MR3, R2, AR_CSD, AR_CCV}, EMPTY
{"cmpxchg1.acq", CMPXCHG (0x00, 0)},
{"cmpxchg1.acq.nt1", CMPXCHG (0x00, 1)},
{"cmpxchg1.acq.nta", CMPXCHG (0x00, 3)},
@ -416,6 +437,9 @@ struct ia64_opcode ia64_opcodes_m[] =
{"cmpxchg8.acq", CMPXCHG (0x03, 0)},
{"cmpxchg8.acq.nt1", CMPXCHG (0x03, 1)},
{"cmpxchg8.acq.nta", CMPXCHG (0x03, 3)},
{"cmp8xchg16.acq", CMPXCHG16 (0x20, 0)},
{"cmp8xchg16.acq.nt1", CMPXCHG16 (0x20, 1)},
{"cmp8xchg16.acq.nta", CMPXCHG16 (0x20, 3)},
{"cmpxchg1.rel", CMPXCHG (0x04, 0)},
{"cmpxchg1.rel.nt1", CMPXCHG (0x04, 1)},
{"cmpxchg1.rel.nta", CMPXCHG (0x04, 3)},
@ -428,7 +452,11 @@ struct ia64_opcode ia64_opcodes_m[] =
{"cmpxchg8.rel", CMPXCHG (0x07, 0)},
{"cmpxchg8.rel.nt1", CMPXCHG (0x07, 1)},
{"cmpxchg8.rel.nta", CMPXCHG (0x07, 3)},
{"cmp8xchg16.rel", CMPXCHG16 (0x24, 0)},
{"cmp8xchg16.rel.nt1", CMPXCHG16 (0x24, 1)},
{"cmp8xchg16.rel.nta", CMPXCHG16 (0x24, 3)},
#undef CMPXCHG
#undef CMPXCHG16
{"xchg1", M, OpMXX6aHint (4, 0, 1, 0x08, 0), {R1, MR3, R2}, EMPTY},
{"xchg1.nt1", M, OpMXX6aHint (4, 0, 1, 0x08, 1), {R1, MR3, R2}, EMPTY},
{"xchg1.nta", M, OpMXX6aHint (4, 0, 1, 0x08, 3), {R1, MR3, R2}, EMPTY},

9
opcodes/ia64-opc-x.c
View file

@ -34,6 +34,7 @@
#define bWha(x) (((ia64_insn) ((x) & 0x3)) << 33)
#define bX3(x) (((ia64_insn) ((x) & 0x7)) << 33)
#define bX6(x) (((ia64_insn) ((x) & 0x3f)) << 27)
#define bY(x) (((ia64_insn) ((x) & 0x1)) << 26)
#define mBtype bBtype (-1)
#define mD bD (-1)
@ -43,9 +44,12 @@
#define mWha bWha (-1)
#define mX3 bX3 (-1)
#define mX6 bX6 (-1)
#define mY bY (-1)
#define OpX3X6(a,b,c) (bOp (a) | bX3 (b) | bX6(c)), \
(mOp | mX3 | mX6)
#define OpX3X6Y(a,b,c,d) (bOp (a) | bX3 (b) | bX6(c) | bY(d)), \
(mOp | mX3 | mX6 | mY)
#define OpVc(a,b) (bOp (a) | bVc (b)), (mOp | mVc)
#define OpPaWhaD(a,b,c,d) \
(bOp (a) | bPa (b) | bWha (c) | bD (d)), (mOp | mPa | mWha | mD)
@ -58,8 +62,9 @@
struct ia64_opcode ia64_opcodes_x[] =
{
{"break.x", X0, OpX3X6 (0, 0, 0x00), {IMMU62}, 0, 0, NULL},
{"nop.x", X0, OpX3X6 (0, 0, 0x01), {IMMU62}, 0, 0, NULL},
{"break.x", X0, OpX3X6 (0, 0, 0x00), {IMMU62}, 0, 0, NULL},
{"nop.x", X0, OpX3X6Y (0, 0, 0x01, 0), {IMMU62}, 0, 0, NULL},
{"hint.x", X0, OpX3X6Y (0, 0, 0x01, 1), {IMMU62}, 0, 0, NULL},
{"movl", X, OpVc (6, 0), {R1, IMMU64}, 0, 0, NULL},
#define BRL(a,b) \
X0, OpBtypePaWhaDPr (0xC, 0, a, 0, b, 0), {TGT64}, PSEUDO, 0, NULL

1
opcodes/ia64-opc.h
View file

@ -44,6 +44,7 @@
#define AR_CCV IA64_OPND_AR_CCV
#define AR_PFS IA64_OPND_AR_PFS
#define AR_CSD IA64_OPND_AR_CSD
#define C1 IA64_OPND_C1
#define C8 IA64_OPND_C8
#define C16 IA64_OPND_C16

8
opcodes/ia64-raw.tbl
View file

@ -2,8 +2,14 @@ Resource Name; Writers; Readers; Semantics of Dependency
ALAT; chk.a.clr, IC:mem-readers-alat, IC:mem-writers, IC:invala-all; IC:mem-readers-alat, IC:mem-writers, IC:chk-a, invala.e; none
AR[BSP]; br.call, brl.call, br.ret, cover, IC:mov-to-AR-BSPSTORE, rfi; br.call, brl.call, br.ia, br.ret, cover, flushrs, loadrs, IC:mov-from-AR-BSP, rfi; impliedF
AR[BSPSTORE]; alloc, loadrs, flushrs, IC:mov-to-AR-BSPSTORE; alloc, br.ia, flushrs, IC:mov-from-AR-BSPSTORE; impliedF
AR[CFLG]; IC:mov-to-AR-CFLG; br.ia, IC:mov-from-AR-CFLG; impliedF
AR[CCV]; IC:mov-to-AR-CCV; br.ia, IC:cmpxchg, IC:mov-from-AR-CCV; impliedF
AR[CSD]; ld16, IC:mov-to-AR-CSD; br.ia, cmp8xchg16, IC:mov-from-AR-CSD, st16; impliedF
AR[EC]; IC:mod-sched-brs, br.ret, IC:mov-to-AR-EC; br.call, brl.call, br.ia, IC:mod-sched-brs, IC:mov-from-AR-EC; impliedF
AR[EFLAG]; IC:mov-to-AR-EFLAG; br.ia, IC:mov-from-AR-EFLAG; impliedF
AR[FCR]; IC:mov-to-AR-FCR; br.ia, IC:mov-from-AR-FCR; impliedF
AR[FDR]; IC:mov-to-AR-FDR; br.ia, IC:mov-from-AR-FDR; impliedF
AR[FIR]; IC:mov-to-AR-FIR; br.ia, IC:mov-from-AR-FIR; impliedF
AR[FPSR].sf0.controls; IC:mov-to-AR-FPSR, fsetc.s0; br.ia, IC:fp-arith-s0, IC:fcmp-s0, IC:fpcmp-s0, fsetc, IC:mov-from-AR-FPSR; impliedF
AR[FPSR].sf1.controls; IC:mov-to-AR-FPSR, fsetc.s1; br.ia, IC:fp-arith-s1, IC:fcmp-s1, IC:fpcmp-s1, IC:mov-from-AR-FPSR; impliedF
AR[FPSR].sf2.controls; IC:mov-to-AR-FPSR, fsetc.s2; br.ia, IC:fp-arith-s2, IC:fcmp-s2, IC:fpcmp-s2, IC:mov-from-AR-FPSR; impliedF
@ -14,6 +20,7 @@ AR[FPSR].sf2.flags; IC:fp-arith-s2, fclrf.s2, IC:fcmp-s2, IC:fpcmp-s2, IC:mov-to
AR[FPSR].sf3.flags; IC:fp-arith-s3, fclrf.s3, IC:fcmp-s3, IC:fpcmp-s3, IC:mov-to-AR-FPSR; br.ia, fchkf.s3, IC:mov-from-AR-FPSR; impliedF
AR[FPSR].traps; IC:mov-to-AR-FPSR; br.ia, IC:fp-arith, fchkf, fcmp, fpcmp, IC:mov-from-AR-FPSR; impliedF
AR[FPSR].rv; IC:mov-to-AR-FPSR; br.ia, IC:fp-arith, fchkf, fcmp, fpcmp, IC:mov-from-AR-FPSR; impliedF
AR[FSR]; IC:mov-to-AR-FSR; br.ia, IC:mov-from-AR-FSR; impliedF
AR[ITC]; IC:mov-to-AR-ITC; br.ia, IC:mov-from-AR-ITC; impliedF
AR[K%], % in 0 - 7; IC:mov-to-AR-K+1; br.ia, IC:mov-from-AR-K+1; impliedF
AR[LC]; IC:mod-sched-brs-counted, IC:mov-to-AR-LC; br.ia, IC:mod-sched-brs-counted, IC:mov-from-AR-LC; impliedF
@ -22,6 +29,7 @@ AR[PFS]; IC:mov-to-AR-PFS; alloc, br.ia, epc, IC:mov-from-AR-PFS; impliedF
AR[PFS]; IC:mov-to-AR-PFS; br.ret; none
AR[RNAT]; alloc, flushrs, loadrs, IC:mov-to-AR-RNAT, IC:mov-to-AR-BSPSTORE; alloc, br.ia, flushrs, loadrs, IC:mov-from-AR-RNAT; impliedF
AR[RSC]; IC:mov-to-AR-RSC; alloc, br.ia, flushrs, loadrs, IC:mov-from-AR-RSC, IC:mov-from-AR-BSPSTORE, IC:mov-to-AR-RNAT, IC:mov-from-AR-RNAT, IC:mov-to-AR-BSPSTORE; impliedF
AR[SSD]; IC:mov-to-AR-SSD; br.ia, IC:mov-from-AR-SSD; impliedF
AR[UNAT]{%}, % in 0 - 63; IC:mov-to-AR-UNAT, st8.spill; br.ia, ld8.fill, IC:mov-from-AR-UNAT; impliedF
AR%, % in 8-15, 20, 22-23, 31, 33-35, 37-39, 41-43, 45-47, 67-111; IC:none; br.ia, IC:mov-from-AR-rv+1; none
AR%, % in 48-63, 112-127; IC:mov-to-AR-ig+1; br.ia, IC:mov-from-AR-ig+1; impliedF

7
opcodes/ia64-waw.tbl
View file

@ -3,7 +3,13 @@ ALAT; IC:mem-readers-alat, IC:mem-writers, chk.a.clr, IC:invala-all; IC:mem-read
AR[BSP]; br.call, brl.call, br.ret, cover, IC:mov-to-AR-BSPSTORE, rfi; br.call, brl.call, br.ret, cover, IC:mov-to-AR-BSPSTORE, rfi; impliedF
AR[BSPSTORE]; alloc, loadrs, flushrs, IC:mov-to-AR-BSPSTORE; alloc, loadrs, flushrs, IC:mov-to-AR-BSPSTORE; impliedF
AR[CCV]; IC:mov-to-AR-CCV; IC:mov-to-AR-CCV; impliedF
AR[CFLG]; IC:mov-to-AR-CFLG; IC:mov-to-AR-CFLG; impliedF
AR[CSD]; ld16, IC:mov-to-AR-CSD; ld16, IC:mov-to-AR-CSD; impliedF
AR[EC]; br.ret, IC:mod-sched-brs, IC:mov-to-AR-EC; br.ret, IC:mod-sched-brs, IC:mov-to-AR-EC; impliedF
AR[EFLAG]; mov-to-AR-EFLAG; mov-to-AR-EFLAG; impliedF
AR[FCR]; mov-to-AR-FCR; mov-to-AR-FCR; impliedF
AR[FDR]; mov-to-AR-FDR; mov-to-AR-FDR; impliedF
AR[FIR]; mov-to-AR-FIR; mov-to-AR-FIR; impliedF
AR[FPSR].sf0.controls; IC:mov-to-AR-FPSR, fsetc.s0; IC:mov-to-AR-FPSR, fsetc.s0; impliedF
AR[FPSR].sf1.controls; IC:mov-to-AR-FPSR, fsetc.s1; IC:mov-to-AR-FPSR, fsetc.s1; impliedF
AR[FPSR].sf2.controls; IC:mov-to-AR-FPSR, fsetc.s2; IC:mov-to-AR-FPSR, fsetc.s2; impliedF
@ -18,6 +24,7 @@ AR[FPSR].sf3.flags; IC:fp-arith-s3, IC:fcmp-s3, IC:fpcmp-s3; IC:fp-arith-s3, IC:
AR[FPSR].sf3.flags; fclrf.s3, IC:fcmp-s3, IC:fp-arith-s3, IC:fpcmp-s3, IC:mov-to-AR-FPSR; fclrf.s3, IC:mov-to-AR-FPSR; impliedF
AR[FPSR].rv; IC:mov-to-AR-FPSR; IC:mov-to-AR-FPSR; impliedF
AR[FPSR].traps; IC:mov-to-AR-FPSR; IC:mov-to-AR-FPSR; impliedF
AR[FSR]; IC:mov-to-AR-FSR; IC:mov-to-AR-FSR; impliedF
AR[ITC]; IC:mov-to-AR-ITC; IC:mov-to-AR-ITC; impliedF
AR[K%], % in 0 - 7; IC:mov-to-AR-K+1; IC:mov-to-AR-K+1; impliedF
AR[LC]; IC:mod-sched-brs-counted, IC:mov-to-AR-LC; IC:mod-sched-brs-counted, IC:mov-to-AR-LC; impliedF