x86: allow suffix-less movzw and 64-bit movzb
... just like is already the case for 16- and 32-bit movzb: I can't see
why omitting suffixes on this (and movs{b,w,l}) is not allowed, when it
is allowed for all other instructions where the suffix is redundant
with (one of) the operands.
This commit is contained in:
Jan Beulich
Jan Beulich
parent
9243100aef
commit
c07315e0c6
8 changed files with 108 additions and 80 deletions
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@ -1,3 +1,10 @@
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2016-07-01 Jan Beulich <jbeulich@suse.com>
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* testsuite/gas/i386/movz.s: New.
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* testsuite/gas/i386/movz32.d: New.
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* testsuite/gas/i386/movz64.d: New.
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* testsuite/gas/i386/i386.exp: Run new tests.
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2016-07-01 Jan Beulich <jbeulich@suse.com>
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* config/tc-i386.c (struct _i386_insn): New field memop1_string.
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@ -59,6 +59,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]]
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run_dump_test "amd"
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run_dump_test "katmai"
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run_dump_test "jump"
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run_dump_test "movz32"
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run_dump_test "relax-1"
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run_dump_test "relax-2"
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run_dump_test "ssemmx2"
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@ -507,6 +508,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
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run_dump_test "x86-64-segovr"
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run_list_test "x86-64-inval-seg" "-al"
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run_dump_test "x86-64-branch"
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run_dump_test "movz64"
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run_dump_test "x86-64-relax-1"
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run_dump_test "svme64"
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run_dump_test "x86-64-amdfam10"
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33
gas/testsuite/gas/i386/movz.s
Normal file
33
gas/testsuite/gas/i386/movz.s
Normal file
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@ -0,0 +1,33 @@
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.text
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movz:
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movzb %al,%ax
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movzb (%eax),%ax
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movzb %al,%eax
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movzb (%eax),%eax
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.ifdef x86_64
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movzb %al,%rax
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movzb (%rax),%rax
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.endif
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movzbw %al,%ax
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movzbw (%eax),%ax
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movzbl %al,%eax
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movzbl (%eax),%eax
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.ifdef x86_64
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movzbq %al,%rax
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movzbq (%rax),%rax
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.endif
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movzw %ax,%eax
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movzw (%eax),%eax
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.ifdef x86_64
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movzw %ax,%rax
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movzw (%rax),%rax
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.endif
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movzwl %ax,%eax
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movzwl (%eax),%eax
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.ifdef x86_64
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movzwq %ax,%rax
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movzwq (%rax),%rax
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.endif
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22
gas/testsuite/gas/i386/movz32.d
Normal file
22
gas/testsuite/gas/i386/movz32.d
Normal file
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@ -0,0 +1,22 @@
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#objdump: -dw
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#source: movz.s
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#name: x86 mov with zero-extend (32-bit object)
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.*: +file format .*
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Disassembly of section .text:
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0+ <movz>:
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[ ]*[a-f0-9]+: 66 0f b6 c0 * movzbw %al,%ax
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[ ]*[a-f0-9]+: 66 0f b6 00 * movzbw \(%eax\),%ax
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[ ]*[a-f0-9]+: 0f b6 c0 * movzbl %al,%eax
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[ ]*[a-f0-9]+: 0f b6 00 * movzbl \(%eax\),%eax
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[ ]*[a-f0-9]+: 66 0f b6 c0 * movzbw %al,%ax
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[ ]*[a-f0-9]+: 66 0f b6 00 * movzbw \(%eax\),%ax
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[ ]*[a-f0-9]+: 0f b6 c0 * movzbl %al,%eax
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[ ]*[a-f0-9]+: 0f b6 00 * movzbl \(%eax\),%eax
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[ ]*[a-f0-9]+: 0f b7 c0 * movzwl %ax,%eax
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[ ]*[a-f0-9]+: 0f b7 00 * movzwl \(%eax\),%eax
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[ ]*[a-f0-9]+: 0f b7 c0 * movzwl %ax,%eax
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[ ]*[a-f0-9]+: 0f b7 00 * movzwl \(%eax\),%eax
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#pass
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30
gas/testsuite/gas/i386/movz64.d
Normal file
30
gas/testsuite/gas/i386/movz64.d
Normal file
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@ -0,0 +1,30 @@
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#objdump: -dw
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#source: movz.s
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#name: x86 mov with zero-extend (64-bit object)
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.*: +file format .*
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Disassembly of section .text:
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0+ <movz>:
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[ ]*[a-f0-9]+: 66 0f b6 c0 * movzbw %al,%ax
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[ ]*[a-f0-9]+: 67 66 0f b6 00 * movzbw \(%eax\),%ax
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[ ]*[a-f0-9]+: 0f b6 c0 * movzbl %al,%eax
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[ ]*[a-f0-9]+: 67 0f b6 00 * movzbl \(%eax\),%eax
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[ ]*[a-f0-9]+: 48 0f b6 c0 * movzbq %al,%rax
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[ ]*[a-f0-9]+: 48 0f b6 00 * movzbq \(%rax\),%rax
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[ ]*[a-f0-9]+: 66 0f b6 c0 * movzbw %al,%ax
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[ ]*[a-f0-9]+: 67 66 0f b6 00 * movzbw \(%eax\),%ax
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[ ]*[a-f0-9]+: 0f b6 c0 * movzbl %al,%eax
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[ ]*[a-f0-9]+: 67 0f b6 00 * movzbl \(%eax\),%eax
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[ ]*[a-f0-9]+: 48 0f b6 c0 * movzbq %al,%rax
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[ ]*[a-f0-9]+: 48 0f b6 00 * movzbq \(%rax\),%rax
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[ ]*[a-f0-9]+: 0f b7 c0 * movzwl %ax,%eax
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[ ]*[a-f0-9]+: 67 0f b7 00 * movzwl \(%eax\),%eax
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[ ]*[a-f0-9]+: 48 0f b7 c0 * movzwq %ax,%rax
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[ ]*[a-f0-9]+: 48 0f b7 00 * movzwq \(%rax\),%rax
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[ ]*[a-f0-9]+: 0f b7 c0 * movzwl %ax,%eax
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[ ]*[a-f0-9]+: 67 0f b7 00 * movzwl \(%eax\),%eax
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[ ]*[a-f0-9]+: 48 0f b7 c0 * movzwq %ax,%rax
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[ ]*[a-f0-9]+: 48 0f b7 00 * movzwq \(%rax\),%rax
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#pass
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@ -1,3 +1,10 @@
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2016-07-01 Jan Beulich <jbeulich@suse.com>
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* i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
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(movzb): Adjust to cover all permitted suffixes.
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(movzw): New.
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* i386-tbl.h: Re-generate.
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2016-07-01 Jan Beulich <jbeulich@suse.com>
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* i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
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@ -74,18 +74,9 @@ movsx, 2, 0xfbf, None, 2, Cpu386, Modrm|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf
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movsx, 2, 0x63, None, 1, Cpu64, Modrm|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64|IntelSyntax, { Reg32|Dword|BaseIndex|Disp8|Disp32|Disp32S, Reg64 }
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movsxd, 2, 0x63, None, 1, Cpu64, Modrm|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg32|Dword|Unspecified|BaseIndex|Disp8|Disp32|Disp32S, Reg64 }
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// Move with zero extend. We can't remove "movzb" since existing
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// assembly codes may use it.
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movzb, 2, 0xfb6, None, 2, Cpu386, Modrm|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg8|Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 }
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// "movzbl" & "movzbw" should not be unified into "movzb" for
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// consistency with the sign extending moves above.
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movzbl, 2, 0xfb6, None, 2, Cpu386, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg8|Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32 }
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movzbw, 2, 0xfb6, None, 2, Cpu386, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg8|Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16 }
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movzwl, 2, 0xfb7, None, 2, Cpu386, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Word|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32 }
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// These instructions are not particulary useful, since the zero extend
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// 32->64 is implicit, but we can encode them.
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movzbq, 2, 0xfb6, None, 2, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg8|Byte|Unspecified|BaseIndex|Disp8|Disp32|Disp32S, Reg64 }
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movzwq, 2, 0xfb7, None, 2, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg16|Word|Unspecified|BaseIndex|Disp8|Disp32|Disp32S, Reg64 }
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// Move with zero extend.
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movzb, 2, 0xfb6, None, 2, Cpu386, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Reg8|Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 }
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movzw, 2, 0xfb7, None, 2, Cpu386, Modrm|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg16|Word|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32|Reg64 }
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// Intel Syntax next 2 insns (the 64-bit variants are not particulary
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// useful since the zero extend 32->64 is implicit, but we can encode them).
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movzx, 2, 0xfb6, None, 2, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Reg8|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 }
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@ -605,7 +605,7 @@ const insn_template i386_optab[] =
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
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{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
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0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0 },
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{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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@ -614,84 +614,20 @@ const insn_template i386_optab[] =
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{ { 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } },
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{ "movzbl", 2, 0xfb6, None, 2,
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{ "movzw", 2, 0xfb7, None, 2,
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{ { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
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{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1,
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1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0 },
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{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0,
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0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } },
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{ { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } },
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{ "movzbw", 2, 0xfb6, None, 2,
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{ { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
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{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1,
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1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0 },
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{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0,
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0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } },
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{ { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } },
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{ "movzwl", 2, 0xfb7, None, 2,
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{ { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
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{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1,
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1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0 },
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{ { { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
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0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } },
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{ { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } },
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{ "movzbq", 2, 0xfb6, None, 2,
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 } },
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{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1,
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1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0 },
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{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 1, 0, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0,
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0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } },
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{ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } },
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{ "movzwq", 2, 0xfb7, None, 2,
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1,
|
||||
1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0 },
|
||||
{ { { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 1, 0, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
|
||||
0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
{ { 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } },
|
||||
{ "movzx", 2, 0xfb6, None, 2,
|
||||
|
|
|
|||
Loading…
Reference in a new issue