2000-08-28 Kazu Hirata <kazu@hxi.com>
* tic30-dis.c: Fix formatting.
This commit is contained in:
parent
f0a58b0b8c
commit
bf830eae8f
2 changed files with 39 additions and 35 deletions
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@ -1,3 +1,7 @@
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2000-08-28 Kazu Hirata <kazu@hxi.com>
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* tic30-dis.c: Fix formatting.
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2000-08-27 Kazu Hirata <kazu@hxi.com>
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* sh-dis.c: Fix formatting.
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@ -1,5 +1,5 @@
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/* Disassembly routines for TMS320C30 architecture
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Copyright (C) 1998, 1999 Free Software Foundation, Inc.
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Copyright (C) 1998, 1999, 2000 Free Software Foundation, Inc.
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Contributed by Steven Haworth (steve@pm.cse.rmit.edu.au)
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This program is free software; you can redistribute it and/or modify
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@ -27,10 +27,10 @@
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#define PARALLEL_INSN 2
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/* Gets the type of instruction based on the top 2 or 3 bits of the
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instruction word. */
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instruction word. */
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#define GET_TYPE(insn) (insn & 0x80000000 ? insn & 0xC0000000 : insn & 0xE0000000)
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/* Instruction types. */
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/* Instruction types. */
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#define TWO_OPERAND_1 0x00000000
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#define TWO_OPERAND_2 0x40000000
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#define THREE_OPERAND 0x20000000
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@ -38,14 +38,14 @@
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#define MUL_ADDS 0x80000000
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#define BRANCHES 0x60000000
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/* Specific instruction id bits. */
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/* Specific instruction id bits. */
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#define NORMAL_IDEN 0x1F800000
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#define PAR_STORE_IDEN 0x3E000000
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#define MUL_ADD_IDEN 0x2C000000
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#define BR_IMM_IDEN 0x1F000000
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#define BR_COND_IDEN 0x1C3F0000
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/* Addressing modes. */
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/* Addressing modes. */
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#define AM_REGISTER 0x00000000
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#define AM_DIRECT 0x00200000
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#define AM_INDIRECT 0x00400000
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@ -56,15 +56,15 @@
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#define REG_AR0 0x08
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#define LDP_INSN 0x08700000
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/* TMS320C30 program counter for current instruction. */
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/* TMS320C30 program counter for current instruction. */
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static unsigned int _pc;
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struct instruction
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{
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int type;
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template *tm;
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partemplate *ptm;
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};
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{
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int type;
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template *tm;
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partemplate *ptm;
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};
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int get_tic30_instruction PARAMS ((unsigned long, struct instruction *));
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int print_two_operand
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@ -85,15 +85,14 @@ print_insn_tic30 (pc, info)
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disassemble_info *info;
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{
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unsigned long insn_word;
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struct instruction insn =
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{0, NULL, NULL};
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struct instruction insn = { 0, NULL, NULL };
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bfd_vma bufaddr = pc - info->buffer_vma;
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/* Obtain the current instruction word from the buffer. */
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/* Obtain the current instruction word from the buffer. */
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insn_word = (*(info->buffer + bufaddr) << 24) | (*(info->buffer + bufaddr + 1) << 16) |
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(*(info->buffer + bufaddr + 2) << 8) | *(info->buffer + bufaddr + 3);
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_pc = pc / 4;
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/* Get the instruction refered to by the current instruction word
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and print it out based on its type. */
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and print it out based on its type. */
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if (!get_tic30_instruction (insn_word, &insn))
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return -1;
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switch (GET_TYPE (insn_word))
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@ -249,7 +248,7 @@ print_two_operand (info, insn_word, insn)
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if (insn->tm->opcode_modifier == AddressMode)
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{
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int src_op, dest_op;
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/* Determine whether instruction is a store or a normal instruction. */
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/* Determine whether instruction is a store or a normal instruction. */
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if ((insn->tm->operand_types[1] & (Direct | Indirect)) == (Direct | Indirect))
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{
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src_op = 1;
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@ -260,14 +259,14 @@ print_two_operand (info, insn_word, insn)
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src_op = 0;
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dest_op = 1;
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}
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/* Get the destination register. */
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/* Get the destination register. */
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if (insn->tm->operands == 2)
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get_register_operand ((insn_word & 0x001F0000) >> 16, operand[dest_op]);
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/* Get the source operand based on addressing mode. */
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/* Get the source operand based on addressing mode. */
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switch (insn_word & AddressMode)
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{
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case AM_REGISTER:
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/* Check for the NOP instruction before getting the operand. */
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/* Check for the NOP instruction before getting the operand. */
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if ((insn->tm->operand_types[0] & NotReq) == 0)
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get_register_operand ((insn_word & 0x0000001F), operand[src_op]);
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break;
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@ -278,7 +277,7 @@ print_two_operand (info, insn_word, insn)
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get_indirect_operand ((insn_word & 0x0000FFFF), 2, operand[src_op]);
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break;
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case AM_IMM:
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/* Get the value of the immediate operand based on variable type. */
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/* Get the value of the immediate operand based on variable type. */
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switch (insn->tm->imm_arg_type)
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{
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case Imm_Float:
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@ -294,7 +293,7 @@ print_two_operand (info, insn_word, insn)
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default:
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return 0;
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}
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/* Handle special case for LDP instruction. */
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/* Handle special case for LDP instruction. */
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if ((insn_word & 0xFFFFFF00) == LDP_INSN)
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{
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strcpy (name, "ldp");
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@ -303,7 +302,7 @@ print_two_operand (info, insn_word, insn)
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}
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}
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}
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/* Handle case for stack and rotate instructions. */
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/* Handle case for stack and rotate instructions. */
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else if (insn->tm->operands == 1)
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{
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if (insn->tm->opcode_modifier == StackOp)
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@ -311,7 +310,7 @@ print_two_operand (info, insn_word, insn)
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get_register_operand ((insn_word & 0x001F0000) >> 16, operand[0]);
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}
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}
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/* Output instruction to stream. */
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/* Output instruction to stream. */
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info->fprintf_func (info->stream, " %s %s%c%s", name,
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operand[0][0] ? operand[0] : "",
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operand[1][0] ? ',' : ' ',
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@ -385,7 +384,7 @@ print_par_insn (info, insn_word, insn)
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if (insn->ptm == NULL)
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return 0;
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/* Parse out the names of each of the parallel instructions from the
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q_insn1_insn2 format. */
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q_insn1_insn2 format. */
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name1 = (char *) strdup (insn->ptm->name + 2);
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name2 = "";
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len = strlen (name1);
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@ -398,7 +397,7 @@ print_par_insn (info, insn_word, insn)
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break;
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}
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}
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/* Get the operands of the instruction based on the operand order. */
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/* Get the operands of the instruction based on the operand order. */
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switch (insn->ptm->oporder)
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{
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case OO_4op1:
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@ -500,14 +499,14 @@ print_branch (info, insn_word, insn)
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if (insn->tm == NULL)
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return 0;
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/* Get the operands for 24-bit immediate jumps. */
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/* Get the operands for 24-bit immediate jumps. */
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if (insn->tm->operand_types[0] & Imm24)
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{
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address = insn_word & 0x00FFFFFF;
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sprintf (operand[0], "0x%lX", address);
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print_label = 1;
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}
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/* Get the operand for the trap instruction. */
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/* Get the operand for the trap instruction. */
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else if (insn->tm->operand_types[0] & IVector)
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{
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address = insn_word & 0x0000001F;
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@ -516,7 +515,7 @@ print_branch (info, insn_word, insn)
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else
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{
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address = insn_word & 0x0000FFFF;
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/* Get the operands for the DB instructions. */
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/* Get the operands for the DB instructions. */
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if (insn->tm->operands == 2)
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{
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get_register_operand (((insn_word & 0x01C00000) >> 22) + REG_AR0, operand[0]);
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else
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get_register_operand (insn_word & 0x0000001F, operand[1]);
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}
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/* Get the operands for the standard branches. */
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/* Get the operands for the standard branches. */
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else if (insn->tm->operands == 1)
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{
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if (insn_word & PCRel)
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operand[0][0] ? operand[0] : "",
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operand[1][0] ? ',' : ' ',
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operand[1][0] ? operand[1] : "");
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/* Print destination of branch in relation to current symbol. */
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/* Print destination of branch in relation to current symbol. */
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if (print_label && info->symbols)
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{
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asymbol *sym = *info->symbols;
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@ -553,7 +552,7 @@ print_branch (info, insn_word, insn)
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if ((insn->tm->opcode_modifier == PCRel) && (insn_word & PCRel))
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{
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address = (_pc + 1 + (short) address) - ((sym->section->vma + sym->value) / 4);
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/* Check for delayed instruction, if so adjust destination. */
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/* Check for delayed instruction, if so adjust destination. */
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if (insn_word & 0x00200000)
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address += 2;
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}
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if (buffer == NULL)
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return 0;
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/* Determine which bits identify the sections of the indirect operand based on the
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size in bytes. */
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/* Determine which bits identify the sections of the indirect
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operand based on the size in bytes. */
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switch (size)
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{
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case 1:
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buffer[bufcnt] = current_ind->syntax[i];
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if (buffer[bufcnt - 1] == 'a' && buffer[bufcnt] == 'r')
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buffer[++bufcnt] = arnum + '0';
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if (buffer[bufcnt] == '(' && current_ind->displacement == DISP_REQUIRED)
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if (buffer[bufcnt] == '('
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&& current_ind->displacement == DISP_REQUIRED)
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{
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sprintf (&buffer[bufcnt + 1], "%u", disp);
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bufcnt += strlen (&buffer[bufcnt + 1]);
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