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2003-08-11 Michael Snyder <msnyder@redhat.com>

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* macl.s: New file.
        * macw.s: New file.
        * allinsn.exp: Add new tests for mac.w and mac.l.
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Michael Snyder 2003-08-11 19:36:23 +00:00
parent d1789acece
commit be8fb42bc5
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6
sim/testsuite/sim/sh/ChangeLog
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@ -1,3 +1,9 @@
2003-08-11 Michael Snyder <msnyder@redhat.com>
* macl.s: New file.
* macw.s: New file.
* allinsn.exp: Add new tests for mac.w and mac.l.
2003-07-25 Michael Snyder <msnyder@redhat.com>
* pshai.s, pshar.s, pshli.s, pshlr.s: New files.

2
sim/testsuite/sim/sh/allinsn.exp
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@ -24,6 +24,8 @@ if [istarget sh-*elf] {
run_sim_test fsqrt.s sh
run_sim_test fsub.s sh
run_sim_test ftrc.s sh
run_sim_test macl.s sh
run_sim_test macw.s sh
run_sim_test paddc.s shdsp
run_sim_test padd.s shdsp
run_sim_test pand.s shdsp

54
sim/testsuite/sim/sh/macl.s Normal file
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@ -0,0 +1,54 @@
# sh testcase for mac.l
# mach: all
# as(sh): -defsym sim_cpu=0
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
start
# force S-bit clear
clrs
init:
# Prime {MACL, MACH} to #1.
mov #1, r0
dmulu.l r0, r0
# Set up addresses.
mov.l pfour00, r0 ! 85
mov.l pfour12, r1 ! 17
test:
mac.l @r0+, @r1+
check:
# Check result.
assert_sreg 0, mach
assert_sreg 85*17+1, macl
# Ensure post-increment occurred.
assertreg0 four00+4
assertreg four12+4, r1
doubleinc:
mov.l pfour00, r0
mac.l @r0+, @r0+
assertreg0 four00+8
pass
exit 0
.align 1
four00:
.long 85
.long 2
four12:
.long 17
.long 3
.align 2
pfour00:
.long four00
pfour12:
.long four12

56
sim/testsuite/sim/sh/macw.s Normal file
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@ -0,0 +1,56 @@
# sh testcase for mac.w
# mach: all
# as(sh): -defsym sim_cpu=0
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
start
set_grs_a5a5
# Prime {MACL, MACH} to #1.
mov #1, r0
dmulu.l r0, r0
# Set up addresses.
mov.l pfour00, r0 ! 85
mov.l pfour12, r1 ! 17
test:
mac.w @r0+, @r1+ ! MAC = 85 * 17 + 1
check:
# Check result.
assert_sreg 0, mach
assert_sreg 85*17+1, macl
# Ensure post-increment occurred.
assertreg0 four00+2
assertreg four12+2, r1
doubleinc:
mov.l pfour00, r0
mac.w @r0+, @r0+
assertreg0 four00+4
set_greg 0xa5a5a5a5, r0
set_greg 0xa5a5a5a5, r1
test_grs_a5a5
pass
exit 0
.align 2
four00:
.word 85
.word 2
four12:
.word 17
.word 3
pfour00:
.long four00
pfour12:
.long four12