Namespace cleanup for the tic4x target. Replace s/c4x/tic4x/ and s/c3x/tic3x/. 2003 copyright update
This commit is contained in:
Svein Seldal
parent
36018d2e5a
commit
be33c5dd4d
19 changed files with 576 additions and 538 deletions
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@ -1,3 +1,11 @@
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2003-04-04 Svein E. Seldal <Svein.Seldal@solidas.com>
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* archures.c: Namespace cleanup. Rename bfd_mach_c3x to
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bfd_mach_tic3x and bfd_mach_c4x to bfd_mach_tic4x
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* bfd-in2.h: Regenerate
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* coff-tic4x.c: Namespace cleanup. Replace s/c4x/tic4x/
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* cpu-tic4x.c: Ditto
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2003-04-03 Nick Clifton <nickc@redhat.com>
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* peXXigen.c (_bfd_XXi_swap_scnhdr_out): Compute ps and ss
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@ -241,8 +241,8 @@ DESCRIPTION
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. bfd_arch_w65, {* WDC 65816 *}
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. bfd_arch_tic30, {* Texas Instruments TMS320C30 *}
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. bfd_arch_tic4x, {* Texas Instruments TMS320C3X/4X *}
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.#define bfd_mach_c3x 30
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.#define bfd_mach_c4x 40
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.#define bfd_mach_tic3x 30
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.#define bfd_mach_tic4x 40
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. bfd_arch_tic54x, {* Texas Instruments TMS320C54X *}
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. bfd_arch_tic80, {* TI TMS320c80 (MVP) *}
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. bfd_arch_v850, {* NEC V850 *}
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@ -1707,8 +1707,8 @@ enum bfd_architecture
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bfd_arch_w65, /* WDC 65816 */
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bfd_arch_tic30, /* Texas Instruments TMS320C30 */
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bfd_arch_tic4x, /* Texas Instruments TMS320C3X/4X */
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#define bfd_mach_c3x 30
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#define bfd_mach_c4x 40
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#define bfd_mach_tic3x 30
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#define bfd_mach_tic4x 40
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bfd_arch_tic54x, /* Texas Instruments TMS320C54X */
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bfd_arch_tic80, /* TI TMS320c80 (MVP) */
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bfd_arch_v850, /* NEC V850 */
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@ -1,6 +1,7 @@
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/* BFD back-end for TMS320C4X coff binaries.
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Copyright 1996, 1997, 1998, 1999, 2000, 2002
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Copyright 1996, 1997, 1998, 1999, 2000, 2002, 2003
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Free Software Foundation, Inc.
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Contributed by Michael Hayes (m.hayes@elec.canterbury.ac.nz)
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This file is part of BFD, the Binary File Descriptor library.
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@ -365,7 +366,7 @@ static const bfd_coff_backend_data ticoff1_swap_table =
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/* TI COFF v0, DOS tools (little-endian headers). */
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const bfd_target tic4x_coff0_vec =
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{
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"coff0-c4x", /* Name. */
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"coff0-tic4x", /* Name. */
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bfd_target_coff_flavour,
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BFD_ENDIAN_LITTLE, /* Data byte order is little. */
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BFD_ENDIAN_LITTLE, /* Header byte order is little (DOS tools). */
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@ -409,7 +410,7 @@ const bfd_target tic4x_coff0_vec =
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/* TI COFF v0, SPARC tools (big-endian headers). */
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const bfd_target tic4x_coff0_beh_vec =
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{
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"coff0-beh-c4x", /* Name. */
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"coff0-beh-tic4x", /* Name. */
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bfd_target_coff_flavour,
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BFD_ENDIAN_LITTLE, /* Data byte order is little. */
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BFD_ENDIAN_BIG, /* Header byte order is big. */
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@ -454,7 +455,7 @@ const bfd_target tic4x_coff0_beh_vec =
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/* TI COFF v1, DOS tools (little-endian headers). */
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const bfd_target tic4x_coff1_vec =
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{
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"coff1-c4x", /* Name. */
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"coff1-tic4x", /* Name. */
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bfd_target_coff_flavour,
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BFD_ENDIAN_LITTLE, /* Data byte order is little. */
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BFD_ENDIAN_LITTLE, /* Header byte order is little (DOS tools). */
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@ -499,7 +500,7 @@ const bfd_target tic4x_coff1_vec =
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/* TI COFF v1, SPARC tools (big-endian headers). */
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const bfd_target tic4x_coff1_beh_vec =
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{
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"coff1-beh-c4x", /* Name. */
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"coff1-beh-tic4x", /* Name. */
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bfd_target_coff_flavour,
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BFD_ENDIAN_LITTLE, /* Data byte order is little. */
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BFD_ENDIAN_BIG, /* Header byte order is big. */
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@ -544,7 +545,7 @@ const bfd_target tic4x_coff1_beh_vec =
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/* TI COFF v2, TI DOS tools output (little-endian headers). */
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const bfd_target tic4x_coff2_vec =
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{
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"coff2-c4x", /* Name. */
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"coff2-tic4x", /* Name. */
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bfd_target_coff_flavour,
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BFD_ENDIAN_LITTLE, /* Data byte order is little. */
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BFD_ENDIAN_LITTLE, /* Header byte order is little (DOS tools). */
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@ -589,7 +590,7 @@ const bfd_target tic4x_coff2_vec =
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/* TI COFF v2, TI SPARC tools output (big-endian headers). */
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const bfd_target tic4x_coff2_beh_vec =
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{
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"coff2-beh-c4x", /* Name. */
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"coff2-beh-tic4x", /* Name. */
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bfd_target_coff_flavour,
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BFD_ENDIAN_LITTLE, /* Data byte order is little. */
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BFD_ENDIAN_BIG, /* Header byte order is big. */
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@ -1,5 +1,5 @@
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/* bfd back-end for TMS320C[34]x support
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Copyright 1996, 1997, 2002 Free Software Foundation, Inc.
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Copyright 1996, 1997, 2002, 2003 Free Software Foundation, Inc.
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Contributed by Michael Hayes (m.hayes@elec.canterbury.ac.nz)
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@ -23,12 +23,12 @@
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#include "sysdep.h"
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#include "libbfd.h"
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static bfd_boolean c4x_scan
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static bfd_boolean tic4x_scan
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PARAMS ((const struct bfd_arch_info *, const char * ));
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static bfd_boolean
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c4x_scan (info, string)
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tic4x_scan (info, string)
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const struct bfd_arch_info *info;
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const char *string;
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{
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@ -42,9 +42,9 @@ c4x_scan (info, string)
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return FALSE;
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if (*string == '3')
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return (info->mach == bfd_mach_c3x);
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return (info->mach == bfd_mach_tic3x);
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else if (*string == '4')
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return info->mach == bfd_mach_c4x;
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return info->mach == bfd_mach_tic4x;
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return FALSE;
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}
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@ -56,13 +56,13 @@ const bfd_arch_info_type bfd_tic3x_arch =
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32, /* 32 bits in an address. */
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32, /* 32 bits in a byte. */
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bfd_arch_tic4x,
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bfd_mach_c3x, /* Machine number. */
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"c3x", /* Architecture name. */
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bfd_mach_tic3x, /* Machine number. */
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"tic3x", /* Architecture name. */
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"tms320c3x", /* Printable name. */
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0, /* Alignment power. */
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FALSE, /* Not the default architecture. */
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bfd_default_compatible,
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c4x_scan,
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tic4x_scan,
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0
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};
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@ -72,13 +72,13 @@ const bfd_arch_info_type bfd_tic4x_arch =
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32, /* 32 bits in an address. */
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32, /* 32 bits in a byte. */
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bfd_arch_tic4x,
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bfd_mach_c4x, /* Machine number. */
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"c4x", /* Architecture name. */
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bfd_mach_tic4x, /* Machine number. */
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"tic4x", /* Architecture name. */
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"tms320c4x", /* Printable name. */
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0, /* Alignment power. */
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TRUE, /* The default architecture. */
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bfd_default_compatible,
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c4x_scan,
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tic4x_scan,
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&bfd_tic3x_arch,
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};
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@ -1,3 +1,11 @@
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2003-04-04 Svein E. Seldal <Svein.Seldal@solidas.com>
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* config/obj-coff.h (TARGET_FORMAT): Namespace cleanup, changed
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default tic4x target format to 'coff2-tic4x'.
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* config/tc-tic4x.c: Namespace cleanup. Replace s/c4x/tic4x/ and
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s/c3x/tic3x/
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* config/tc-tic4x.h: Ditto
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2003-04-03 Nick Clifton <nickc@redhat.com>
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* NEWS: Mention support for Xtensa architecture.
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@ -159,7 +159,7 @@
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#ifdef TC_TIC4X
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#include "coff/tic4x.h"
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#define TARGET_FORMAT "coff2-c4x"
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#define TARGET_FORMAT "coff2-tic4x"
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#endif
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#ifdef TC_TIC54X
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File diff suppressed because it is too large
Load diff
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@ -1,5 +1,5 @@
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/* tc-tic4x.h -- Assemble for the Texas TMS320C[34]X.
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Copyright (C) 1997, 2002 Free Software Foundation.
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Copyright (C) 1997, 2002, 2003 Free Software Foundation.
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Contributed by Michael P. Hayes (m.hayes@elec.canterbury.ac.nz)
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@ -20,7 +20,7 @@
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the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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#define TC_TIC4X
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#define C4X
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#define TIC4X
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#ifndef BFD_ASSEMBLER
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#error TMS320C4x requires BFD_ASSEMBLER
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@ -80,21 +80,21 @@
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/* Accept numbers with a suffix, e.g. 0ffffh, 1010b. */
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#define NUMBERS_WITH_SUFFIX 1
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extern int c4x_unrecognized_line PARAMS ((int));
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#define tc_unrecognized_line(c) c4x_unrecognized_line (c)
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extern int tic4x_unrecognized_line PARAMS ((int));
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#define tc_unrecognized_line(c) tic4x_unrecognized_line (c)
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#define md_number_to_chars number_to_chars_littleendian
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extern int c4x_do_align PARAMS ((int, const char *, int, int));
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#define md_do_align(n,fill,len,max,label) if( c4x_do_align (n,fill,len,max) ) goto label;
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extern int tic4x_do_align PARAMS ((int, const char *, int, int));
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#define md_do_align(n,fill,len,max,label) if( tic4x_do_align (n,fill,len,max) ) goto label;
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/* Start of line hook to remove parallel instruction operator || */
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extern void c4x_start_line PARAMS ((void));
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#define md_start_line_hook() c4x_start_line()
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extern void tic4x_start_line PARAMS ((void));
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#define md_start_line_hook() tic4x_start_line()
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extern void c4x_cleanup PARAMS ((void));
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#define md_cleanup() c4x_cleanup()
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extern void tic4x_cleanup PARAMS ((void));
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#define md_cleanup() tic4x_cleanup()
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extern void c4x_end PARAMS ((void));
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#define md_end() c4x_end()
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extern void tic4x_end PARAMS ((void));
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#define md_end() tic4x_end()
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@ -1,3 +1,10 @@
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2003-04-04 Svein E. Seldal <Svein.Seldal@solidas.com>
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* coff/tic4x.h: Namespace cleanup. Replace s/c4x/tic4x
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and s/c3x/tic3x/
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* coff/tc-tic4x.h: Ditto
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* opcode/tic4x.h: Ditto
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2003-04-02 Bob Wilson <bob.wilson@acm.org>
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* xtensa-config.h: Remove comment indicating that this is a
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@ -1,7 +1,7 @@
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/* TI COFF information for Texas Instruments TMS320C4X/C3X.
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This file customizes the settings in coff/ti.h.
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Copyright 2002 Free Software Foundation, Inc.
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Copyright 2002, 2003 Free Software Foundation, Inc.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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@ -31,12 +31,12 @@
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#define TICOFF_DEFAULT_MAGIC TICOFF2MAGIC
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#define TICOFF_TARGET_MACHINE_GET(FLAGS) \
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(((FLAGS) & F_VERS) ? bfd_mach_c4x : bfd_mach_c3x)
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(((FLAGS) & F_VERS) ? bfd_mach_tic4x : bfd_mach_tic3x)
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#define TICOFF_TARGET_MACHINE_SET(FLAGSP, MACHINE) \
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do \
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{ \
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if ((MACHINE) == bfd_mach_c4x) \
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if ((MACHINE) == bfd_mach_tic4x) \
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*(FLAGSP) |= F_VERS; \
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} \
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while (0)
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@ -1,6 +1,6 @@
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/* Table of opcodes for the Texas Instruments TMS320C[34]X family.
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Copyright (c) 2002 Free Software Foundation.
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Copyright (C) 2002, 2003 Free Software Foundation.
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Contributed by Michael P. Hayes (m.hayes@elec.canterbury.ac.nz)
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@ -19,8 +19,8 @@
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Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#define IS_CPU_C3X(v) ((v) == 30 || (v) == 31 || (v) == 32 || (v) == 33)
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#define IS_CPU_C4X(v) ((v) == 0 || (v) == 40 || (v) == 44)
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#define IS_CPU_TIC3X(v) ((v) == 30 || (v) == 31 || (v) == 32 || (v) == 33)
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#define IS_CPU_TIC4X(v) ((v) == 0 || (v) == 40 || (v) == 44)
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/* Define some bitfield extraction/insertion macros. */
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#define EXTR(inst, m, l) ((inst) << (31 - (m)) >> (31 - ((m) - (l))))
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@ -50,22 +50,22 @@ c4x_reg_t;
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#define REG_IF REG_IIE /* C3x only */
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#define REG_IOF REG_IIF /* C3x only */
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#define C3X_REG_MAX REG_RC
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#define C4X_REG_MAX REG_TVTP
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#define TIC3X_REG_MAX REG_RC
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#define TIC4X_REG_MAX REG_TVTP
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/* Register table size including C4x expansion regs. */
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#define REG_TABLE_SIZE (C4X_REG_MAX + 1)
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#define REG_TABLE_SIZE (TIC4X_REG_MAX + 1)
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struct c4x_register
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struct tic4x_register
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{
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char * name;
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unsigned long regno;
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};
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typedef struct c4x_register c4x_register_t;
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typedef struct tic4x_register tic4x_register_t;
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/* We could store register synonyms here. */
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static const c4x_register_t c3x_registers[] =
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static const tic4x_register_t tic3x_registers[] =
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{
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{"f0", REG_R0},
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{"r0", REG_R0},
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@ -106,10 +106,10 @@ static const c4x_register_t c3x_registers[] =
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{"", 0}
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};
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const unsigned int c3x_num_registers = (((sizeof c3x_registers) / (sizeof c3x_registers[0])) - 1);
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const unsigned int tic3x_num_registers = (((sizeof tic3x_registers) / (sizeof tic3x_registers[0])) - 1);
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/* Define C4x registers in addition to C3x registers. */
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static const c4x_register_t c4x_registers[] =
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static const tic4x_register_t tic4x_registers[] =
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{
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{"die", REG_DIE}, /* Clobbers C3x REG_IE */
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{"iie", REG_IIE}, /* Clobbers C3x REG_IF */
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@ -127,19 +127,19 @@ static const c4x_register_t c4x_registers[] =
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{"", 0}
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};
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const unsigned int c4x_num_registers = (((sizeof c4x_registers) / (sizeof c4x_registers[0])) - 1);
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const unsigned int tic4x_num_registers = (((sizeof tic4x_registers) / (sizeof tic4x_registers[0])) - 1);
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struct c4x_cond
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struct tic4x_cond
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{
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char * name;
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unsigned long cond;
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};
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typedef struct c4x_cond c4x_cond_t;
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typedef struct tic4x_cond tic4x_cond_t;
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/* Define conditional branch/load suffixes. Put desired form for
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disassembler last. */
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static const c4x_cond_t c4x_conds[] =
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static const tic4x_cond_t tic4x_conds[] =
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{
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{ "u", 0x00 },
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{ "c", 0x01 }, { "lo", 0x01 },
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@ -167,22 +167,22 @@ static const c4x_cond_t c4x_conds[] =
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{ "", 0x0}
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};
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const unsigned int num_conds = (((sizeof c4x_conds) / (sizeof c4x_conds[0])) - 1);
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const unsigned int tic4x_num_conds = (((sizeof tic4x_conds) / (sizeof tic4x_conds[0])) - 1);
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struct c4x_indirect
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struct tic4x_indirect
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{
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char * name;
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unsigned long modn;
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};
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typedef struct c4x_indirect c4x_indirect_t;
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typedef struct tic4x_indirect tic4x_indirect_t;
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/* Define indirect addressing modes where:
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d displacement (signed)
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y ir0
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z ir1 */
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static const c4x_indirect_t c4x_indirects[] =
|
||||
static const tic4x_indirect_t tic4x_indirects[] =
|
||||
{
|
||||
{ "*+a(d)", 0x00 },
|
||||
{ "*-a(d)", 0x01 },
|
||||
|
|
@ -216,12 +216,12 @@ static const c4x_indirect_t c4x_indirects[] =
|
|||
{ "", 0x0}
|
||||
};
|
||||
|
||||
#define C3X_MODN_MAX 0x19
|
||||
#define TIC3X_MODN_MAX 0x19
|
||||
|
||||
const unsigned int c4x_num_indirects = (((sizeof c4x_indirects) / (sizeof c4x_indirects[0])) - 1);
|
||||
const unsigned int tic4x_num_indirects = (((sizeof tic4x_indirects) / (sizeof tic4x_indirects[0])) - 1);
|
||||
|
||||
/* Instruction template. */
|
||||
struct c4x_inst
|
||||
struct tic4x_inst
|
||||
{
|
||||
char * name;
|
||||
unsigned long opcode;
|
||||
|
|
@ -230,7 +230,7 @@ struct c4x_inst
|
|||
unsigned long oplevel;
|
||||
};
|
||||
|
||||
typedef struct c4x_inst c4x_inst_t;
|
||||
typedef struct tic4x_inst tic4x_inst_t;
|
||||
|
||||
/* Opcode infix
|
||||
B condition 16--20 U,C,Z,LO,HI, etc.
|
||||
|
|
@ -278,8 +278,8 @@ typedef struct c4x_inst c4x_inst_t;
|
|||
Z expansion reg (C4x) 16--20 [Z] - IVTP, TVTP
|
||||
*/
|
||||
|
||||
#define C4X_OPERANDS_MAX 7 /* Max number of operands for an inst. */
|
||||
#define C4X_NAME_MAX 16 /* Max number of chars in parallel name. */
|
||||
#define TIC4X_OPERANDS_MAX 7 /* Max number of operands for an inst. */
|
||||
#define TIC4X_NAME_MAX 16 /* Max number of chars in parallel name. */
|
||||
|
||||
/* Define the instruction level */
|
||||
#define OP_C3X 0x1 /* C30 support - supported by all */
|
||||
|
|
@ -873,8 +873,8 @@ typedef struct c4x_inst c4x_inst_t;
|
|||
*/
|
||||
|
||||
|
||||
/* Define c3x opcodes for assembler and disassembler. */
|
||||
static const c4x_inst_t c4x_insts[] =
|
||||
/* Define tic4x opcodes for assembler and disassembler. */
|
||||
static const tic4x_inst_t tic4x_insts[] =
|
||||
{
|
||||
/* Put synonyms after the desired forms in table so that they get
|
||||
overwritten in the lookup table. The disassembler will thus
|
||||
|
|
@ -1070,10 +1070,10 @@ static const c4x_inst_t c4x_insts[] =
|
|||
TC_CLASS_INSN( "xor", 0x08000000, OP_C3X ),
|
||||
QC_CLASS_INSN( "xor", "sti", 0xee000000, OP_C3X ),
|
||||
|
||||
/* Dummy entry, not included in c3x_num_insts. This
|
||||
/* Dummy entry, not included in tic4x_num_insts. This
|
||||
lets code examine entry i + 1 without checking
|
||||
if we've run off the end of the table. */
|
||||
{ "", 0x0, 0x00, "", 0 }
|
||||
};
|
||||
|
||||
const unsigned int c4x_num_insts = (((sizeof c4x_insts) / (sizeof c4x_insts[0])) - 1);
|
||||
const unsigned int tic4x_num_insts = (((sizeof tic4x_insts) / (sizeof tic4x_insts[0])) - 1);
|
||||
|
|
|
|||
|
|
@ -1,3 +1,11 @@
|
|||
2003-04-04 Svein E. Seldal <Svein.Seldal@solidas.com>
|
||||
|
||||
* emulparams/tic3xcoff.sh (SCRIPT_NAME): Namespace
|
||||
cleanup. Replace s/c4x/tic4x and s/c3x/tic3x/
|
||||
* emulparams/tic3xcoff_onchip.sh: Ditto
|
||||
* emulparams/tic4xcoff.sh: Ditto
|
||||
* scripttempl/tic4xcoff.sc: Ditto
|
||||
|
||||
2003-04-03 Nick Clifton <nickc@redhat.com>
|
||||
|
||||
* NEWS: Mention support for Xtensa architecture.
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
SCRIPT_NAME=tic4xcoff
|
||||
OUTPUT_FORMAT="coff2-c4x"
|
||||
OUTPUT_ARCH="c3x"
|
||||
ARCH=c3x
|
||||
OUTPUT_FORMAT="coff2-tic4x"
|
||||
OUTPUT_ARCH="tic3x"
|
||||
ARCH=tic3x
|
||||
TEMPLATE_NAME=ticoff
|
||||
OUTPUT_FORMAT_TEMPLATE=tic4x
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
SCRIPT_NAME=tic4xcoff
|
||||
OUTPUT_FORMAT="coff2-c4x"
|
||||
OUTPUT_ARCH="c3x"
|
||||
ARCH=c3x
|
||||
OUTPUT_FORMAT="coff2-tic4x"
|
||||
OUTPUT_ARCH="tic3x"
|
||||
ARCH=tic3x
|
||||
TEMPLATE_NAME=ticoff
|
||||
OUTPUT_FORMAT_TEMPLATE=tic4x
|
||||
ONCHIP=yes
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
SCRIPT_NAME=tic4xcoff
|
||||
OUTPUT_FORMAT="coff2-c4x"
|
||||
OUTPUT_ARCH="c4x"
|
||||
ARCH=c4x
|
||||
OUTPUT_FORMAT="coff2-tic4x"
|
||||
OUTPUT_ARCH="tic4x"
|
||||
ARCH=tic4x
|
||||
TEMPLATE_NAME=ticoff
|
||||
OUTPUT_FORMAT_TEMPLATE=tic4x
|
||||
|
|
|
|||
|
|
@ -31,8 +31,8 @@
|
|||
# This emulation assumes config 7.
|
||||
|
||||
case $OUTPUT_ARCH in
|
||||
c3x) OUTPUT_ARCHNAME="TMS320C3x" ;;
|
||||
c4x) OUTPUT_ARCHNAME="TMS320C4x" ;;
|
||||
tic3x) OUTPUT_ARCHNAME="TMS320C3x" ;;
|
||||
tic4x) OUTPUT_ARCHNAME="TMS320C4x" ;;
|
||||
esac
|
||||
|
||||
case $ONCHIP in
|
||||
|
|
|
|||
|
|
@ -1,3 +1,8 @@
|
|||
2003-04-04 Svein E. Seldal <Svein.Seldal@solidas.com>
|
||||
|
||||
* tic4x-dis.c: Namespace cleanup. Replace s/c4x/tic4x and
|
||||
s/c3x/tic3x/
|
||||
|
||||
2003-04-01 Nick Clifton <nickc@redhat.com>
|
||||
|
||||
* arm-dis.c: Remove presence of (r) and (tm) symbols.
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
/* Print instructions for the Texas TMS320C[34]X, for GDB and GNU Binutils.
|
||||
|
||||
Copyright 2002 Free Software Foundation, Inc.
|
||||
Copyright 2002, 2003 Free Software Foundation, Inc.
|
||||
|
||||
Contributed by Michael P. Hayes (m.hayes@elec.canterbury.ac.nz)
|
||||
|
||||
|
|
@ -23,10 +23,10 @@
|
|||
#include "dis-asm.h"
|
||||
#include "opcode/tic4x.h"
|
||||
|
||||
#define C4X_DEBUG 0
|
||||
#define TIC4X_DEBUG 0
|
||||
|
||||
#define C4X_HASH_SIZE 11 /* 11 (bits) and above should give unique entries. */
|
||||
#define C4X_SPESOP_SIZE 8 /* Max 8. ops for special instructions */
|
||||
#define TIC4X_HASH_SIZE 11 /* 11 (bits) and above should give unique entries. */
|
||||
#define TIC4X_SPESOP_SIZE 8 /* Max 8. ops for special instructions */
|
||||
|
||||
typedef enum
|
||||
{
|
||||
|
|
@ -43,49 +43,49 @@ typedef enum
|
|||
{
|
||||
INDIRECT_SHORT,
|
||||
INDIRECT_LONG,
|
||||
INDIRECT_C4X
|
||||
INDIRECT_TIC4X
|
||||
}
|
||||
indirect_t;
|
||||
|
||||
static int c4x_version = 0;
|
||||
static int c4x_dp = 0;
|
||||
static int tic4x_version = 0;
|
||||
static int tic4x_dp = 0;
|
||||
|
||||
static int c4x_pc_offset
|
||||
static int tic4x_pc_offset
|
||||
PARAMS ((unsigned int));
|
||||
static int c4x_print_char
|
||||
static int tic4x_print_char
|
||||
PARAMS ((struct disassemble_info *, char));
|
||||
static int c4x_print_str
|
||||
static int tic4x_print_str
|
||||
PARAMS ((struct disassemble_info *, char *));
|
||||
static int c4x_print_register
|
||||
static int tic4x_print_register
|
||||
PARAMS ((struct disassemble_info *, unsigned long));
|
||||
static int c4x_print_addr
|
||||
static int tic4x_print_addr
|
||||
PARAMS ((struct disassemble_info *, unsigned long));
|
||||
static int c4x_print_relative
|
||||
static int tic4x_print_relative
|
||||
PARAMS ((struct disassemble_info *, unsigned long, long, unsigned long));
|
||||
void c4x_print_ftoa
|
||||
void tic4x_print_ftoa
|
||||
PARAMS ((unsigned int, FILE *, fprintf_ftype));
|
||||
static int c4x_print_direct
|
||||
static int tic4x_print_direct
|
||||
PARAMS ((struct disassemble_info *, unsigned long));
|
||||
static int c4x_print_immed
|
||||
static int tic4x_print_immed
|
||||
PARAMS ((struct disassemble_info *, immed_t, unsigned long));
|
||||
static int c4x_print_cond
|
||||
static int tic4x_print_cond
|
||||
PARAMS ((struct disassemble_info *, unsigned int));
|
||||
static int c4x_print_indirect
|
||||
static int tic4x_print_indirect
|
||||
PARAMS ((struct disassemble_info *, indirect_t, unsigned long));
|
||||
static int c4x_print_op
|
||||
PARAMS ((struct disassemble_info *, unsigned long, c4x_inst_t *, unsigned long));
|
||||
static void c4x_hash_opcode_special
|
||||
PARAMS ((c4x_inst_t **, const c4x_inst_t *));
|
||||
static void c4x_hash_opcode
|
||||
PARAMS ((c4x_inst_t **, c4x_inst_t **, const c4x_inst_t *, unsigned long));
|
||||
static int c4x_disassemble
|
||||
static int tic4x_print_op
|
||||
PARAMS ((struct disassemble_info *, unsigned long, tic4x_inst_t *, unsigned long));
|
||||
static void tic4x_hash_opcode_special
|
||||
PARAMS ((tic4x_inst_t **, const tic4x_inst_t *));
|
||||
static void tic4x_hash_opcode
|
||||
PARAMS ((tic4x_inst_t **, tic4x_inst_t **, const tic4x_inst_t *, unsigned long));
|
||||
static int tic4x_disassemble
|
||||
PARAMS ((unsigned long, unsigned long, struct disassemble_info *));
|
||||
int print_insn_tic4x
|
||||
PARAMS ((bfd_vma, struct disassemble_info *));
|
||||
|
||||
|
||||
static int
|
||||
c4x_pc_offset (op)
|
||||
tic4x_pc_offset (op)
|
||||
unsigned int op;
|
||||
{
|
||||
/* Determine the PC offset for a C[34]x instruction.
|
||||
|
|
@ -143,7 +143,7 @@ c4x_pc_offset (op)
|
|||
}
|
||||
|
||||
static int
|
||||
c4x_print_char (info, ch)
|
||||
tic4x_print_char (info, ch)
|
||||
struct disassemble_info * info;
|
||||
char ch;
|
||||
{
|
||||
|
|
@ -153,7 +153,7 @@ c4x_print_char (info, ch)
|
|||
}
|
||||
|
||||
static int
|
||||
c4x_print_str (info, str)
|
||||
tic4x_print_str (info, str)
|
||||
struct disassemble_info *info;
|
||||
char *str;
|
||||
{
|
||||
|
|
@ -163,28 +163,28 @@ c4x_print_str (info, str)
|
|||
}
|
||||
|
||||
static int
|
||||
c4x_print_register (info, regno)
|
||||
tic4x_print_register (info, regno)
|
||||
struct disassemble_info *info;
|
||||
unsigned long regno;
|
||||
{
|
||||
static c4x_register_t **registertable = NULL;
|
||||
static tic4x_register_t **registertable = NULL;
|
||||
unsigned int i;
|
||||
|
||||
if (registertable == NULL)
|
||||
{
|
||||
registertable = (c4x_register_t **)
|
||||
xmalloc (sizeof (c4x_register_t *) * REG_TABLE_SIZE);
|
||||
for (i = 0; i < c3x_num_registers; i++)
|
||||
registertable[c3x_registers[i].regno] = (void *)&c3x_registers[i];
|
||||
if (IS_CPU_C4X (c4x_version))
|
||||
registertable = (tic4x_register_t **)
|
||||
xmalloc (sizeof (tic4x_register_t *) * REG_TABLE_SIZE);
|
||||
for (i = 0; i < tic3x_num_registers; i++)
|
||||
registertable[tic3x_registers[i].regno] = (void *)&tic3x_registers[i];
|
||||
if (IS_CPU_TIC4X (tic4x_version))
|
||||
{
|
||||
/* Add C4x additional registers, overwriting
|
||||
any C3x registers if necessary. */
|
||||
for (i = 0; i < c4x_num_registers; i++)
|
||||
registertable[c4x_registers[i].regno] = (void *)&c4x_registers[i];
|
||||
for (i = 0; i < tic4x_num_registers; i++)
|
||||
registertable[tic4x_registers[i].regno] = (void *)&tic4x_registers[i];
|
||||
}
|
||||
}
|
||||
if ((int) regno > (IS_CPU_C4X (c4x_version) ? C4X_REG_MAX : C3X_REG_MAX))
|
||||
if ((int) regno > (IS_CPU_TIC4X (tic4x_version) ? TIC4X_REG_MAX : TIC3X_REG_MAX))
|
||||
return 0;
|
||||
if (info != NULL)
|
||||
(*info->fprintf_func) (info->stream, "%s", registertable[regno]->name);
|
||||
|
|
@ -192,7 +192,7 @@ c4x_print_register (info, regno)
|
|||
}
|
||||
|
||||
static int
|
||||
c4x_print_addr (info, addr)
|
||||
tic4x_print_addr (info, addr)
|
||||
struct disassemble_info *info;
|
||||
unsigned long addr;
|
||||
{
|
||||
|
|
@ -202,24 +202,24 @@ c4x_print_addr (info, addr)
|
|||
}
|
||||
|
||||
static int
|
||||
c4x_print_relative (info, pc, offset, opcode)
|
||||
tic4x_print_relative (info, pc, offset, opcode)
|
||||
struct disassemble_info *info;
|
||||
unsigned long pc;
|
||||
long offset;
|
||||
unsigned long opcode;
|
||||
{
|
||||
return c4x_print_addr (info, pc + offset + c4x_pc_offset (opcode));
|
||||
return tic4x_print_addr (info, pc + offset + tic4x_pc_offset (opcode));
|
||||
}
|
||||
|
||||
static int
|
||||
c4x_print_direct (info, arg)
|
||||
tic4x_print_direct (info, arg)
|
||||
struct disassemble_info *info;
|
||||
unsigned long arg;
|
||||
{
|
||||
if (info != NULL)
|
||||
{
|
||||
(*info->fprintf_func) (info->stream, "@");
|
||||
c4x_print_addr (info, arg + (c4x_dp << 16));
|
||||
tic4x_print_addr (info, arg + (tic4x_dp << 16));
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
|
|
@ -227,7 +227,7 @@ c4x_print_direct (info, arg)
|
|||
/* FIXME: make the floating point stuff not rely on host
|
||||
floating point arithmetic. */
|
||||
void
|
||||
c4x_print_ftoa (val, stream, pfunc)
|
||||
tic4x_print_ftoa (val, stream, pfunc)
|
||||
unsigned int val;
|
||||
FILE *stream;
|
||||
fprintf_ftype pfunc;
|
||||
|
|
@ -253,7 +253,7 @@ c4x_print_ftoa (val, stream, pfunc)
|
|||
}
|
||||
|
||||
static int
|
||||
c4x_print_immed (info, type, arg)
|
||||
tic4x_print_immed (info, type, arg)
|
||||
struct disassemble_info *info;
|
||||
immed_t type;
|
||||
unsigned long arg;
|
||||
|
|
@ -312,18 +312,18 @@ c4x_print_immed (info, type, arg)
|
|||
}
|
||||
|
||||
static int
|
||||
c4x_print_cond (info, cond)
|
||||
tic4x_print_cond (info, cond)
|
||||
struct disassemble_info *info;
|
||||
unsigned int cond;
|
||||
{
|
||||
static c4x_cond_t **condtable = NULL;
|
||||
static tic4x_cond_t **condtable = NULL;
|
||||
unsigned int i;
|
||||
|
||||
if (condtable == NULL)
|
||||
{
|
||||
condtable = (c4x_cond_t **)xmalloc (sizeof (c4x_cond_t *) * 32);
|
||||
for (i = 0; i < num_conds; i++)
|
||||
condtable[c4x_conds[i].cond] = (void *)&c4x_conds[i];
|
||||
condtable = (tic4x_cond_t **)xmalloc (sizeof (tic4x_cond_t *) * 32);
|
||||
for (i = 0; i < tic4x_num_conds; i++)
|
||||
condtable[tic4x_conds[i].cond] = (void *)&tic4x_conds[i];
|
||||
}
|
||||
if (cond > 31 || condtable[cond] == NULL)
|
||||
return 0;
|
||||
|
|
@ -333,7 +333,7 @@ c4x_print_cond (info, cond)
|
|||
}
|
||||
|
||||
static int
|
||||
c4x_print_indirect (info, type, arg)
|
||||
tic4x_print_indirect (info, type, arg)
|
||||
struct disassemble_info *info;
|
||||
indirect_t type;
|
||||
unsigned long arg;
|
||||
|
|
@ -348,7 +348,7 @@ c4x_print_indirect (info, type, arg)
|
|||
disp = 1;
|
||||
switch(type)
|
||||
{
|
||||
case INDIRECT_C4X: /* *+ARn(disp) */
|
||||
case INDIRECT_TIC4X: /* *+ARn(disp) */
|
||||
disp = EXTRU (arg, 7, 3);
|
||||
aregno = EXTRU (arg, 2, 0) + REG_AR0;
|
||||
modn = 0;
|
||||
|
|
@ -366,29 +366,30 @@ c4x_print_indirect (info, type, arg)
|
|||
return 0;
|
||||
break;
|
||||
default:
|
||||
abort ();
|
||||
(*info->fprintf_func)(info->stream, "# internal error: Unknown indirect type %d", type);
|
||||
return 0;
|
||||
}
|
||||
if (modn > C3X_MODN_MAX)
|
||||
if (modn > TIC3X_MODN_MAX)
|
||||
return 0;
|
||||
a = c4x_indirects[modn].name;
|
||||
a = tic4x_indirects[modn].name;
|
||||
while (*a)
|
||||
{
|
||||
switch (*a)
|
||||
{
|
||||
case 'a':
|
||||
c4x_print_register (info, aregno);
|
||||
tic4x_print_register (info, aregno);
|
||||
break;
|
||||
case 'd':
|
||||
c4x_print_immed (info, IMMED_UINT, disp);
|
||||
tic4x_print_immed (info, IMMED_UINT, disp);
|
||||
break;
|
||||
case 'y':
|
||||
c4x_print_str (info, "ir0");
|
||||
tic4x_print_str (info, "ir0");
|
||||
break;
|
||||
case 'z':
|
||||
c4x_print_str (info, "ir1");
|
||||
tic4x_print_str (info, "ir1");
|
||||
break;
|
||||
default:
|
||||
c4x_print_char (info, *a);
|
||||
tic4x_print_char (info, *a);
|
||||
break;
|
||||
}
|
||||
a++;
|
||||
|
|
@ -397,10 +398,10 @@ c4x_print_indirect (info, type, arg)
|
|||
}
|
||||
|
||||
static int
|
||||
c4x_print_op (info, instruction, p, pc)
|
||||
tic4x_print_op (info, instruction, p, pc)
|
||||
struct disassemble_info *info;
|
||||
unsigned long instruction;
|
||||
c4x_inst_t *p;
|
||||
tic4x_inst_t *p;
|
||||
unsigned long pc;
|
||||
{
|
||||
int val;
|
||||
|
|
@ -414,18 +415,18 @@ c4x_print_op (info, instruction, p, pc)
|
|||
switch (*s)
|
||||
{
|
||||
case 'B':
|
||||
if (! c4x_print_cond (info, EXTRU (instruction, 20, 16)))
|
||||
if (! tic4x_print_cond (info, EXTRU (instruction, 20, 16)))
|
||||
return 0;
|
||||
break;
|
||||
case 'C':
|
||||
if (! c4x_print_cond (info, EXTRU (instruction, 27, 23)))
|
||||
if (! tic4x_print_cond (info, EXTRU (instruction, 27, 23)))
|
||||
return 0;
|
||||
break;
|
||||
case '_':
|
||||
parallel = s + 1; /* Skip past `_' in name */
|
||||
break;
|
||||
default:
|
||||
c4x_print_char (info, *s);
|
||||
tic4x_print_char (info, *s);
|
||||
break;
|
||||
}
|
||||
s++;
|
||||
|
|
@ -434,45 +435,45 @@ c4x_print_op (info, instruction, p, pc)
|
|||
/* Print arguments. */
|
||||
s = p->args;
|
||||
if (*s)
|
||||
c4x_print_char (info, ' ');
|
||||
tic4x_print_char (info, ' ');
|
||||
|
||||
while (*s)
|
||||
{
|
||||
switch (*s)
|
||||
{
|
||||
case '*': /* indirect 0--15 */
|
||||
if (! c4x_print_indirect (info, INDIRECT_LONG,
|
||||
if (! tic4x_print_indirect (info, INDIRECT_LONG,
|
||||
EXTRU (instruction, 15, 0)))
|
||||
return 0;
|
||||
break;
|
||||
|
||||
case '#': /* only used for ldp, ldpk */
|
||||
c4x_print_immed (info, IMMED_UINT, EXTRU (instruction, 15, 0));
|
||||
tic4x_print_immed (info, IMMED_UINT, EXTRU (instruction, 15, 0));
|
||||
break;
|
||||
|
||||
case '@': /* direct 0--15 */
|
||||
c4x_print_direct (info, EXTRU (instruction, 15, 0));
|
||||
tic4x_print_direct (info, EXTRU (instruction, 15, 0));
|
||||
break;
|
||||
|
||||
case 'A': /* address register 24--22 */
|
||||
if (! c4x_print_register (info, EXTRU (instruction, 24, 22) +
|
||||
if (! tic4x_print_register (info, EXTRU (instruction, 24, 22) +
|
||||
REG_AR0))
|
||||
return 0;
|
||||
break;
|
||||
|
||||
case 'B': /* 24-bit unsigned int immediate br(d)/call/rptb
|
||||
address 0--23. */
|
||||
if (IS_CPU_C4X (c4x_version))
|
||||
c4x_print_relative (info, pc, EXTRS (instruction, 23, 0),
|
||||
if (IS_CPU_TIC4X (tic4x_version))
|
||||
tic4x_print_relative (info, pc, EXTRS (instruction, 23, 0),
|
||||
p->opcode);
|
||||
else
|
||||
c4x_print_addr (info, EXTRU (instruction, 23, 0));
|
||||
tic4x_print_addr (info, EXTRU (instruction, 23, 0));
|
||||
break;
|
||||
|
||||
case 'C': /* indirect (short C4x) 0--7 */
|
||||
if (! IS_CPU_C4X (c4x_version))
|
||||
if (! IS_CPU_TIC4X (tic4x_version))
|
||||
return 0;
|
||||
if (! c4x_print_indirect (info, INDIRECT_C4X,
|
||||
if (! tic4x_print_indirect (info, INDIRECT_TIC4X,
|
||||
EXTRU (instruction, 7, 0)))
|
||||
return 0;
|
||||
break;
|
||||
|
|
@ -483,26 +484,26 @@ c4x_print_op (info, instruction, p, pc)
|
|||
|
||||
case 'E': /* register 0--7 */
|
||||
case 'e':
|
||||
if (! c4x_print_register (info, EXTRU (instruction, 7, 0)))
|
||||
if (! tic4x_print_register (info, EXTRU (instruction, 7, 0)))
|
||||
return 0;
|
||||
break;
|
||||
|
||||
case 'F': /* 16-bit float immediate 0--15 */
|
||||
c4x_print_immed (info, IMMED_SFLOAT,
|
||||
tic4x_print_immed (info, IMMED_SFLOAT,
|
||||
EXTRU (instruction, 15, 0));
|
||||
break;
|
||||
|
||||
case 'i': /* Extended indirect 0--7 */
|
||||
if ( EXTRU (instruction, 7, 5) == 7 )
|
||||
{
|
||||
if( !c4x_print_register (info, EXTRU (instruction, 4, 0)) )
|
||||
if( !tic4x_print_register (info, EXTRU (instruction, 4, 0)) )
|
||||
return 0;
|
||||
break;
|
||||
}
|
||||
/* Fallthrough */
|
||||
|
||||
case 'I': /* indirect (short) 0--7 */
|
||||
if (! c4x_print_indirect (info, INDIRECT_SHORT,
|
||||
if (! tic4x_print_indirect (info, INDIRECT_SHORT,
|
||||
EXTRU (instruction, 7, 0)))
|
||||
return 0;
|
||||
break;
|
||||
|
|
@ -510,106 +511,106 @@ c4x_print_op (info, instruction, p, pc)
|
|||
case 'j': /* Extended indirect 8--15 */
|
||||
if ( EXTRU (instruction, 15, 13) == 7 )
|
||||
{
|
||||
if( !c4x_print_register (info, EXTRU (instruction, 12, 8)) )
|
||||
if( !tic4x_print_register (info, EXTRU (instruction, 12, 8)) )
|
||||
return 0;
|
||||
break;
|
||||
}
|
||||
|
||||
case 'J': /* indirect (short) 8--15 */
|
||||
if (! c4x_print_indirect (info, INDIRECT_SHORT,
|
||||
if (! tic4x_print_indirect (info, INDIRECT_SHORT,
|
||||
EXTRU (instruction, 15, 8)))
|
||||
return 0;
|
||||
break;
|
||||
|
||||
case 'G': /* register 8--15 */
|
||||
case 'g':
|
||||
if (! c4x_print_register (info, EXTRU (instruction, 15, 8)))
|
||||
if (! tic4x_print_register (info, EXTRU (instruction, 15, 8)))
|
||||
return 0;
|
||||
break;
|
||||
|
||||
case 'H': /* register 16--18 */
|
||||
if (! c4x_print_register (info, EXTRU (instruction, 18, 16)))
|
||||
if (! tic4x_print_register (info, EXTRU (instruction, 18, 16)))
|
||||
return 0;
|
||||
break;
|
||||
|
||||
case 'K': /* register 19--21 */
|
||||
if (! c4x_print_register (info, EXTRU (instruction, 21, 19)))
|
||||
if (! tic4x_print_register (info, EXTRU (instruction, 21, 19)))
|
||||
return 0;
|
||||
break;
|
||||
|
||||
case 'L': /* register 22--24 */
|
||||
if (! c4x_print_register (info, EXTRU (instruction, 24, 22)))
|
||||
if (! tic4x_print_register (info, EXTRU (instruction, 24, 22)))
|
||||
return 0;
|
||||
break;
|
||||
|
||||
case 'M': /* register 22--22 */
|
||||
c4x_print_register (info, EXTRU (instruction, 22, 22) + REG_R2);
|
||||
tic4x_print_register (info, EXTRU (instruction, 22, 22) + REG_R2);
|
||||
break;
|
||||
|
||||
case 'N': /* register 23--23 */
|
||||
c4x_print_register (info, EXTRU (instruction, 23, 23) + REG_R0);
|
||||
tic4x_print_register (info, EXTRU (instruction, 23, 23) + REG_R0);
|
||||
break;
|
||||
|
||||
case 'O': /* indirect (short C4x) 8--15 */
|
||||
if (! IS_CPU_C4X (c4x_version))
|
||||
if (! IS_CPU_TIC4X (tic4x_version))
|
||||
return 0;
|
||||
if (! c4x_print_indirect (info, INDIRECT_C4X,
|
||||
if (! tic4x_print_indirect (info, INDIRECT_TIC4X,
|
||||
EXTRU (instruction, 15, 8)))
|
||||
return 0;
|
||||
break;
|
||||
|
||||
case 'P': /* displacement 0--15 (used by Bcond and BcondD) */
|
||||
c4x_print_relative (info, pc, EXTRS (instruction, 15, 0),
|
||||
tic4x_print_relative (info, pc, EXTRS (instruction, 15, 0),
|
||||
p->opcode);
|
||||
break;
|
||||
|
||||
case 'Q': /* register 0--15 */
|
||||
case 'q':
|
||||
if (! c4x_print_register (info, EXTRU (instruction, 15, 0)))
|
||||
if (! tic4x_print_register (info, EXTRU (instruction, 15, 0)))
|
||||
return 0;
|
||||
break;
|
||||
|
||||
case 'R': /* register 16--20 */
|
||||
case 'r':
|
||||
if (! c4x_print_register (info, EXTRU (instruction, 20, 16)))
|
||||
if (! tic4x_print_register (info, EXTRU (instruction, 20, 16)))
|
||||
return 0;
|
||||
break;
|
||||
|
||||
case 'S': /* 16-bit signed immediate 0--15 */
|
||||
c4x_print_immed (info, IMMED_SINT,
|
||||
tic4x_print_immed (info, IMMED_SINT,
|
||||
EXTRS (instruction, 15, 0));
|
||||
break;
|
||||
|
||||
case 'T': /* 5-bit signed immediate 16--20 (C4x stik) */
|
||||
if (! IS_CPU_C4X (c4x_version))
|
||||
if (! IS_CPU_TIC4X (tic4x_version))
|
||||
return 0;
|
||||
if (! c4x_print_immed (info, IMMED_SUINT,
|
||||
if (! tic4x_print_immed (info, IMMED_SUINT,
|
||||
EXTRU (instruction, 20, 16)))
|
||||
return 0;
|
||||
break;
|
||||
|
||||
case 'U': /* 16-bit unsigned int immediate 0--15 */
|
||||
c4x_print_immed (info, IMMED_SUINT, EXTRU (instruction, 15, 0));
|
||||
tic4x_print_immed (info, IMMED_SUINT, EXTRU (instruction, 15, 0));
|
||||
break;
|
||||
|
||||
case 'V': /* 5/9-bit unsigned vector 0--4/8 */
|
||||
c4x_print_immed (info, IMMED_SUINT,
|
||||
IS_CPU_C4X (c4x_version) ?
|
||||
tic4x_print_immed (info, IMMED_SUINT,
|
||||
IS_CPU_TIC4X (tic4x_version) ?
|
||||
EXTRU (instruction, 8, 0) :
|
||||
EXTRU (instruction, 4, 0) & ~0x20);
|
||||
break;
|
||||
|
||||
case 'W': /* 8-bit signed immediate 0--7 */
|
||||
if (! IS_CPU_C4X (c4x_version))
|
||||
if (! IS_CPU_TIC4X (tic4x_version))
|
||||
return 0;
|
||||
c4x_print_immed (info, IMMED_SINT, EXTRS (instruction, 7, 0));
|
||||
tic4x_print_immed (info, IMMED_SINT, EXTRS (instruction, 7, 0));
|
||||
break;
|
||||
|
||||
case 'X': /* expansion register 4--0 */
|
||||
val = EXTRU (instruction, 4, 0) + REG_IVTP;
|
||||
if (val < REG_IVTP || val > REG_TVTP)
|
||||
return 0;
|
||||
if (! c4x_print_register (info, val))
|
||||
if (! tic4x_print_register (info, val))
|
||||
return 0;
|
||||
break;
|
||||
|
||||
|
|
@ -617,7 +618,7 @@ c4x_print_op (info, instruction, p, pc)
|
|||
val = EXTRU (instruction, 20, 16);
|
||||
if (val < REG_AR0 || val > REG_SP)
|
||||
return 0;
|
||||
if (! c4x_print_register (info, val))
|
||||
if (! tic4x_print_register (info, val))
|
||||
return 0;
|
||||
break;
|
||||
|
||||
|
|
@ -625,22 +626,22 @@ c4x_print_op (info, instruction, p, pc)
|
|||
val = EXTRU (instruction, 20, 16) + REG_IVTP;
|
||||
if (val < REG_IVTP || val > REG_TVTP)
|
||||
return 0;
|
||||
if (! c4x_print_register (info, val))
|
||||
if (! tic4x_print_register (info, val))
|
||||
return 0;
|
||||
break;
|
||||
|
||||
case '|': /* Parallel instruction */
|
||||
c4x_print_str (info, " || ");
|
||||
c4x_print_str (info, parallel);
|
||||
c4x_print_char (info, ' ');
|
||||
tic4x_print_str (info, " || ");
|
||||
tic4x_print_str (info, parallel);
|
||||
tic4x_print_char (info, ' ');
|
||||
break;
|
||||
|
||||
case ';':
|
||||
c4x_print_char (info, ',');
|
||||
tic4x_print_char (info, ',');
|
||||
break;
|
||||
|
||||
default:
|
||||
c4x_print_char (info, *s);
|
||||
tic4x_print_char (info, *s);
|
||||
break;
|
||||
}
|
||||
s++;
|
||||
|
|
@ -649,13 +650,13 @@ c4x_print_op (info, instruction, p, pc)
|
|||
}
|
||||
|
||||
static void
|
||||
c4x_hash_opcode_special (optable_special, inst)
|
||||
c4x_inst_t **optable_special;
|
||||
const c4x_inst_t *inst;
|
||||
tic4x_hash_opcode_special (optable_special, inst)
|
||||
tic4x_inst_t **optable_special;
|
||||
const tic4x_inst_t *inst;
|
||||
{
|
||||
int i;
|
||||
|
||||
for( i=0; i<C4X_SPESOP_SIZE; i++ )
|
||||
for( i=0; i<TIC4X_SPESOP_SIZE; i++ )
|
||||
if( optable_special[i] != NULL
|
||||
&& optable_special[i]->opcode == inst->opcode )
|
||||
{
|
||||
|
|
@ -664,7 +665,7 @@ c4x_hash_opcode_special (optable_special, inst)
|
|||
return;
|
||||
}
|
||||
|
||||
for( i=0; i<C4X_SPESOP_SIZE; i++ )
|
||||
for( i=0; i<TIC4X_SPESOP_SIZE; i++ )
|
||||
if( optable_special[i] == NULL )
|
||||
{
|
||||
/* Add the new opcode */
|
||||
|
|
@ -673,32 +674,32 @@ c4x_hash_opcode_special (optable_special, inst)
|
|||
}
|
||||
|
||||
/* This should never occur. This happens if the number of special
|
||||
instructions exceeds C4X_SPESOP_SIZE. Please increase the variable
|
||||
instructions exceeds TIC4X_SPESOP_SIZE. Please increase the variable
|
||||
of this variable */
|
||||
#if C4X_DEBUG
|
||||
printf("optable_special[] is full, please increase C4X_SPESOP_SIZE!\n");
|
||||
#if TIC4X_DEBUG
|
||||
printf("optable_special[] is full, please increase TIC4X_SPESOP_SIZE!\n");
|
||||
#endif
|
||||
}
|
||||
|
||||
static void
|
||||
c4x_hash_opcode (optable, optable_special, inst, c4x_oplevel)
|
||||
c4x_inst_t **optable;
|
||||
c4x_inst_t **optable_special;
|
||||
const c4x_inst_t *inst;
|
||||
const unsigned long c4x_oplevel;
|
||||
tic4x_hash_opcode (optable, optable_special, inst, tic4x_oplevel)
|
||||
tic4x_inst_t **optable;
|
||||
tic4x_inst_t **optable_special;
|
||||
const tic4x_inst_t *inst;
|
||||
const unsigned long tic4x_oplevel;
|
||||
{
|
||||
int j;
|
||||
int opcode = inst->opcode >> (32 - C4X_HASH_SIZE);
|
||||
int opmask = inst->opmask >> (32 - C4X_HASH_SIZE);
|
||||
int opcode = inst->opcode >> (32 - TIC4X_HASH_SIZE);
|
||||
int opmask = inst->opmask >> (32 - TIC4X_HASH_SIZE);
|
||||
|
||||
/* Use a C4X_HASH_SIZE bit index as a hash index. We should
|
||||
/* Use a TIC4X_HASH_SIZE bit index as a hash index. We should
|
||||
have unique entries so there's no point having a linked list
|
||||
for each entry? */
|
||||
for (j = opcode; j < opmask; j++)
|
||||
if ( (j & opmask) == opcode
|
||||
&& inst->oplevel & c4x_oplevel )
|
||||
&& inst->oplevel & tic4x_oplevel )
|
||||
{
|
||||
#if C4X_DEBUG
|
||||
#if TIC4X_DEBUG
|
||||
/* We should only have collisions for synonyms like
|
||||
ldp for ldi. */
|
||||
if (optable[j] != NULL)
|
||||
|
|
@ -710,13 +711,13 @@ c4x_hash_opcode (optable, optable_special, inst, c4x_oplevel)
|
|||
hash. Store them in a special-list, that will handle full
|
||||
32-bit INSN, not only the first 11-bit (or so). */
|
||||
if ( optable[j] != NULL
|
||||
&& inst->opmask & ~(opmask << (32 - C4X_HASH_SIZE)) )
|
||||
&& inst->opmask & ~(opmask << (32 - TIC4X_HASH_SIZE)) )
|
||||
{
|
||||
/* Add the instruction already on the list */
|
||||
c4x_hash_opcode_special(optable_special, optable[j]);
|
||||
tic4x_hash_opcode_special(optable_special, optable[j]);
|
||||
|
||||
/* Add the new instruction */
|
||||
c4x_hash_opcode_special(optable_special, inst);
|
||||
tic4x_hash_opcode_special(optable_special, inst);
|
||||
}
|
||||
|
||||
optable[j] = (void *)inst;
|
||||
|
|
@ -730,67 +731,67 @@ c4x_hash_opcode (optable, optable_special, inst, c4x_oplevel)
|
|||
The function returns the length of this instruction in words. */
|
||||
|
||||
static int
|
||||
c4x_disassemble (pc, instruction, info)
|
||||
tic4x_disassemble (pc, instruction, info)
|
||||
unsigned long pc;
|
||||
unsigned long instruction;
|
||||
struct disassemble_info *info;
|
||||
{
|
||||
static c4x_inst_t **optable = NULL;
|
||||
static c4x_inst_t **optable_special = NULL;
|
||||
c4x_inst_t *p;
|
||||
static tic4x_inst_t **optable = NULL;
|
||||
static tic4x_inst_t **optable_special = NULL;
|
||||
tic4x_inst_t *p;
|
||||
int i;
|
||||
unsigned long c4x_oplevel;
|
||||
unsigned long tic4x_oplevel;
|
||||
|
||||
c4x_version = info->mach;
|
||||
tic4x_version = info->mach;
|
||||
|
||||
c4x_oplevel = (IS_CPU_C4X (c4x_version)) ? OP_C4X : 0;
|
||||
c4x_oplevel |= OP_C3X|OP_LPWR|OP_IDLE2|OP_ENH;
|
||||
tic4x_oplevel = (IS_CPU_TIC4X (tic4x_version)) ? OP_C4X : 0;
|
||||
tic4x_oplevel |= OP_C3X|OP_LPWR|OP_IDLE2|OP_ENH;
|
||||
|
||||
if (optable == NULL)
|
||||
{
|
||||
optable = (c4x_inst_t **)
|
||||
xcalloc (sizeof (c4x_inst_t *), (1 << C4X_HASH_SIZE));
|
||||
optable = (tic4x_inst_t **)
|
||||
xcalloc (sizeof (tic4x_inst_t *), (1 << TIC4X_HASH_SIZE));
|
||||
|
||||
optable_special = (c4x_inst_t **)
|
||||
xcalloc (sizeof (c4x_inst_t *), C4X_SPESOP_SIZE );
|
||||
optable_special = (tic4x_inst_t **)
|
||||
xcalloc (sizeof (tic4x_inst_t *), TIC4X_SPESOP_SIZE );
|
||||
|
||||
/* Install opcodes in reverse order so that preferred
|
||||
forms overwrite synonyms. */
|
||||
for (i = c4x_num_insts - 1; i >= 0; i--)
|
||||
c4x_hash_opcode (optable, optable_special, &c4x_insts[i], c4x_oplevel);
|
||||
for (i = tic4x_num_insts - 1; i >= 0; i--)
|
||||
tic4x_hash_opcode (optable, optable_special, &tic4x_insts[i], tic4x_oplevel);
|
||||
|
||||
/* We now need to remove the insn that are special from the
|
||||
"normal" optable, to make the disasm search this extra list
|
||||
for them.
|
||||
*/
|
||||
for (i=0; i<C4X_SPESOP_SIZE; i++)
|
||||
for (i=0; i<TIC4X_SPESOP_SIZE; i++)
|
||||
if ( optable_special[i] != NULL )
|
||||
optable[optable_special[i]->opcode >> (32 - C4X_HASH_SIZE)] = NULL;
|
||||
optable[optable_special[i]->opcode >> (32 - TIC4X_HASH_SIZE)] = NULL;
|
||||
}
|
||||
|
||||
/* See if we can pick up any loading of the DP register... */
|
||||
if ((instruction >> 16) == 0x5070 || (instruction >> 16) == 0x1f70)
|
||||
c4x_dp = EXTRU (instruction, 15, 0);
|
||||
tic4x_dp = EXTRU (instruction, 15, 0);
|
||||
|
||||
p = optable[instruction >> (32 - C4X_HASH_SIZE)];
|
||||
p = optable[instruction >> (32 - TIC4X_HASH_SIZE)];
|
||||
if ( p != NULL )
|
||||
{
|
||||
if ( ((instruction & p->opmask) == p->opcode)
|
||||
&& c4x_print_op (NULL, instruction, p, pc) )
|
||||
c4x_print_op (info, instruction, p, pc);
|
||||
&& tic4x_print_op (NULL, instruction, p, pc) )
|
||||
tic4x_print_op (info, instruction, p, pc);
|
||||
else
|
||||
(*info->fprintf_func) (info->stream, "%08x", instruction);
|
||||
}
|
||||
else
|
||||
{
|
||||
for (i = 0; i<C4X_SPESOP_SIZE; i++)
|
||||
for (i = 0; i<TIC4X_SPESOP_SIZE; i++)
|
||||
if (optable_special[i] != NULL
|
||||
&& optable_special[i]->opcode == instruction )
|
||||
{
|
||||
(*info->fprintf_func)(info->stream, "%s", optable_special[i]->name);
|
||||
break;
|
||||
}
|
||||
if (i==C4X_SPESOP_SIZE)
|
||||
if (i==TIC4X_SPESOP_SIZE)
|
||||
(*info->fprintf_func) (info->stream, "%08x", instruction);
|
||||
}
|
||||
|
||||
|
|
@ -822,5 +823,5 @@ print_insn_tic4x (memaddr, info)
|
|||
info->bytes_per_chunk = 4;
|
||||
info->octets_per_byte = 4;
|
||||
info->display_endian = BFD_ENDIAN_LITTLE;
|
||||
return c4x_disassemble (pc, op, info) * 4;
|
||||
return tic4x_disassemble (pc, op, info) * 4;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in a new issue