darkkirb/old-cross-binutils
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

* arch.c, arch.h, cpu.c, cpu.h, cpuall.h, decode.c, decode.h,

Browse source 
model.c, sem.c: Regenerate.
This commit is contained in:
Hans-Peter Nilsson 2008-12-23 01:40:25 +00:00
parent 72c1f96001
commit bce3bbcb76
10 changed files with 163 additions and 149 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

5
sim/frv/ChangeLog
View file

@ -1,3 +1,8 @@
2008-12-23 Hans-Peter Nilsson <hp@axis.com>
* arch.c, arch.h, cpu.c, cpu.h, cpuall.h, decode.c, decode.h,
model.c, sem.c: Regenerate.
2008-07-11 Hans-Peter Nilsson <hp@axis.com>
* configure: Regenerate to track ../common/common.m4 changes.

23
sim/frv/arch.c
View file

@ -2,22 +2,23 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996-2005 Free Software Foundation, Inc.
Copyright 1996-2007 Free Software Foundation, Inc.
This file is part of the GNU simulators.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This file is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
It is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/

23
sim/frv/arch.h
View file

@ -2,22 +2,23 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996-2005 Free Software Foundation, Inc.
Copyright 1996-2007 Free Software Foundation, Inc.
This file is part of the GNU simulators.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This file is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
It is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/

23
sim/frv/cpu.c
View file

@ -2,22 +2,23 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996-2005 Free Software Foundation, Inc.
Copyright 1996-2007 Free Software Foundation, Inc.
This file is part of the GNU simulators.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This file is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
It is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/

23
sim/frv/cpu.h
View file

@ -2,22 +2,23 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996-2005 Free Software Foundation, Inc.
Copyright 1996-2007 Free Software Foundation, Inc.
This file is part of the GNU simulators.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This file is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
It is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/

23
sim/frv/cpuall.h
View file

@ -2,22 +2,23 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996-2005 Free Software Foundation, Inc.
Copyright 1996-2007 Free Software Foundation, Inc.
This file is part of the GNU simulators.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This file is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
It is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/

23
sim/frv/decode.c
View file

@ -2,22 +2,23 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996-2005 Free Software Foundation, Inc.
Copyright 1996-2007 Free Software Foundation, Inc.
This file is part of the GNU simulators.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This file is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
It is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/

23
sim/frv/decode.h
View file

@ -2,22 +2,23 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996-2005 Free Software Foundation, Inc.
Copyright 1996-2007 Free Software Foundation, Inc.
This file is part of the GNU simulators.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This file is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
It is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/

23
sim/frv/model.c
View file

@ -2,22 +2,23 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996-2005 Free Software Foundation, Inc.
Copyright 1996-2007 Free Software Foundation, Inc.
This file is part of the GNU simulators.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This file is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
It is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/

123
sim/frv/sem.c
View file

@ -2,22 +2,23 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996-2005 Free Software Foundation, Inc.
Copyright 1996-2007 Free Software Foundation, Inc.
This file is part of the GNU simulators.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This file is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
It is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
*/
@ -481,7 +482,7 @@ SEM_FN_NAME (frvbf,smass) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
DI opval = (ANDIF (ANDIF (GTDI (MULDI (EXTSIDI (GET_H_GR (FLD (f_GRi))), EXTSIDI (GET_H_GR (FLD (f_GRj)))), 0), GTDI (GET_H_IACC0 (((UINT) 0)), 0)), LTDI (SUBDI (9223372036854775807, MULDI (EXTSIDI (GET_H_GR (FLD (f_GRi))), EXTSIDI (GET_H_GR (FLD (f_GRj))))), GET_H_IACC0 (((UINT) 0))))) ? (MAKEDI (2147483647, 0xffffffff)) : (ANDIF (ANDIF (LTDI (MULDI (EXTSIDI (GET_H_GR (FLD (f_GRi))), EXTSIDI (GET_H_GR (FLD (f_GRj)))), 0), LTDI (GET_H_IACC0 (((UINT) 0)), 0)), GTDI (SUBDI (9223372036854775808, MULDI (EXTSIDI (GET_H_GR (FLD (f_GRi))), EXTSIDI (GET_H_GR (FLD (f_GRj))))), GET_H_IACC0 (((UINT) 0))))) ? (MAKEDI (0x80000000, 0)) : (ADDDI (GET_H_IACC0 (((UINT) 0)), MULDI (EXTSIDI (GET_H_GR (FLD (f_GRi))), EXTSIDI (GET_H_GR (FLD (f_GRj))))));
DI opval = (ANDIF (ANDIF (GTDI (MULDI (EXTSIDI (GET_H_GR (FLD (f_GRi))), EXTSIDI (GET_H_GR (FLD (f_GRj)))), 0), GTDI (GET_H_IACC0 (((UINT) 0)), 0)), LTDI (SUBDI (MAKEDI (2147483647, 0xffffffff), MULDI (EXTSIDI (GET_H_GR (FLD (f_GRi))), EXTSIDI (GET_H_GR (FLD (f_GRj))))), GET_H_IACC0 (((UINT) 0))))) ? (MAKEDI (2147483647, 0xffffffff)) : (ANDIF (ANDIF (LTDI (MULDI (EXTSIDI (GET_H_GR (FLD (f_GRi))), EXTSIDI (GET_H_GR (FLD (f_GRj)))), 0), LTDI (GET_H_IACC0 (((UINT) 0)), 0)), GTDI (SUBDI (MAKEDI (0x80000000, 0), MULDI (EXTSIDI (GET_H_GR (FLD (f_GRi))), EXTSIDI (GET_H_GR (FLD (f_GRj))))), GET_H_IACC0 (((UINT) 0))))) ? (MAKEDI (0x80000000, 0)) : (ADDDI (GET_H_IACC0 (((UINT) 0)), MULDI (EXTSIDI (GET_H_GR (FLD (f_GRi))), EXTSIDI (GET_H_GR (FLD (f_GRj))))));
sim_queue_fn_di_write (current_cpu, frvbf_h_iacc0_set, ((UINT) 0), opval);
TRACE_RESULT (current_cpu, abuf, "iacc0", 'D', opval);
}
@ -502,7 +503,7 @@ SEM_FN_NAME (frvbf,smsss) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
DI opval = (ANDIF (ANDIF (LTDI (MULDI (EXTSIDI (GET_H_GR (FLD (f_GRi))), EXTSIDI (GET_H_GR (FLD (f_GRj)))), 0), GTDI (GET_H_IACC0 (((UINT) 0)), 0)), LTDI (ADDDI (9223372036854775807, MULDI (EXTSIDI (GET_H_GR (FLD (f_GRi))), EXTSIDI (GET_H_GR (FLD (f_GRj))))), GET_H_IACC0 (((UINT) 0))))) ? (MAKEDI (2147483647, 0xffffffff)) : (ANDIF (ANDIF (GTDI (MULDI (EXTSIDI (GET_H_GR (FLD (f_GRi))), EXTSIDI (GET_H_GR (FLD (f_GRj)))), 0), LTDI (GET_H_IACC0 (((UINT) 0)), 0)), GTDI (ADDDI (9223372036854775808, MULDI (EXTSIDI (GET_H_GR (FLD (f_GRi))), EXTSIDI (GET_H_GR (FLD (f_GRj))))), GET_H_IACC0 (((UINT) 0))))) ? (MAKEDI (0x80000000, 0)) : (SUBDI (GET_H_IACC0 (((UINT) 0)), MULDI (EXTSIDI (GET_H_GR (FLD (f_GRi))), EXTSIDI (GET_H_GR (FLD (f_GRj))))));
DI opval = (ANDIF (ANDIF (LTDI (MULDI (EXTSIDI (GET_H_GR (FLD (f_GRi))), EXTSIDI (GET_H_GR (FLD (f_GRj)))), 0), GTDI (GET_H_IACC0 (((UINT) 0)), 0)), LTDI (ADDDI (MAKEDI (2147483647, 0xffffffff), MULDI (EXTSIDI (GET_H_GR (FLD (f_GRi))), EXTSIDI (GET_H_GR (FLD (f_GRj))))), GET_H_IACC0 (((UINT) 0))))) ? (MAKEDI (2147483647, 0xffffffff)) : (ANDIF (ANDIF (GTDI (MULDI (EXTSIDI (GET_H_GR (FLD (f_GRi))), EXTSIDI (GET_H_GR (FLD (f_GRj)))), 0), LTDI (GET_H_IACC0 (((UINT) 0)), 0)), GTDI (ADDDI (MAKEDI (0x80000000, 0), MULDI (EXTSIDI (GET_H_GR (FLD (f_GRi))), EXTSIDI (GET_H_GR (FLD (f_GRj))))), GET_H_IACC0 (((UINT) 0))))) ? (MAKEDI (0x80000000, 0)) : (SUBDI (GET_H_IACC0 (((UINT) 0)), MULDI (EXTSIDI (GET_H_GR (FLD (f_GRi))), EXTSIDI (GET_H_GR (FLD (f_GRj))))));
sim_queue_fn_di_write (current_cpu, frvbf_h_iacc0_set, ((UINT) 0), opval);
TRACE_RESULT (current_cpu, abuf, "iacc0", 'D', opval);
}
@ -22941,10 +22942,10 @@ frvbf_media_acc_not_aligned (current_cpu);
{
DI tmp_tmp;
tmp_tmp = ADDDI (GET_H_ACC40S (FLD (f_ACC40Si)), GET_H_ACC40S (((FLD (f_ACC40Si)) + (1))));
if (GTDI (tmp_tmp, 549755813887)) {
if (GTDI (tmp_tmp, MAKEDI (127, 0xffffffff))) {
{
{
DI opval = 549755813887;
DI opval = MAKEDI (127, 0xffffffff);
sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
written |= (1 << 4);
TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
@ -22952,10 +22953,10 @@ if (GTDI (tmp_tmp, 549755813887)) {
frvbf_media_overflow (current_cpu, 8);
}
} else {
if (LTDI (tmp_tmp, INVDI (549755813887))) {
if (LTDI (tmp_tmp, INVDI (MAKEDI (127, 0xffffffff)))) {
{
{
DI opval = INVDI (549755813887);
DI opval = INVDI (MAKEDI (127, 0xffffffff));
sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
written |= (1 << 4);
TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
@ -23000,10 +23001,10 @@ frvbf_media_acc_not_aligned (current_cpu);
{
DI tmp_tmp;
tmp_tmp = SUBDI (GET_H_ACC40S (FLD (f_ACC40Si)), GET_H_ACC40S (((FLD (f_ACC40Si)) + (1))));
if (GTDI (tmp_tmp, 549755813887)) {
if (GTDI (tmp_tmp, MAKEDI (127, 0xffffffff))) {
{
{
DI opval = 549755813887;
DI opval = MAKEDI (127, 0xffffffff);
sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
written |= (1 << 4);
TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
@ -23011,10 +23012,10 @@ if (GTDI (tmp_tmp, 549755813887)) {
frvbf_media_overflow (current_cpu, 8);
}
} else {
if (LTDI (tmp_tmp, INVDI (549755813887))) {
if (LTDI (tmp_tmp, INVDI (MAKEDI (127, 0xffffffff)))) {
{
{
DI opval = INVDI (549755813887);
DI opval = INVDI (MAKEDI (127, 0xffffffff));
sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
written |= (1 << 4);
TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
@ -23063,10 +23064,10 @@ frvbf_media_acc_not_aligned (current_cpu);
{
DI tmp_tmp;
tmp_tmp = ADDDI (GET_H_ACC40S (FLD (f_ACC40Si)), GET_H_ACC40S (((FLD (f_ACC40Si)) + (1))));
if (GTDI (tmp_tmp, 549755813887)) {
if (GTDI (tmp_tmp, MAKEDI (127, 0xffffffff))) {
{
{
DI opval = 549755813887;
DI opval = MAKEDI (127, 0xffffffff);
sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
written |= (1 << 6);
TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
@ -23074,10 +23075,10 @@ if (GTDI (tmp_tmp, 549755813887)) {
frvbf_media_overflow (current_cpu, 8);
}
} else {
if (LTDI (tmp_tmp, INVDI (549755813887))) {
if (LTDI (tmp_tmp, INVDI (MAKEDI (127, 0xffffffff)))) {
{
{
DI opval = INVDI (549755813887);
DI opval = INVDI (MAKEDI (127, 0xffffffff));
sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
written |= (1 << 6);
TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
@ -23097,10 +23098,10 @@ frvbf_media_overflow (current_cpu, 8);
{
DI tmp_tmp;
tmp_tmp = ADDDI (GET_H_ACC40S (((FLD (f_ACC40Si)) + (2))), GET_H_ACC40S (((FLD (f_ACC40Si)) + (3))));
if (GTDI (tmp_tmp, 549755813887)) {
if (GTDI (tmp_tmp, MAKEDI (127, 0xffffffff))) {
{
{
DI opval = 549755813887;
DI opval = MAKEDI (127, 0xffffffff);
sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval);
written |= (1 << 7);
TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
@ -23108,10 +23109,10 @@ if (GTDI (tmp_tmp, 549755813887)) {
frvbf_media_overflow (current_cpu, 4);
}
} else {
if (LTDI (tmp_tmp, INVDI (549755813887))) {
if (LTDI (tmp_tmp, INVDI (MAKEDI (127, 0xffffffff)))) {
{
{
DI opval = INVDI (549755813887);
DI opval = INVDI (MAKEDI (127, 0xffffffff));
sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval);
written |= (1 << 7);
TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
@ -23162,10 +23163,10 @@ frvbf_media_acc_not_aligned (current_cpu);
{
DI tmp_tmp;
tmp_tmp = SUBDI (GET_H_ACC40S (FLD (f_ACC40Si)), GET_H_ACC40S (((FLD (f_ACC40Si)) + (1))));
if (GTDI (tmp_tmp, 549755813887)) {
if (GTDI (tmp_tmp, MAKEDI (127, 0xffffffff))) {
{
{
DI opval = 549755813887;
DI opval = MAKEDI (127, 0xffffffff);
sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
written |= (1 << 6);
TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
@ -23173,10 +23174,10 @@ if (GTDI (tmp_tmp, 549755813887)) {
frvbf_media_overflow (current_cpu, 8);
}
} else {
if (LTDI (tmp_tmp, INVDI (549755813887))) {
if (LTDI (tmp_tmp, INVDI (MAKEDI (127, 0xffffffff)))) {
{
{
DI opval = INVDI (549755813887);
DI opval = INVDI (MAKEDI (127, 0xffffffff));
sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
written |= (1 << 6);
TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
@ -23196,10 +23197,10 @@ frvbf_media_overflow (current_cpu, 8);
{
DI tmp_tmp;
tmp_tmp = SUBDI (GET_H_ACC40S (((FLD (f_ACC40Si)) + (2))), GET_H_ACC40S (((FLD (f_ACC40Si)) + (3))));
if (GTDI (tmp_tmp, 549755813887)) {
if (GTDI (tmp_tmp, MAKEDI (127, 0xffffffff))) {
{
{
DI opval = 549755813887;
DI opval = MAKEDI (127, 0xffffffff);
sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval);
written |= (1 << 7);
TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
@ -23207,10 +23208,10 @@ if (GTDI (tmp_tmp, 549755813887)) {
frvbf_media_overflow (current_cpu, 4);
}
} else {
if (LTDI (tmp_tmp, INVDI (549755813887))) {
if (LTDI (tmp_tmp, INVDI (MAKEDI (127, 0xffffffff)))) {
{
{
DI opval = INVDI (549755813887);
DI opval = INVDI (MAKEDI (127, 0xffffffff));
sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval);
written |= (1 << 7);
TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
@ -23261,10 +23262,10 @@ frvbf_media_acc_not_aligned (current_cpu);
{
DI tmp_tmp;
tmp_tmp = ADDDI (GET_H_ACC40S (FLD (f_ACC40Si)), GET_H_ACC40S (((FLD (f_ACC40Si)) + (1))));
if (GTDI (tmp_tmp, 549755813887)) {
if (GTDI (tmp_tmp, MAKEDI (127, 0xffffffff))) {
{
{
DI opval = 549755813887;
DI opval = MAKEDI (127, 0xffffffff);
sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
written |= (1 << 4);
TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
@ -23272,10 +23273,10 @@ if (GTDI (tmp_tmp, 549755813887)) {
frvbf_media_overflow (current_cpu, 8);
}
} else {
if (LTDI (tmp_tmp, INVDI (549755813887))) {
if (LTDI (tmp_tmp, INVDI (MAKEDI (127, 0xffffffff)))) {
{
{
DI opval = INVDI (549755813887);
DI opval = INVDI (MAKEDI (127, 0xffffffff));
sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
written |= (1 << 4);
TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
@ -23295,10 +23296,10 @@ frvbf_media_overflow (current_cpu, 8);
{
DI tmp_tmp;
tmp_tmp = SUBDI (GET_H_ACC40S (FLD (f_ACC40Si)), GET_H_ACC40S (((FLD (f_ACC40Si)) + (1))));
if (GTDI (tmp_tmp, 549755813887)) {
if (GTDI (tmp_tmp, MAKEDI (127, 0xffffffff))) {
{
{
DI opval = 549755813887;
DI opval = MAKEDI (127, 0xffffffff);
sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval);
written |= (1 << 5);
TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
@ -23306,10 +23307,10 @@ if (GTDI (tmp_tmp, 549755813887)) {
frvbf_media_overflow (current_cpu, 4);
}
} else {
if (LTDI (tmp_tmp, INVDI (549755813887))) {
if (LTDI (tmp_tmp, INVDI (MAKEDI (127, 0xffffffff)))) {
{
{
DI opval = INVDI (549755813887);
DI opval = INVDI (MAKEDI (127, 0xffffffff));
sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval);
written |= (1 << 5);
TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
@ -23360,10 +23361,10 @@ frvbf_media_acc_not_aligned (current_cpu);
{
DI tmp_tmp;
tmp_tmp = ADDDI (GET_H_ACC40S (FLD (f_ACC40Si)), GET_H_ACC40S (((FLD (f_ACC40Si)) + (1))));
if (GTDI (tmp_tmp, 549755813887)) {
if (GTDI (tmp_tmp, MAKEDI (127, 0xffffffff))) {
{
{
DI opval = 549755813887;
DI opval = MAKEDI (127, 0xffffffff);
sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
written |= (1 << 6);
TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
@ -23371,10 +23372,10 @@ if (GTDI (tmp_tmp, 549755813887)) {
frvbf_media_overflow (current_cpu, 8);
}
} else {
if (LTDI (tmp_tmp, INVDI (549755813887))) {
if (LTDI (tmp_tmp, INVDI (MAKEDI (127, 0xffffffff)))) {
{
{
DI opval = INVDI (549755813887);
DI opval = INVDI (MAKEDI (127, 0xffffffff));
sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, FLD (f_ACC40Sk), opval);
written |= (1 << 6);
TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
@ -23394,10 +23395,10 @@ frvbf_media_overflow (current_cpu, 8);
{
DI tmp_tmp;
tmp_tmp = SUBDI (GET_H_ACC40S (FLD (f_ACC40Si)), GET_H_ACC40S (((FLD (f_ACC40Si)) + (1))));
if (GTDI (tmp_tmp, 549755813887)) {
if (GTDI (tmp_tmp, MAKEDI (127, 0xffffffff))) {
{
{
DI opval = 549755813887;
DI opval = MAKEDI (127, 0xffffffff);
sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval);
written |= (1 << 7);
TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
@ -23405,10 +23406,10 @@ if (GTDI (tmp_tmp, 549755813887)) {
frvbf_media_overflow (current_cpu, 4);
}
} else {
if (LTDI (tmp_tmp, INVDI (549755813887))) {
if (LTDI (tmp_tmp, INVDI (MAKEDI (127, 0xffffffff)))) {
{
{
DI opval = INVDI (549755813887);
DI opval = INVDI (MAKEDI (127, 0xffffffff));
sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (1)), opval);
written |= (1 << 7);
TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
@ -23428,10 +23429,10 @@ frvbf_media_overflow (current_cpu, 4);
{
DI tmp_tmp;
tmp_tmp = ADDDI (GET_H_ACC40S (((FLD (f_ACC40Si)) + (2))), GET_H_ACC40S (((FLD (f_ACC40Si)) + (3))));
if (GTDI (tmp_tmp, 549755813887)) {
if (GTDI (tmp_tmp, MAKEDI (127, 0xffffffff))) {
{
{
DI opval = 549755813887;
DI opval = MAKEDI (127, 0xffffffff);
sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (2)), opval);
written |= (1 << 8);
TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
@ -23439,10 +23440,10 @@ if (GTDI (tmp_tmp, 549755813887)) {
frvbf_media_overflow (current_cpu, 2);
}
} else {
if (LTDI (tmp_tmp, INVDI (549755813887))) {
if (LTDI (tmp_tmp, INVDI (MAKEDI (127, 0xffffffff)))) {
{
{
DI opval = INVDI (549755813887);
DI opval = INVDI (MAKEDI (127, 0xffffffff));
sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (2)), opval);
written |= (1 << 8);
TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
@ -23462,10 +23463,10 @@ frvbf_media_overflow (current_cpu, 2);
{
DI tmp_tmp;
tmp_tmp = SUBDI (GET_H_ACC40S (((FLD (f_ACC40Si)) + (2))), GET_H_ACC40S (((FLD (f_ACC40Si)) + (3))));
if (GTDI (tmp_tmp, 549755813887)) {
if (GTDI (tmp_tmp, MAKEDI (127, 0xffffffff))) {
{
{
DI opval = 549755813887;
DI opval = MAKEDI (127, 0xffffffff);
sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (3)), opval);
written |= (1 << 9);
TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);
@ -23473,10 +23474,10 @@ if (GTDI (tmp_tmp, 549755813887)) {
frvbf_media_overflow (current_cpu, 1);
}
} else {
if (LTDI (tmp_tmp, INVDI (549755813887))) {
if (LTDI (tmp_tmp, INVDI (MAKEDI (127, 0xffffffff)))) {
{
{
DI opval = INVDI (549755813887);
DI opval = INVDI (MAKEDI (127, 0xffffffff));
sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, ((FLD (f_ACC40Sk)) + (3)), opval);
written |= (1 << 9);
TRACE_RESULT (current_cpu, abuf, "acc40S", 'D', opval);