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Fix for gold linking tlsdesc into an executable with -pie.

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(Also included in this patch is a minor typo fix in gold/ChangeLog.)

When linking the following tlsdesc access sequence into an executable with -pie,

     adrp    x0, :tlsdesc:tls_gd
     ldr     x1, [x0, #:tlsdesc_lo12:tls_gd]
     add     x0, x0, :tlsdesc_lo12:tls_gd
     .tlsdesccall    tls_gd
     blr	     x1
     mrs	     x1, tpidr_el0
     add	     x0, x1, x0
     ldr	     w0, [x0]

current gold-aarch64 backend does tls-desc-gd-to-ie relaxation, into

       adrp    x0, 1000 <__FRAME_END__+0x720>
       ldr     x1, [x0,#4064]	  ;; <=== the target register should be x0
       nop
       nop
       mrs	x1, tpidr_el0
       add	x0, x1, x0
       ldr	w0, [x0]

This code is wrong. The fix changes ldr target register into x0.
This commit is contained in:
Han Shen 2014-11-26 10:34:46 -08:00
parent a11652892c
commit bb779192ae
2 changed files with 11 additions and 1 deletions
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7
gold/ChangeLog
View file

@ -1,3 +1,8 @@
2014-11-26 Jing Yu <jingyu@google.com>
* aarch64.cc (Relocate::tls_desc_gd_to_ie): Set ldr target
register to be x0 when to relax TLSDESC_LD64_LO12.
2014-11-26 Alan Modra <amodra@gmail.com>
* powerpc.cc (struct Stub_table_owner): New.
@ -162,7 +167,7 @@
* aarch64.cc (AArch64_relocate_functions::maybe_apply_stub):
Add "typename" keyword.
2014-09-22 Han Shen <shenhan@google.com>
2014-10-15 Han Shen <shenhan@google.com>
Jing Yu <jingyu@google.com>
Patch for gold aarch64 backend to support relaxation.

5
gold/aarch64.cc
View file

@ -6536,6 +6536,11 @@ Target_aarch64<size, big_endian>::Relocate::tls_desc_gd_to_ie(
case elfcpp::R_AARCH64_TLSDESC_LD64_LO12:
{
// Set ldr target register to be x0.
Insntype insn = elfcpp::Swap<32, big_endian>::readval(ip);
insn &= 0xffffffe0;
elfcpp::Swap<32, big_endian>::writeval(ip, insn);
// Do relocation.
const AArch64_reloc_property* reloc_property =
aarch64_reloc_property_table->get_reloc_property(
elfcpp::R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC);