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* gas/config/tc-arm.c (insns): Add DCPS instruction.

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* gas/testsuite/gas/arm/armv8-a.d: Update.
	* gas/testsuite/gas/arm/armv8-a.s: Likewise.
	* opcodes/arm-dis.c (thumb32_opcodes): Add DCPS instruction.
This commit is contained in:
Matthew Gretton-Dann 2012-08-24 08:02:09 +00:00
parent 53c4b28b4f
commit b79f7053dd
7 changed files with 26 additions and 0 deletions
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4
gas/ChangeLog
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@ -1,3 +1,7 @@
2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
* config/tc-arm.c (insns): Add DCPS instruction.
2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
* config/tc-arm.c (T16_32_TAB): Add _sevl.

6
gas/config/tc-arm.c
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@ -17975,6 +17975,12 @@ static const struct asm_opcode insns[] =
tCE("sevl", 320f005, _sevl, 0, (), noargs, t_hint),
#undef ARM_VARIANT
#define ARM_VARIANT NULL
TUF("dcps1", 0, f78f8001, 0, (), noargs, noargs),
TUF("dcps2", 0, f78f8002, 0, (), noargs, noargs),
TUF("dcps3", 0, f78f8003, 0, (), noargs, noargs),
#undef ARM_VARIANT
#define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
#undef THUMB_VARIANT

5
gas/testsuite/ChangeLog
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@ -1,3 +1,8 @@
2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
* gas/arm/armv8-a.d: Update.
* gas/arm/armv8-a.s: Likewise.
2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
* gas/arm/armv8-a.s: New testcase.

3
gas/testsuite/gas/arm/armv8-a.d
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@ -8,3 +8,6 @@ Disassembly of section .text:
0[0-9a-f]+ <[^>]+> bf50 sevl
0[0-9a-f]+ <[^>]+> bf50 sevl
0[0-9a-f]+ <[^>]+> f3af 8005 sevl.w
0[0-9a-f]+ <[^>]+> f78f 8001 dcps1
0[0-9a-f]+ <[^>]+> f78f 8002 dcps2
0[0-9a-f]+ <[^>]+> f78f 8003 dcps3

3
gas/testsuite/gas/arm/armv8-a.s
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@ -12,3 +12,6 @@ bar:
sevl
sevl.n
sevl.w
dcps1
dcps2
dcps3

4
opcodes/ChangeLog
View file

@ -1,3 +1,7 @@
2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
* arm-dis.c (thumb32_opcodes): Add DCPS instruction.
2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
* arm-dis.c (arm_opcodes): Add SEVL.

1
opcodes/arm-dis.c
View file

@ -1421,6 +1421,7 @@ static const struct opcode32 thumb32_opcodes[] =
{
/* V8 instructions. */
{ARM_EXT_V8, 0xf3af8005, 0xffffffff, "sevl%c.w"},
{ARM_EXT_V8, 0xf78f8000, 0xfffffffc, "dcps%0-1d"},
/* V7 instructions. */
{ARM_EXT_V7, 0xf910f000, 0xff70f000, "pli%c\t%a"},