* m32r-sim.h (M32R_MISC_PROFILE): New members insn_cycles, cti_stall,
load_stall,biggest_cycles. * m32r.c (m32r_model_mark_get_h_gr): Update. (m32r_model_init_insn_cycles,m32r_model_update_insn_cycles): New fns. (m32r_model_record_cti,m32r_model_record_cycles): New functions. * mloop.in: Call cycle init/update fns. * model.c: Regenerate. * m32rx.c (m32rx_model_mark_get_h_gr): Update. * mloopx.in: Call cycle init/update fns. * modelx.c: Regenerate.
This commit is contained in:
Doug Evans
parent
403bed787e
commit
b4cbaee405
2 changed files with 200 additions and 1 deletions
187
sim/m32r/mloop.in
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187
sim/m32r/mloop.in
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# Simulator main loop for m32r. -*- C -*-
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# Copyright (C) 1996, 1997 Free Software Foundation, Inc.
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#
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# This file is part of the GNU Simulators.
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; either version 2, or (at your option)
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# any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License along
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# with this program; if not, write to the Free Software Foundation, Inc.,
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# 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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# Syntax:
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# /bin/sh mainloop.in init|support|{full,fast}-{extract,exec}-{scache,noscache}
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# ??? After a few more ports are done, revisit.
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# Will eventually need to machine generate a lot of this.
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case "x$1" in
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xsupport)
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cat <<EOF
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static INLINE void
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extract16 (SIM_CPU *current_cpu, PCADDR pc, insn_t insn,
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SCACHE *sc, int fast_p)
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{
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const IDESC *d = @cpu@_decode (current_cpu, pc, insn);
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(*d->extract) (current_cpu, pc, insn, &sc->argbuf);
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if (fast_p)
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{
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#if WITH_SEM_SWITCH_FAST
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#ifdef __GNUC__
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sc->semantic.sem_case = d->sem_fast_lab;
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#else
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sc->semantic.sem_case = d->num;
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#endif
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#else
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sc->semantic.sem_fast = d->sem_fast;
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#endif
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}
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else
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{
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sc->semantic.sem_full = d->sem_full;
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}
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sc->argbuf.idesc = d;
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sc->next = pc + 2;
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}
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static INLINE void
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extract32 (SIM_CPU *current_cpu, PCADDR pc, insn_t insn,
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SCACHE *sc, int fast_p)
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{
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const IDESC *d = @cpu@_decode (current_cpu, pc, (USI) insn >> 16);
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(*d->extract) (current_cpu, pc, insn, &sc->argbuf);
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if (fast_p)
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{
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#if WITH_SEM_SWITCH_FAST
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#ifdef __GNUC__
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sc->semantic.sem_case = d->sem_fast_lab;
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#else
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sc->semantic.sem_case = d->num;
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#endif
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#else
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sc->semantic.sem_fast_fn = d->sem_fast;
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#endif
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}
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else
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{
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sc->semantic.sem_full = d->sem_full;
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}
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sc->argbuf.idesc = d;
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sc->next = pc + 4;
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}
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static INLINE PCADDR
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execute (SIM_CPU *current_cpu, SCACHE *sc, int fast_p)
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{
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PCADDR pc;
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if (fast_p)
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{
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#if WITH_SCACHE && ! WITH_SEM_SWITCH_FAST
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pc = (*sc->semantic.sem_fast) (current_cpu, sc);
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#else
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#if 0
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pc = (*sc->semantic.sem_full) (current_cpu, &sc->argbuf);
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#else
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pc = (*sc->semantic.sem_full) (current_cpu, sc);
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#endif
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#endif
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}
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else
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{
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m32r_model_init_insn_cycles (current_cpu, 1);
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TRACE_INSN_INIT (current_cpu, 1);
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TRACE_INSN (current_cpu, sc->argbuf.idesc->opcode, (const struct argbuf *) &sc->argbuf, sc->argbuf.addr);
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#if 0
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pc = (*sc->semantic.sem_full) (current_cpu, &sc->argbuf);
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#else
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pc = (*sc->semantic.sem_full) (current_cpu, sc);
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#endif
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m32r_model_update_insn_cycles (current_cpu, 1);
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TRACE_INSN_FINI (current_cpu, 1);
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}
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return pc;
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}
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EOF
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;;
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xinit)
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cat <<EOF
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/*xxxinit*/
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EOF
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;;
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xfull-extract-* | xfast-extract-*)
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cat <<EOF
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{
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PCADDR pc = CPU (h_pc);
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if ((pc & 3) != 0)
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{
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/* This only occurs when single stepping.
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The test is unnecessary otherwise, but the cost is teensy,
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compared with decoding/extraction. */
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UHI insn = GETIMEMUHI (current_cpu, pc);
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extract16 (current_cpu, pc, insn & 0x7fff, sc, FAST_P);
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}
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else
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{
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USI insn = GETIMEMUSI (current_cpu, pc);
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if ((SI) insn < 0)
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{
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extract32 (current_cpu, pc, insn, sc, FAST_P);
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}
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else
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{
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extract16 (current_cpu, pc, insn >> 16, sc, FAST_P);
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extract16 (current_cpu, pc + 2, insn & 0x7fff, sc + 1, FAST_P);
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/* The m32r doesn't support parallel execution. */
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if ((insn & 0x8000) != 0
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&& (insn & 0x7fff) != 0x7000) /* parallel nops are ok */
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sim_engine_illegal_insn (current_cpu, pc);
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}
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}
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}
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EOF
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;;
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xfull-exec-* | xfast-exec-*)
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cat <<EOF
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{
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#if WITH_SCACHE && FAST_P && WITH_SEM_SWITCH_FAST
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#define DEFINE_SWITCH
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#include "sem-switch.c"
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#else
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PCADDR new_pc = execute (current_cpu, sc, FAST_P);
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CPU (h_pc) = new_pc;
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#endif
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}
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EOF
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;;
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*)
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echo "Invalid argument to mainloop.in: $1" >&2
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exit 1
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;;
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esac
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@ -58,6 +58,7 @@ cat <<EOF
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d1 = m32rx_decode (current_cpu, pc, insn);
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abufs[0].insn = insn;
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abufs[0].idesc = d1;
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abufs[0].addr = pc; /* FIXME: wip */
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icount = 1;
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}
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else
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d1 = m32rx_decode (current_cpu, pc, insn >> 16);
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abufs[0].insn = insn;
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abufs[0].idesc = d1;
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abufs[0].addr = pc; /* FIXME: wip */
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icount = 1;
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}
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else
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@ -77,9 +79,11 @@ cat <<EOF
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d1 = m32rx_decode (current_cpu, pc, insn >> 16);
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abufs[0].insn = insn >> 16;
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abufs[0].idesc = d1;
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d2 = m32rx_decode (current_cpu, pc, insn & 0x7fff);
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abufs[0].addr = pc; /* FIXME: wip */
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d2 = m32rx_decode (current_cpu, pc + 2, insn & 0x7fff);
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abufs[1].insn = insn & 0x7fff;
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abufs[1].idesc = d2;
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abufs[1].addr = pc + 2; /* FIXME: wip */
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icount = 2;
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}
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else
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d1 = m32rx_decode (current_cpu, pc, insn >> 16);
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abufs[0].insn = insn >> 16;
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abufs[0].idesc = d1;
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abufs[0].addr = pc; /* FIXME: wip */
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icount = 1;
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}
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}
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@ -130,9 +135,11 @@ cat <<EOF
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}
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#endif
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m32r_model_init_insn_cycles (current_cpu, 1);
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TRACE_INSN_INIT (current_cpu, 1);
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TRACE_INSN (current_cpu, d1->opcode, sem_arg, CPU (h_pc));
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new_pc = (*d1->sem_full) (current_cpu, sem_arg, par_exec);
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m32r_model_update_insn_cycles (current_cpu, icount == 1);
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TRACE_INSN_FINI (current_cpu, icount == 1);
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/* The result of the semantic fn is one of:
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@ -164,10 +171,12 @@ cat <<EOF
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++sem_arg;
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++par_exec;
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m32r_model_init_insn_cycles (current_cpu, 0);
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TRACE_INSN_INIT (current_cpu, 0);
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TRACE_INSN (current_cpu, d2->opcode, sem_arg, CPU (h_pc) + 2);
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/* pc2 isn't used. It's assigned a value for debugging. */
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pc2 = (*d2->sem_full) (current_cpu, sem_arg, par_exec);
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m32r_model_update_insn_cycles (current_cpu, 1);
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TRACE_INSN_FINI (current_cpu, 1);
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if (NEW_PC_BRANCH_P (new_pc))
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@ -175,6 +184,9 @@ cat <<EOF
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else
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CPU (h_pc) += 4;
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}
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/* Update count of parallel insns executed. */
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PROFILE_COUNT_PARINSNS (current_cpu);
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}
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else if (NEW_PC_BRANCH_P (new_pc))
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CPU (h_pc) = new_pc;
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