Rewrite simulator floating point module. Do not rely on host FP
implementation. Add preliminary support for different IEEE-754 rounding modes. Implement SQRT in software. Update TiC80 simulator. Add sim-fpu -> TestFloat interface for testing.
This commit is contained in:
Andrew Cagney
parent
22b23d7deb
commit
b3c77578dc
4 changed files with 602 additions and 41 deletions
538
sim/testsuite/common/fpu-tst.c
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538
sim/testsuite/common/fpu-tst.c
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@ -0,0 +1,538 @@
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#define ASSERT(EXPRESSION) \
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do { \
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if (!(EXPRESSION)) { \
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fprintf (stderr, "%s:%d: assertion failed - %s\n", \
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__FILE__, __LINE__, #EXPRESSION); \
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abort (); \
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} \
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} while (0)
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#define SIM_BITS_INLINE (INCLUDE_MODULE | INCLUDED_BY_MODULE)
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#include "milieu.h"
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#include "softfloat.h"
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#include "systfloat.h"
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#include "systmodes.h"
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/* #define SIM_FPU_INLINE (INCLUDE_MODULE | INCLUDED_BY_MODULE) */
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#include "sim-bits.h"
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#include "sim-fpu.h"
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#include "sim-fpu.c"
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static int flags;
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int8
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syst_float_flags_clear ()
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{
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int old_flags = 0;
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int i = 1;
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while (flags >= i)
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{
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switch ((sim_fpu_status) (flags & i))
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{
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case sim_fpu_status_denorm:
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break;
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case sim_fpu_status_invalid_snan:
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case sim_fpu_status_invalid_qnan:
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case sim_fpu_status_invalid_isi:
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case sim_fpu_status_invalid_idi:
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case sim_fpu_status_invalid_zdz:
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case sim_fpu_status_invalid_imz:
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case sim_fpu_status_invalid_cvi:
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case sim_fpu_status_invalid_cmp:
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case sim_fpu_status_invalid_sqrt:
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old_flags |= float_flag_invalid; /* v */
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break;
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case sim_fpu_status_inexact:
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old_flags |= float_flag_inexact; /* x */
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break;
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case sim_fpu_status_overflow:
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old_flags |= float_flag_overflow; /* o */
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break;
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case sim_fpu_status_underflow:
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old_flags |= float_flag_underflow; /* u */
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break;
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case sim_fpu_status_invalid_div0:
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old_flags |= float_flag_divbyzero; /* z */
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break;
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case sim_fpu_status_rounded:
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break;
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}
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i <<= 1;
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}
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flags = 0;
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return old_flags;
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}
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sim_fpu_round rounding_mode;
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void
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syst_float_set_rounding_mode(int8 mode)
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{
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switch (mode)
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{
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case float_round_nearest_even:
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rounding_mode = sim_fpu_round_near;
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break;
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case float_round_down:
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rounding_mode = sim_fpu_round_down;
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break;
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case float_round_up:
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rounding_mode = sim_fpu_round_up;
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break;
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case float_round_to_zero:
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rounding_mode = sim_fpu_round_zero;
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break;
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}
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}
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float32
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syst_int32_to_float32(int32 a)
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{
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float32 z;
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sim_fpu s;
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flags |= sim_fpu_i32to (&s, a, rounding_mode);
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flags |= sim_fpu_round_32 (&s, rounding_mode, 0);
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sim_fpu_to32 (&z, &s);
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return z;
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}
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float64
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syst_int32_to_float64( int32 a )
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{
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float64 z;
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sim_fpu s;
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flags |= sim_fpu_i32to (&s, a, rounding_mode);
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sim_fpu_to64 (&z, &s);
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return z;
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}
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int32
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syst_float32_to_int32_round_to_zero( float32 a )
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{
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int32 z;
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sim_fpu s;
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sim_fpu_32to (&s, a);
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flags |= sim_fpu_to32i (&z, &s, sim_fpu_round_zero);
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return z;
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}
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float64
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syst_float32_to_float64 (float32 a)
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{
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float64 z;
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sim_fpu s;
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sim_fpu_32to (&s, a);
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flags |= sim_fpu_round_64 (&s, rounding_mode, 0);
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sim_fpu_to64 (&z, &s);
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return z;
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}
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float32 syst_float32_add( float32 a, float32 b )
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{
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float32 z;
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sim_fpu A;
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sim_fpu B;
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sim_fpu ans;
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sim_fpu_32to (&A, a);
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sim_fpu_32to (&B, b);
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#if 0
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fprintf (stdout, "\n ");
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sim_fpu_print_fpu (&A, (sim_fpu_print_func*) fprintf, stdout);
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fprintf (stdout, "\n+ ");
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sim_fpu_print_fpu (&B, (sim_fpu_print_func*) fprintf, stdout);
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fprintf (stdout, "\n= ");
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#endif
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flags |= sim_fpu_add (&ans, &A, &B);
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flags |= sim_fpu_round_32 (&ans, rounding_mode, 0);
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#if 0
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sim_fpu_print_fpu (&ans, (sim_fpu_print_func*) fprintf, stdout);
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fprintf (stdout, "\n");
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#endif
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sim_fpu_to32 (&z, &ans);
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return z;
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}
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float32 syst_float32_sub( float32 a, float32 b )
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{
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float32 z;
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sim_fpu A;
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sim_fpu B;
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sim_fpu ans;
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sim_fpu_32to (&A, a);
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sim_fpu_32to (&B, b);
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#if 0
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sim_fpu_print_fpu (&A, (sim_fpu_print_func*) fprintf, stdout);
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fprintf (stdout, " + ");
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sim_fpu_print_fpu (&B, (sim_fpu_print_func*) fprintf, stdout);
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fprintf (stdout, " = ");
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#endif
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flags |= sim_fpu_sub (&ans, &A, &B);
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flags |= sim_fpu_round_32 (&ans, rounding_mode, 0);
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#if 0
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sim_fpu_print_fpu (&ans, (sim_fpu_print_func*) fprintf, stdout);
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fprintf (stdout, "\n");
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#endif
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sim_fpu_to32 (&z, &ans);
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return z;
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}
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float32 syst_float32_mul( float32 a, float32 b )
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{
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float32 z;
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sim_fpu A;
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sim_fpu B;
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sim_fpu ans;
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sim_fpu_32to (&A, a);
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sim_fpu_32to (&B, b);
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#if 0
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sim_fpu_print_fpu (&A, (sim_fpu_print_func*) fprintf, stdout);
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fprintf (stdout, " + ");
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sim_fpu_print_fpu (&B, (sim_fpu_print_func*) fprintf, stdout);
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fprintf (stdout, " = ");
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#endif
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flags |= sim_fpu_mul (&ans, &A, &B);
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#if 0
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sim_fpu_print_fpu (&ans, (sim_fpu_print_func*) fprintf, stdout);
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#endif
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flags |= sim_fpu_round_32 (&ans, rounding_mode, 0);
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#if 0
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sim_fpu_print_status (flags, (sim_fpu_print_func*) fprintf, stdout);
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fprintf (stdout, "\n");
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#endif
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sim_fpu_to32 (&z, &ans);
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return z;
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}
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float32 syst_float32_div( float32 a, float32 b )
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{
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float32 z;
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sim_fpu A;
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sim_fpu B;
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sim_fpu ans;
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sim_fpu_32to (&A, a);
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sim_fpu_32to (&B, b);
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flags |= sim_fpu_div (&ans, &A, &B);
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flags |= sim_fpu_round_32 (&ans, rounding_mode, 0);
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sim_fpu_to32 (&z, &ans);
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return z;
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}
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float32 syst_float32_sqrt( float32 a )
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{
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float32 z;
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sim_fpu A;
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sim_fpu ans;
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sim_fpu_32to (&A, a);
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#if 0
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sim_fpu_print_fpu (&A, (sim_fpu_print_func*) fprintf, stdout);
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fprintf (stdout, " sqrt> ");
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#endif
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flags |= sim_fpu_sqrt (&ans, &A);
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#if 0
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sim_fpu_print_fpu (&ans, (sim_fpu_print_func*) fprintf, stdout);
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#endif
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flags |= sim_fpu_round_32 (&ans, rounding_mode, 0);
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#if 0
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fprintf (stdout, " (%x)\n", flags);
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#endif
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sim_fpu_to32 (&z, &ans);
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return z;
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}
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flag syst_float32_eq( float32 a, float32 b )
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{
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sim_fpu A;
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sim_fpu B;
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int is;
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sim_fpu_32to (&A, a);
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sim_fpu_32to (&B, b);
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flags |= (sim_fpu_eq (&is, &A, &B) & ~sim_fpu_status_invalid_qnan);
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return is;
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}
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flag syst_float32_eq_signaling( float32 a, float32 b )
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{
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sim_fpu A;
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sim_fpu B;
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int is;
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sim_fpu_32to (&A, a);
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sim_fpu_32to (&B, b);
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flags |= sim_fpu_eq (&is, &A, &B);
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return is;
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}
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flag syst_float32_le( float32 a, float32 b )
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{
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sim_fpu A;
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sim_fpu B;
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int is;
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sim_fpu_32to (&A, a);
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sim_fpu_32to (&B, b);
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flags |= sim_fpu_le (&is, &A, &B);
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return is;
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}
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flag syst_float32_le_quiet( float32 a, float32 b )
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{
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sim_fpu A;
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sim_fpu B;
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int is;
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sim_fpu_32to (&A, a);
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sim_fpu_32to (&B, b);
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flags |= (sim_fpu_le (&is, &A, &B) & ~sim_fpu_status_invalid_qnan);
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return is;
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}
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flag syst_float32_lt( float32 a, float32 b )
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{
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sim_fpu A;
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sim_fpu B;
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int is;
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sim_fpu_32to (&A, a);
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sim_fpu_32to (&B, b);
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flags |= sim_fpu_lt (&is, &A, &B);
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return is;
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}
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flag syst_float32_lt_quiet( float32 a, float32 b )
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{
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sim_fpu A;
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sim_fpu B;
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int is;
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sim_fpu_32to (&A, a);
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sim_fpu_32to (&B, b);
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flags |= (sim_fpu_lt (&is, &A, &B) & ~sim_fpu_status_invalid_qnan);
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return is;
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}
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int32 syst_float64_to_int32_round_to_zero( float64 a )
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{
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int32 z;
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sim_fpu s;
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sim_fpu_64to (&s, a);
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flags |= sim_fpu_to32i (&z, &s, sim_fpu_round_zero);
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return z;
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}
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float32 syst_float64_to_float32( float64 a )
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{
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float32 z;
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sim_fpu s;
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sim_fpu_64to (&s, a);
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#if 0
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sim_fpu_print_fpu (&s, (sim_fpu_print_func*) fprintf, stdout);
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fprintf (stdout, " -> ");
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#endif
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flags |= sim_fpu_round_32 (&s, rounding_mode, 0);
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#if 0
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sim_fpu_print_fpu (&s, (sim_fpu_print_func*) fprintf, stdout);
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sim_fpu_print_status (flags, (sim_fpu_print_func*) fprintf, stdout);
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printf ("\n");
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#endif
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sim_fpu_to32 (&z, &s);
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return z;
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}
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float64 syst_float64_add( float64 a, float64 b )
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{
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float64 z;
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sim_fpu A;
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sim_fpu B;
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sim_fpu ans;
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sim_fpu_64to (&A, a);
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sim_fpu_64to (&B, b);
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#if 0
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sim_fpu_print_fpu (&A, (sim_fpu_print_func*) fprintf, stdout);
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fprintf (stdout, " + ");
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sim_fpu_print_fpu (&B, (sim_fpu_print_func*) fprintf, stdout);
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fprintf (stdout, " = ");
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#endif
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flags |= sim_fpu_add (&ans, &A, &B);
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#if 0
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sim_fpu_print_fpu (&ans, (sim_fpu_print_func*) fprintf, stdout);
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#endif
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flags |= sim_fpu_round_64 (&ans, rounding_mode, 0);
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#if 0
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fprintf (stdout, " (%x)\n", flags);
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#endif
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sim_fpu_to64 (&z, &ans);
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return z;
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}
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float64 syst_float64_sub( float64 a, float64 b )
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{
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float64 z;
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sim_fpu A;
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sim_fpu B;
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sim_fpu ans;
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sim_fpu_64to (&A, a);
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sim_fpu_64to (&B, b);
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#if 0
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sim_fpu_print_fpu (&A, (sim_fpu_print_func*) fprintf, stdout);
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fprintf (stdout, " + ");
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sim_fpu_print_fpu (&B, (sim_fpu_print_func*) fprintf, stdout);
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fprintf (stdout, " = ");
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#endif
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flags |= sim_fpu_sub (&ans, &A, &B);
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#if 0
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sim_fpu_print_fpu (&ans, (sim_fpu_print_func*) fprintf, stdout);
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#endif
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flags |= sim_fpu_round_64 (&ans, rounding_mode, 0);
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#if 0
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fprintf (stdout, " (%x)\n", flags);
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#endif
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sim_fpu_to64 (&z, &ans);
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return z;
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}
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float64 syst_float64_mul( float64 a, float64 b )
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{
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float64 z;
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sim_fpu A;
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sim_fpu B;
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sim_fpu ans;
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sim_fpu_64to (&A, a);
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sim_fpu_64to (&B, b);
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#if 0
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sim_fpu_print_fpu (&A, (sim_fpu_print_func*) fprintf, stdout);
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fprintf (stdout, " * ");
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sim_fpu_print_fpu (&B, (sim_fpu_print_func*) fprintf, stdout);
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fprintf (stdout, " = ");
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#endif
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flags |= sim_fpu_mul (&ans, &A, &B);
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#if 0
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sim_fpu_print_fpu (&ans, (sim_fpu_print_func*) fprintf, stdout);
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#endif
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flags |= sim_fpu_round_64 (&ans, rounding_mode, 0);
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#if 0
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sim_fpu_print_status (flags, (sim_fpu_print_func*) fprintf, stdout);
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fprintf (stdout, "\n");
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#endif
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sim_fpu_to64 (&z, &ans);
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return z;
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}
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float64 syst_float64_div( float64 a, float64 b )
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{
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float64 z;
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sim_fpu A;
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sim_fpu B;
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sim_fpu ans;
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sim_fpu_64to (&A, a);
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sim_fpu_64to (&B, b);
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#if 0
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sim_fpu_print_fpu (&A, (sim_fpu_print_func*) fprintf, stdout);
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fprintf (stdout, " + ");
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sim_fpu_print_fpu (&B, (sim_fpu_print_func*) fprintf, stdout);
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fprintf (stdout, " = ");
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#endif
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flags |= sim_fpu_div (&ans, &A, &B);
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#if 0
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sim_fpu_print_fpu (&ans, (sim_fpu_print_func*) fprintf, stdout);
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#endif
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flags |= sim_fpu_round_64 (&ans, rounding_mode, 0);
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#if 0
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sim_fpu_print_status (flags, (sim_fpu_print_func*) fprintf, stdout);
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fprintf (stdout, "\n");
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#endif
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sim_fpu_to64 (&z, &ans);
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return z;
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}
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float64 syst_float64_sqrt( float64 a )
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{
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float64 z;
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sim_fpu A;
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sim_fpu ans;
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sim_fpu_64to (&A, a);
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#if 0
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sim_fpu_print_fpu (&A, (sim_fpu_print_func*) fprintf, stdout);
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printf (" sqrt> ");
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printf ("\n");
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#endif
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flags |= sim_fpu_sqrt (&ans, &A);
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#if 0
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sim_fpu_print_fpu (&ans, (sim_fpu_print_func*) fprintf, stdout);
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#endif
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flags |= sim_fpu_round_64 (&ans, rounding_mode, 0);
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#if 0
|
||||
sim_fpu_print_status (flags, (sim_fpu_print_func*) fprintf, stdout);
|
||||
fprintf (stdout, "\n");
|
||||
#endif
|
||||
sim_fpu_to64 (&z, &ans);
|
||||
return z;
|
||||
}
|
||||
|
||||
flag syst_float64_eq( float64 a, float64 b )
|
||||
{
|
||||
sim_fpu A;
|
||||
sim_fpu B;
|
||||
int is;
|
||||
sim_fpu_64to (&A, a);
|
||||
sim_fpu_64to (&B, b);
|
||||
flags |= (sim_fpu_eq (&is, &A, &B) & ~sim_fpu_status_invalid_qnan);
|
||||
return is;
|
||||
}
|
||||
|
||||
flag syst_float64_eq_signaling( float64 a, float64 b )
|
||||
{
|
||||
sim_fpu A;
|
||||
sim_fpu B;
|
||||
int is;
|
||||
sim_fpu_64to (&A, a);
|
||||
sim_fpu_64to (&B, b);
|
||||
flags |= sim_fpu_eq (&is, &A, &B);
|
||||
return is;
|
||||
}
|
||||
|
||||
flag syst_float64_le( float64 a, float64 b )
|
||||
{
|
||||
sim_fpu A;
|
||||
sim_fpu B;
|
||||
int is;
|
||||
sim_fpu_64to (&A, a);
|
||||
sim_fpu_64to (&B, b);
|
||||
flags |= sim_fpu_le (&is, &A, &B);
|
||||
return is;
|
||||
}
|
||||
|
||||
flag syst_float64_le_quiet( float64 a, float64 b )
|
||||
{
|
||||
sim_fpu A;
|
||||
sim_fpu B;
|
||||
int is;
|
||||
sim_fpu_64to (&A, a);
|
||||
sim_fpu_64to (&B, b);
|
||||
flags |= (sim_fpu_le (&is, &A, &B) & ~sim_fpu_status_invalid_qnan);
|
||||
return is;
|
||||
}
|
||||
|
||||
flag syst_float64_lt( float64 a, float64 b )
|
||||
{
|
||||
sim_fpu A;
|
||||
sim_fpu B;
|
||||
int is;
|
||||
sim_fpu_64to (&A, a);
|
||||
sim_fpu_64to (&B, b);
|
||||
flags |= sim_fpu_lt (&is, &A, &B);
|
||||
return is;
|
||||
}
|
||||
|
||||
flag syst_float64_lt_quiet( float64 a, float64 b )
|
||||
{
|
||||
sim_fpu A;
|
||||
sim_fpu B;
|
||||
int is;
|
||||
sim_fpu_64to (&A, a);
|
||||
sim_fpu_64to (&B, b);
|
||||
flags |= (sim_fpu_lt (&is, &A, &B) & ~sim_fpu_status_invalid_qnan);
|
||||
return is;
|
||||
}
|
||||
|
||||
|
|
@ -1,3 +1,12 @@
|
|||
Mon Sep 29 12:49:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
|
||||
|
||||
* insns (get_fp_reg, set_fp_reg): Update to use changed sim_fpu
|
||||
interface.
|
||||
(do_fadd, do_fcmp, do_fdiv, do_fmpy, do_frnd, do_fsub): Ditto.
|
||||
|
||||
* misc.c (tic80_trace_fpu3, tic80_trace_fpu2, tic80_trace_fpu1,
|
||||
tic80_trace_fpu2i) Update to use changed sim_fpu interface.
|
||||
|
||||
Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
|
||||
|
||||
* configure.in (SIM_AC_OPTIONS_BITSIZE): Define.
|
||||
|
|
|
|||
|
|
@ -434,10 +434,12 @@ void::function::do_dst:int Source, unsigned32 base, unsigned32 *rBase, int m , i
|
|||
|
||||
|
||||
sim_fpu::function::get_fp_reg:int reg, unsigned32 val, int precision
|
||||
sim_fpu ans;
|
||||
switch (precision)
|
||||
{
|
||||
case 0: /* single */
|
||||
return sim_fpu_32to (val);
|
||||
sim_fpu_32to (&ans, val);
|
||||
break;
|
||||
case 1: /* double */
|
||||
if (reg < 0)
|
||||
sim_engine_abort (SD, CPU, cia, "DP immediate invalid");
|
||||
|
|
@ -445,43 +447,43 @@ sim_fpu::function::get_fp_reg:int reg, unsigned32 val, int precision
|
|||
sim_engine_abort (SD, CPU, cia, "DP FP register must be even");
|
||||
if (reg <= 1)
|
||||
sim_engine_abort (SD, CPU, cia, "DP FP register must be >= 2");
|
||||
return sim_fpu_64to (INSERTED64 (GPR (reg + 1), 63, 32)
|
||||
| INSERTED64 (GPR (reg), 31, 0));
|
||||
sim_fpu_232to (&ans, GPR (reg), GPR (reg + 1));
|
||||
break;
|
||||
case 2: /* 32 bit signed integer */
|
||||
return sim_fpu_i32to (val);
|
||||
sim_fpu_i32to (&ans, val, 0);
|
||||
break;
|
||||
case 3: /* 32 bit unsigned integer */
|
||||
return sim_fpu_u32to (val);
|
||||
sim_fpu_u32to (&ans, val, 0);
|
||||
break;
|
||||
default:
|
||||
sim_engine_abort (SD, CPU, cia, "Unsupported FP precision");
|
||||
}
|
||||
return sim_fpu_i32to (0);
|
||||
return ans;
|
||||
void::function::set_fp_reg:int Dest, sim_fpu val, int PD
|
||||
switch (PD)
|
||||
{
|
||||
case 0: /* single */
|
||||
{
|
||||
GPR (Dest) = sim_fpu_to32 (val);
|
||||
sim_fpu_to32 (&GPR (Dest), &val);
|
||||
break;
|
||||
}
|
||||
case 1: /* double */
|
||||
{
|
||||
unsigned64 v = sim_fpu_to64 (val);
|
||||
if (Dest & 1)
|
||||
sim_engine_abort (SD, CPU, cia, "DP FP Dest register must be even");
|
||||
if (Dest <= 1)
|
||||
sim_engine_abort (SD, CPU, cia, "DP FP Dest register must be >= 2");
|
||||
GPR (Dest + 0) = VL4_8 (v);
|
||||
GPR (Dest + 1) = VH4_8 (v);
|
||||
sim_fpu_to232 (&GPR (Dest + 0), &GPR (Dest + 1), &val);
|
||||
break;
|
||||
}
|
||||
case 2: /* signed */
|
||||
{
|
||||
GPR (Dest) = sim_fpu_to32i (val);
|
||||
sim_fpu_to32i (&GPR (Dest), &val, 0);
|
||||
break;
|
||||
}
|
||||
case 3: /* unsigned */
|
||||
{
|
||||
GPR (Dest) = sim_fpu_to32u (val);
|
||||
sim_fpu_to32u (&GPR (Dest), &val, 0);
|
||||
break;
|
||||
}
|
||||
default:
|
||||
|
|
@ -490,7 +492,8 @@ void::function::set_fp_reg:int Dest, sim_fpu val, int PD
|
|||
|
||||
// fadd.{s|d}{s|d}{s|d}
|
||||
void::function::do_fadd:int Dest, int PD, sim_fpu s1, sim_fpu s2
|
||||
sim_fpu ans = sim_fpu_add (s1, s2);
|
||||
sim_fpu ans;
|
||||
sim_fpu_add (&ans, &s1, &s2);
|
||||
TRACE_FPU3 (ans, s1, s2);
|
||||
set_fp_reg (_SD, Dest, ans, PD);
|
||||
const char *::function::str_PX:int PX
|
||||
|
|
@ -517,25 +520,25 @@ const char *::function::str_PX:int PX
|
|||
// fcmp.{s|d}{s|d}{s|d}
|
||||
void::function::do_fcmp:unsigned32 *rDest, sim_fpu s1, sim_fpu s2
|
||||
unsigned32 result = 0;
|
||||
if (sim_fpu_is_nan (s1) || sim_fpu_is_nan (s2))
|
||||
if (sim_fpu_is_nan (&s1) || sim_fpu_is_nan (&s2))
|
||||
result |= BIT32 (30);
|
||||
else
|
||||
{
|
||||
result |= BIT32 (31);
|
||||
if (sim_fpu_is_eq (s1, s2)) result |= BIT32(20);
|
||||
if (sim_fpu_is_ne (s1, s2)) result |= BIT32(21);
|
||||
if (sim_fpu_is_gt (s1, s2)) result |= BIT32(22);
|
||||
if (sim_fpu_is_le (s1, s2)) result |= BIT32(23);
|
||||
if (sim_fpu_is_lt (s1, s2)) result |= BIT32(24);
|
||||
if (sim_fpu_is_ge (s1, s2)) result |= BIT32(25);
|
||||
if (sim_fpu_is_lt (s1, sim_fpu_i32to (0))
|
||||
|| sim_fpu_is_gt (s1, s2)) result |= BIT32(26);
|
||||
if (sim_fpu_is_lt (sim_fpu_i32to (0), s1)
|
||||
&& sim_fpu_is_lt (s1, s2)) result |= BIT32(27);
|
||||
if (sim_fpu_is_le (sim_fpu_i32to (0), s1)
|
||||
&& sim_fpu_is_le (s1, s2)) result |= BIT32(28);
|
||||
if (sim_fpu_is_le (s1, sim_fpu_i32to (0))
|
||||
|| sim_fpu_is_ge (s1, s2)) result |= BIT32(29);
|
||||
if (sim_fpu_is_eq (&s1, &s2)) result |= BIT32(20);
|
||||
if (sim_fpu_is_ne (&s1, &s2)) result |= BIT32(21);
|
||||
if (sim_fpu_is_gt (&s1, &s2)) result |= BIT32(22);
|
||||
if (sim_fpu_is_le (&s1, &s2)) result |= BIT32(23);
|
||||
if (sim_fpu_is_lt (&s1, &s2)) result |= BIT32(24);
|
||||
if (sim_fpu_is_ge (&s1, &s2)) result |= BIT32(25);
|
||||
if (sim_fpu_is_lt (&s1, &sim_fpu_zero)
|
||||
|| sim_fpu_is_gt (&s1, &s2)) result |= BIT32(26);
|
||||
if (sim_fpu_is_lt (&sim_fpu_zero, &s1)
|
||||
&& sim_fpu_is_lt (&s1, &s2)) result |= BIT32(27);
|
||||
if (sim_fpu_is_le (&sim_fpu_zero, &s1)
|
||||
&& sim_fpu_is_le (&s1, &s2)) result |= BIT32(28);
|
||||
if (sim_fpu_is_le (&s1, &sim_fpu_zero)
|
||||
|| sim_fpu_is_ge (&s1, &s2)) result |= BIT32(29);
|
||||
}
|
||||
*rDest = result;
|
||||
TRACE_FPU2I (result, s1, s2);
|
||||
|
|
@ -554,7 +557,8 @@ void::function::do_fcmp:unsigned32 *rDest, sim_fpu s1, sim_fpu s2
|
|||
|
||||
// fdiv.{s|d}{s|d}{s|d}
|
||||
void::function::do_fdiv:int Dest, int PD, sim_fpu s1, sim_fpu s2
|
||||
sim_fpu ans = sim_fpu_div (s1, s2);
|
||||
sim_fpu ans;
|
||||
sim_fpu_div (&ans, &s1, &s2);
|
||||
TRACE_FPU3 (ans, s1, s2);
|
||||
set_fp_reg (_SD, Dest, ans, PD);
|
||||
31.Dest,26.Source2,21.0b111110011,12.0,11./,10.PD,8.P2,6.P1,4.Source1::f::fdiv r
|
||||
|
|
@ -575,19 +579,28 @@ void::function::do_fmpy:int Dest, int PD, sim_fpu s1, sim_fpu s2
|
|||
{
|
||||
case 2: /* signed */
|
||||
{
|
||||
GPR (Dest) = sim_fpu_to64i (s1) * sim_fpu_to64i (s2);
|
||||
signed64 i1;
|
||||
signed64 i2;
|
||||
sim_fpu_to64i (&i1, &s1, 0);
|
||||
sim_fpu_to64i (&i2, &s2, 0);
|
||||
GPR (Dest) = i1 * i2;
|
||||
TRACE_FPU2I (GPR (Dest), s1, s2);
|
||||
break;
|
||||
}
|
||||
case 3: /* unsigned */
|
||||
{
|
||||
GPR (Dest) = sim_fpu_to64u (s1) * sim_fpu_to64u (s2);
|
||||
unsigned64 u1;
|
||||
unsigned64 u2;
|
||||
sim_fpu_to64u (&u1, &s1, 0);
|
||||
sim_fpu_to64u (&u2, &s2, 0);
|
||||
GPR (Dest) = u1 * u2;
|
||||
TRACE_FPU2I (GPR (Dest), s1, s2);
|
||||
break;
|
||||
}
|
||||
default:
|
||||
{
|
||||
sim_fpu ans = sim_fpu_mul (s1, s2);
|
||||
sim_fpu ans;
|
||||
sim_fpu_mul (&ans, &s1, &s2);
|
||||
set_fp_reg (_SD, Dest, ans, PD);
|
||||
TRACE_FPU3 (ans, s1, s2);
|
||||
}
|
||||
|
|
@ -664,7 +677,8 @@ void::function::do_frnd:int Dest, int PD, sim_fpu s1
|
|||
|
||||
// fsub.{s|d}{s|d}{s|d}
|
||||
void::function::do_fsub:int Dest, int PD, sim_fpu s1, sim_fpu s2
|
||||
sim_fpu ans = sim_fpu_sub (s1, s2);
|
||||
sim_fpu ans;
|
||||
sim_fpu_sub (&ans, &s1, &s2);
|
||||
TRACE_FPU3 (ans, s1, s2);
|
||||
set_fp_reg (_SD, Dest, ans, PD);
|
||||
31.Dest,26.Source2,21.0b111110001,12.0,11.r,10.PD,8.P2,6.P1,4.Source1::f::fsub r
|
||||
|
|
|
|||
|
|
@ -241,9 +241,9 @@ tic80_trace_fpu3 (SIM_DESC sd,
|
|||
itable[indx].file, itable[indx].line_nr, "fpu",
|
||||
"%-*s %*g %*g => %*g",
|
||||
tic80_size_name, itable[indx].name,
|
||||
SIZE_HEX + SIZE_DECIMAL + 3, sim_fpu_2d (input1),
|
||||
SIZE_HEX + SIZE_DECIMAL + 3, sim_fpu_2d (input2),
|
||||
SIZE_HEX + SIZE_DECIMAL + 3, sim_fpu_2d (result));
|
||||
SIZE_HEX + SIZE_DECIMAL + 3, sim_fpu_2d (&input1),
|
||||
SIZE_HEX + SIZE_DECIMAL + 3, sim_fpu_2d (&input2),
|
||||
SIZE_HEX + SIZE_DECIMAL + 3, sim_fpu_2d (&result));
|
||||
}
|
||||
|
||||
/* Trace the result of an FPU operation with 1 floating point input and a floating point output */
|
||||
|
|
@ -262,9 +262,9 @@ tic80_trace_fpu2 (SIM_DESC sd,
|
|||
itable[indx].file, itable[indx].line_nr, "fpu",
|
||||
"%-*s %*g %-*s => %*g",
|
||||
tic80_size_name, itable[indx].name,
|
||||
SIZE_HEX + SIZE_DECIMAL + 3, sim_fpu_2d (input),
|
||||
SIZE_HEX + SIZE_DECIMAL + 3, sim_fpu_2d (&input),
|
||||
SIZE_HEX + SIZE_DECIMAL + 3, "",
|
||||
SIZE_HEX + SIZE_DECIMAL, sim_fpu_2d (result));
|
||||
SIZE_HEX + SIZE_DECIMAL, sim_fpu_2d (&result));
|
||||
}
|
||||
|
||||
/* Trace the result of an FPU operation with 1 floating point input and a floating point output */
|
||||
|
|
@ -284,7 +284,7 @@ tic80_trace_fpu1 (SIM_DESC sd,
|
|||
tic80_size_name, itable[indx].name,
|
||||
SIZE_HEX + SIZE_DECIMAL + 3, "",
|
||||
SIZE_HEX + SIZE_DECIMAL + 3, "",
|
||||
SIZE_HEX + SIZE_DECIMAL, sim_fpu_2d (result));
|
||||
SIZE_HEX + SIZE_DECIMAL, sim_fpu_2d (&result));
|
||||
}
|
||||
|
||||
/* Trace the result of an FPU operation with 1 integer input and an integer output */
|
||||
|
|
@ -304,8 +304,8 @@ tic80_trace_fpu2i (SIM_DESC sd,
|
|||
itable[indx].file, itable[indx].line_nr, "fpu",
|
||||
"%-*s %*f %*f => 0x%.*lx %-*ld",
|
||||
tic80_size_name, itable[indx].name,
|
||||
SIZE_HEX + SIZE_DECIMAL + 3, sim_fpu_2d (input1),
|
||||
SIZE_HEX + SIZE_DECIMAL + 3, sim_fpu_2d (input2),
|
||||
SIZE_HEX + SIZE_DECIMAL + 3, sim_fpu_2d (&input1),
|
||||
SIZE_HEX + SIZE_DECIMAL + 3, sim_fpu_2d (&input2),
|
||||
SIZE_HEX, result, SIZE_DECIMAL, (long)(signed32)result);
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue