gas/
2005-06-20 H.J. Lu <hongjiu.lu@intel.com> PR 1013 * config/tc-i386.c (md_assemble): Don't call optimize_disp on movabs. (optimize_disp): Optimize only if possible. Don't use 64bit displacement on non-constants and do same on constants if possible. gas/testsuite/ 2005-06-20 H.J. Lu <hongjiu.lu@intel.com> PR 1013 * i386/x86_64.s: Add absolute 64bit addressing tests for mov. * i386/x86_64.s: Updated. include/opcode/ 2005-06-20 H.J. Lu <hongjiu.lu@intel.com> PR 1013 * i386.h (i386_optab): Update comments for 64bit addressing on mov. Allow 64bit addressing for mov and movq.
This commit is contained in:
H.J. Lu
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973a3492d5
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b300c311a0
7 changed files with 113 additions and 38 deletions
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@ -1,3 +1,12 @@
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2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
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PR 1013
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* config/tc-i386.c (md_assemble): Don't call optimize_disp on
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movabs.
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(optimize_disp): Optimize only if possible. Don't use 64bit
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displacement on non-constants and do same on constants if
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possible.
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2005-06-17 Jan Beulich <jbeulich@novell.com>
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* config/tc-i386.c (reloc): Also handle BFD_RELOC_64_PCREL.
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@ -1409,7 +1409,11 @@ md_assemble (line)
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if (i.imm_operands)
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optimize_imm ();
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if (i.disp_operands)
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/* Don't optimize displacement for movabs since it only takes 64bit
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displacement. */
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if (i.disp_operands
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&& (flag_code != CODE_64BIT
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|| strcmp (mnemonic, "movabs") != 0))
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optimize_disp ();
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/* Next, we find a template that matches the given insn,
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@ -2065,43 +2069,51 @@ optimize_disp ()
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int op;
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for (op = i.operands; --op >= 0;)
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if ((i.types[op] & Disp) && i.op[op].disps->X_op == O_constant)
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if (i.types[op] & Disp)
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{
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offsetT disp = i.op[op].disps->X_add_number;
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if (i.op[op].disps->X_op == O_constant)
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{
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offsetT disp = i.op[op].disps->X_add_number;
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if (i.types[op] & Disp16)
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{
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/* We know this operand is at most 16 bits, so
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convert to a signed 16 bit number before trying
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to see whether it will fit in an even smaller
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size. */
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disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
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if ((i.types[op] & Disp16)
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&& (disp & ~(offsetT) 0xffff) == 0)
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{
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/* If this operand is at most 16 bits, convert
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to a signed 16 bit number and don't use 64bit
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displacement. */
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disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
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i.types[op] &= ~Disp64;
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}
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if ((i.types[op] & Disp32)
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&& (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
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{
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/* If this operand is at most 32 bits, convert
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to a signed 32 bit number and don't use 64bit
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displacement. */
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disp &= (((offsetT) 2 << 31) - 1);
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disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
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i.types[op] &= ~Disp64;
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}
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if (!disp && (i.types[op] & BaseIndex))
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{
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i.types[op] &= ~Disp;
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i.op[op].disps = 0;
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i.disp_operands--;
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}
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else if (flag_code == CODE_64BIT)
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{
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if (fits_in_signed_long (disp))
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i.types[op] |= Disp32S;
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if (fits_in_unsigned_long (disp))
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i.types[op] |= Disp32;
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}
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if ((i.types[op] & (Disp32 | Disp32S | Disp16))
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&& fits_in_signed_byte (disp))
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i.types[op] |= Disp8;
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}
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else if (i.types[op] & Disp32)
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{
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/* We know this operand is at most 32 bits, so convert to a
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signed 32 bit number before trying to see whether it will
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fit in an even smaller size. */
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disp &= (((offsetT) 2 << 31) - 1);
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disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
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}
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if (!disp && (i.types[op] & BaseIndex))
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{
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i.types[op] &= ~Disp;
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i.op[op].disps = 0;
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i.disp_operands--;
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}
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else if (flag_code == CODE_64BIT)
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{
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if (fits_in_signed_long (disp))
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i.types[op] |= Disp32S;
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if (fits_in_unsigned_long (disp))
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i.types[op] |= Disp32;
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}
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if ((i.types[op] & (Disp32 | Disp32S | Disp16))
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&& fits_in_signed_byte (disp))
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i.types[op] |= Disp8;
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else
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/* We only support 64bit displacement on constants. */
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i.types[op] &= ~Disp64;
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}
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}
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@ -1,3 +1,9 @@
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2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
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PR 1013
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* i386/x86_64.s: Add absolute 64bit addressing tests for mov.
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* i386/x86_64.s: Updated.
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2005-06-17 Jan Beulich <jbeulich@novell.com>
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* gas/i386/x86-64-pcrel.s: Add insn requiring 64-bit pc-relative
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@ -122,4 +122,22 @@ Disassembly of section .text:
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1f0: 8b 04 25 00 00 00 00 mov[ ]+0x0,%eax
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1f7: 8b 80 00 00 00 00[ ]+mov[ ]+0x0\(%rax\),%eax
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1fd: 8b 05 00 00 00 00[ ]+mov[ ]+0\(%rip\),%eax.*
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0+203 <foo>:
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203: a0 11 22 33 44 55 66 77 88 mov[ ]+0x8877665544332211,%al
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20c: 66 a1 11 22 33 44 55 66 77 88 mov[ ]+0x8877665544332211,%ax
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216: a1 11 22 33 44 55 66 77 88 mov[ ]+0x8877665544332211,%eax
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21f: 48 a1 11 22 33 44 55 66 77 88 mov[ ]+0x8877665544332211,%rax
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229: a2 11 22 33 44 55 66 77 88 mov[ ]+%al,0x8877665544332211
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232: 66 a3 11 22 33 44 55 66 77 88 mov[ ]+%ax,0x8877665544332211
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23c: a3 11 22 33 44 55 66 77 88 mov[ ]+%eax,0x8877665544332211
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245: 48 a3 11 22 33 44 55 66 77 88 mov[ ]+%rax,0x8877665544332211
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24f: a0 11 22 33 44 55 66 77 88 mov[ ]+0x8877665544332211,%al
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258: 66 a1 11 22 33 44 55 66 77 88 mov[ ]+0x8877665544332211,%ax
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262: a1 11 22 33 44 55 66 77 88 mov[ ]+0x8877665544332211,%eax
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26b: 48 a1 11 22 33 44 55 66 77 88 mov[ ]+0x8877665544332211,%rax
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275: a2 11 22 33 44 55 66 77 88 mov[ ]+%al,0x8877665544332211
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27e: 66 a3 11 22 33 44 55 66 77 88 mov[ ]+%ax,0x8877665544332211
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288: a3 11 22 33 44 55 66 77 88 mov[ ]+%eax,0x8877665544332211
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291: 48 a3 11 22 33 44 55 66 77 88 mov[ ]+%rax,0x8877665544332211
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#pass
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@ -150,5 +150,25 @@ mov eax, [rax+symbol]
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#RIP relative
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mov eax, [rip+symbol]
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foo:
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.att_syntax
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#absolute 64bit addressing
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mov 0x8877665544332211,%al
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mov 0x8877665544332211,%ax
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mov 0x8877665544332211,%eax
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mov 0x8877665544332211,%rax
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mov %al,0x8877665544332211
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mov %ax,0x8877665544332211
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mov %eax,0x8877665544332211
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mov %rax,0x8877665544332211
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movb 0x8877665544332211,%al
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movw 0x8877665544332211,%ax
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movl 0x8877665544332211,%eax
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movq 0x8877665544332211,%rax
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movb %al,0x8877665544332211
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movw %ax,0x8877665544332211
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movl %eax,0x8877665544332211
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movq %rax,0x8877665544332211
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# Get a good alignment.
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.p2align 4,0
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@ -1,3 +1,9 @@
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2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
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PR 1013
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* i386.h (i386_optab): Update comments for 64bit addressing on
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mov. Allow 64bit addressing for mov and movq.
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2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
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* hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
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@ -83,12 +83,13 @@ static const template i386_optab[] =
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/* Move instructions. */
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#define MOV_AX_DISP32 0xa0
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/* In the 64bit mode the short form mov immediate is redefined to have
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64bit displacement value. */
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/* We put the 64bit displacement first and we only mark constants
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larger than 32bit as Disp64. */
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{ "mov", 2, 0xa0, X, Cpu64, bwlq_Suf|D|W, { Disp64, Acc, 0 } },
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{ "mov", 2, 0xa0, X, CpuNo64,bwl_Suf|D|W, { Disp16|Disp32, Acc, 0 } },
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{ "mov", 2, 0x88, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} },
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/* In the 64bit mode the short form mov immediate is redefined to have
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64bit displacement value. */
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64bit value. */
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{ "mov", 2, 0xb0, X, 0, bwl_Suf|W|ShortForm, { EncImm, Reg8|Reg16|Reg32, 0 } },
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{ "mov", 2, 0xc6, 0, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0 } },
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{ "mov", 2, 0xb0, X, Cpu64, q_Suf|W|ShortForm, { Imm64, Reg64, 0 } },
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@ -1004,6 +1005,9 @@ static const template i386_optab[] =
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{"movq", 2, 0x0f7f, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX, RegMMX|LongMem, 0 } },
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{"movq", 2, 0xf30f7e,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
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{"movq", 2, 0x660fd6,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM, RegXMM|LLongMem, 0 } },
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/* We put the 64bit displacement first and we only mark constants
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larger than 32bit as Disp64. */
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{"movq", 2, 0xa0, X, Cpu64, NoSuf|D|W|Size64, { Disp64, Acc, 0 } },
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{"movq", 2, 0x88, X, Cpu64, NoSuf|D|W|Modrm|Size64,{ Reg64, Reg64|AnyMem, 0 } },
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{"movq", 2, 0xc6, 0, Cpu64, NoSuf|W|Modrm|Size64, { Imm32S, Reg64|WordMem, 0 } },
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{"movq", 2, 0xb0, X, Cpu64, NoSuf|W|ShortForm|Size64,{ Imm64, Reg64, 0 } },
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