[ bfd/ChangeLog ]
2001-10-31 Chris Demetriou <cgd@demetriou.com> * elf32-mips.c (_bfd_mips_elf_hi16_reloc): Handle PC-relative relocations properly. [ gas/ChangeLog ] 2001-10-31 Chris Demetriou <cgd@broadcom.com> * config/tc-mips.c (HAVE_32BIT_ADDRESSES): If compiling embedded PIC code, assume pointers the same size as GPRs. (macro): In M_LA_AB handling for embedded PIC code, support "la $treg,foo-bar($breg)". In load/store handling (label ld_st) support "<op> $treg,<sym>-<local_sym>($breg)" which is used by the compiler for switch statements. In load/store double multi-instruction macro handling (label ldd_std) add a comment that no special handling is currently done for embedded PIC. (mips_ip): In 'o' (16-bit offset) case, only accept 16 bit offsets. [ gas/testsuite/ChangeLog ] 2001-10-31 Chris Demetriou <cgd@broadcom.com> * gas/mips/empic.s: Undo damage inflicted on 2000-12-02. * gas/mips/empic.d: Likewise. * gas/mips/elempic.d: Likewise (it was copied into other files). * gas/mips/telempic.d: Likewise. * gas/mips/tempic.d: Likewise. * gas/mips/empic2.s: New test to check new 'la' and 'lw' (and related ops) syntax, test loads with large offsets. * gas/mips/emcic2.d: Likewise. * gas/mips/mips.exp: Run the new test on ELF platforms.
This commit is contained in:
Chris Demetriou
parent
d45fc520b1
commit
afdbd6d03b
13 changed files with 538 additions and 57 deletions
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@ -1,3 +1,8 @@
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2001-10-31 Chris Demetriou <cgd@demetriou.com>
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* elf32-mips.c (_bfd_mips_elf_hi16_reloc): Handle PC-relative
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relocations properly.
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2001-10-31 H.J. Lu <hjl@gnu.org>
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* elflink.h (elf_link_output_extsym): Don't clear the visibility
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@ -1190,6 +1190,8 @@ _bfd_mips_elf_hi16_reloc (abfd,
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relocation += symbol->section->output_section->vma;
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relocation += symbol->section->output_offset;
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relocation += reloc_entry->addend;
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if (reloc_entry->howto->pc_relative)
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relocation -= reloc_entry->address;
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if (reloc_entry->address > input_section->_cooked_size)
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return bfd_reloc_outofrange;
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@ -1,3 +1,17 @@
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2001-10-31 Chris Demetriou <cgd@broadcom.com>
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* config/tc-mips.c (HAVE_32BIT_ADDRESSES): If compiling embedded
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PIC code, assume pointers the same size as GPRs.
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(macro): In M_LA_AB handling for embedded PIC code, support
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"la $treg,foo-bar($breg)". In load/store handling
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(label ld_st) support "<op> $treg,<sym>-<local_sym>($breg)"
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which is used by the compiler for switch statements.
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In load/store double multi-instruction macro handling
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(label ldd_std) add a comment that no special handling
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is currently done for embedded PIC.
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(mips_ip): In 'o' (16-bit offset) case, only accept 16
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bit offsets.
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2001-10-31 Richard Earnshaw <rearnsha@arm.com>
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General cleanup of feature definitions.
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@ -246,10 +246,11 @@ static int mips_fp32 = 0;
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/* We can only have 64bit addresses if the object file format
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supports it. */
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#define HAVE_32BIT_ADDRESSES \
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(HAVE_32BIT_GPRS \
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|| bfd_arch_bits_per_address (stdoutput) == 32 \
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|| ! HAVE_64BIT_OBJECTS)
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#define HAVE_32BIT_ADDRESSES \
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(HAVE_32BIT_GPRS \
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|| ((bfd_arch_bits_per_address (stdoutput) == 32 \
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|| ! HAVE_64BIT_OBJECTS) \
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&& mips_pic != EMBEDDED_PIC))
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#define HAVE_64BIT_ADDRESSES (! HAVE_32BIT_ADDRESSES)
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@ -4447,9 +4448,21 @@ macro (ip)
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/* Load the address of a symbol into a register. If breg is not
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zero, we then add a base register to it. */
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if (treg == breg)
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{
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tempreg = AT;
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used_at = 1;
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}
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else
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{
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tempreg = treg;
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used_at = 0;
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}
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/* When generating embedded PIC code, we permit expressions of
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the form
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la $4,foo-bar
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la $treg,foo-bar
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la $treg,foo-bar($breg)
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where bar is an address in the current section. These are used
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when getting the addresses of functions. We don't permit
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X_add_number to be non-zero, because if the symbol is
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@ -4464,16 +4477,30 @@ macro (ip)
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(symbol_get_value_expression (offset_expr.X_op_symbol)
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->X_add_symbol)
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== now_seg)))
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&& breg == 0
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&& (offset_expr.X_add_number == 0
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|| OUTPUT_FLAVOR == bfd_target_elf_flavour))
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{
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macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
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treg, (int) BFD_RELOC_PCREL_HI16_S);
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if (breg == 0)
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{
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tempreg = treg;
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used_at = 0;
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macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
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tempreg, (int) BFD_RELOC_PCREL_HI16_S);
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}
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else
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{
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macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
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tempreg, (int) BFD_RELOC_PCREL_HI16_S);
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macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
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HAVE_32BIT_ADDRESSES ? "addu" : "daddu",
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"d,v,t", tempreg, tempreg, breg);
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}
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macro_build ((char *) NULL, &icnt, &offset_expr,
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HAVE_32BIT_ADDRESSES ? "addiu" : "daddiu",
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"t,r,j", treg, treg, (int) BFD_RELOC_PCREL_LO16);
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return;
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"t,r,j", treg, tempreg, (int) BFD_RELOC_PCREL_LO16);
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if (! used_at)
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return;
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break;
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}
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if (offset_expr.X_op != O_symbol
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@ -4483,17 +4510,6 @@ macro (ip)
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offset_expr.X_op = O_constant;
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}
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if (treg == breg)
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{
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tempreg = AT;
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used_at = 1;
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}
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else
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{
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tempreg = treg;
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used_at = 0;
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}
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if (offset_expr.X_op == O_constant)
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load_register (&icnt, tempreg, &offset_expr, dbl);
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else if (mips_pic == NO_PIC)
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@ -5289,6 +5305,46 @@ macro (ip)
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else
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fmt = "t,o(b)";
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/* For embedded PIC, we allow loads where the offset is calculated
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by subtracting a symbol in the current segment from an unknown
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symbol, relative to a base register, e.g.:
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<op> $treg, <sym>-<localsym>($breg)
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This is used by the compiler for switch statements. */
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if (mips_pic == EMBEDDED_PIC
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&& offset_expr.X_op == O_subtract
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&& (symbol_constant_p (offset_expr.X_op_symbol)
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? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg
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: (symbol_equated_p (offset_expr.X_op_symbol)
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&& (S_GET_SEGMENT
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(symbol_get_value_expression (offset_expr.X_op_symbol)
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->X_add_symbol)
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== now_seg)))
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&& breg != 0
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&& (offset_expr.X_add_number == 0
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|| OUTPUT_FLAVOR == bfd_target_elf_flavour))
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{
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/* For this case, we output the instructions:
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lui $tempreg,<sym> (BFD_RELOC_PCREL_HI16_S)
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addiu $tempreg,$tempreg,$breg
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<op> $treg,<sym>($tempreg) (BFD_RELOC_PCREL_LO16)
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If the relocation would fit entirely in 16 bits, it would be
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nice to emit:
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<op> $treg,<sym>($breg) (BFD_RELOC_PCREL_LO16)
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instead, but that seems quite difficult. */
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macro_build ((char *) NULL, &icnt, &offset_expr, "lui", "t,u",
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tempreg, (int) BFD_RELOC_PCREL_HI16_S);
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macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
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((bfd_arch_bits_per_address (stdoutput) == 32
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|| ! ISA_HAS_64BIT_REGS (mips_opts.isa))
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? "addu" : "daddu"),
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"d,v,t", tempreg, tempreg, breg);
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macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt, treg,
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(int) BFD_RELOC_PCREL_LO16, tempreg);
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if (! used_at)
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return;
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break;
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}
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if (offset_expr.X_op != O_constant
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&& offset_expr.X_op != O_symbol)
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{
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@ -5893,6 +5949,11 @@ macro (ip)
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fmt = "t,o(b)";
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ldd_std:
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/* We do _not_ bother to allow embedded PIC (symbol-local_symbol)
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loads for the case of doing a pair of loads to simulate an 'ld'.
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This is not currently done by the compiler, and assembly coders
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writing embedded-pic code can cope. */
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if (offset_expr.X_op != O_symbol
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&& offset_expr.X_op != O_constant)
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{
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@ -8216,23 +8277,11 @@ mips_ip (str, ip)
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/* If this value won't fit into a 16 bit offset, then go
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find a macro that will generate the 32 bit offset
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code pattern. As a special hack, we accept the
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difference of two local symbols as a constant. This
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is required to suppose embedded PIC switches, which
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use an instruction which looks like
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lw $4,$L12-$LS12($4)
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The problem with handling this in a more general
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fashion is that the macro function doesn't expect to
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see anything which can be handled in a single
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constant instruction. */
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code pattern. */
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if (c == S_EX_NONE
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&& (offset_expr.X_op != O_constant
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|| offset_expr.X_add_number >= 0x8000
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|| offset_expr.X_add_number < -0x8000)
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&& (mips_pic != EMBEDDED_PIC
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|| offset_expr.X_op != O_subtract
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|| (S_GET_SEGMENT (offset_expr.X_add_symbol)
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!= S_GET_SEGMENT (offset_expr.X_op_symbol))))
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|| offset_expr.X_add_number < -0x8000))
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break;
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if (c == S_EX_HI)
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@ -1,3 +1,16 @@
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2001-10-31 Chris Demetriou <cgd@broadcom.com>
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* gas/mips/empic.s: Undo damage inflicted on 2000-12-02.
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* gas/mips/empic.d: Likewise.
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* gas/mips/elempic.d: Likewise (it was copied into other files).
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* gas/mips/telempic.d: Likewise.
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* gas/mips/tempic.d: Likewise.
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* gas/mips/empic2.s: New test to check new 'la' and 'lw' (and
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related ops) syntax, test loads with large offsets.
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* gas/mips/emcic2.d: Likewise.
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* gas/mips/mips.exp: Run the new test on ELF platforms.
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2001-10-31 Nick Clifton <nickc@cambridge.redhat.com>
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* gas/mmix/pop-op.l: Update to match latest listing behaviour.
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@ -56,8 +56,12 @@ OFFSET [ ]+ TYPE VALUE
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0+00000b8 R_MIPS_64 \.text
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0+00000cc R_MIPS_GNU_REL16_S2 \.text
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0+00000d0 R_MIPS_GNU_REL16_S2 \.text
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0+00000dc R_MIPS_32 \.text
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0+00000e8 R_MIPS_64 \.text
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0+00000d4 R_MIPS_GNU_REL_HI16 \.text
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0+00000d8 R_MIPS_GNU_REL_LO16 \.text
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0+00000dc R_MIPS_GNU_REL_HI16 \.text
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0+00000e0 R_MIPS_GNU_REL_LO16 \.text
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0+00000e4 R_MIPS_32 \.text
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0+00000f0 R_MIPS_64 \.text
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RELOCATION RECORDS FOR \[\.foo\]:
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@ -123,9 +127,9 @@ Contents of section \.text:
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00a0 0000033c d80063[26]4 0000033c e80063[26]4 .*
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00b0 cc000000 34000000 cc000000 00000000 .*
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00c0 34000000 00000000 00000000 32000010 .*
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00d0 33000010 34000324 3c000324 cc000000 .*
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00e0 34000000 00000000 cc000000 00000000 .*
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00f0 34000000 00000000 00000000 00000000 .*
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00d0 33000010 0000033c 0c0163[26]4 0000033c .*
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00e0 1c0163[26]4 cc000000 34000000 00000000 .*
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00f0 cc000000 00000000 34000000 00000000 .*
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Contents of section \.data:
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Contents of section \.reginfo:
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0000 08000080 00000000 00000000 00000000 .*
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@ -55,8 +55,12 @@ OFFSET [ ]+ TYPE VALUE
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0+00000b8 R_MIPS_64 \.text
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0+00000cc R_MIPS_GNU_REL16_S2 \.text
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0+00000d0 R_MIPS_GNU_REL16_S2 \.text
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0+00000dc R_MIPS_32 \.text
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0+00000e8 R_MIPS_64 \.text
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0+00000d4 R_MIPS_GNU_REL_HI16 \.text
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0+00000d8 R_MIPS_GNU_REL_LO16 \.text
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0+00000dc R_MIPS_GNU_REL_HI16 \.text
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0+00000e0 R_MIPS_GNU_REL_LO16 \.text
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0+00000e4 R_MIPS_32 \.text
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0+00000f0 R_MIPS_64 \.text
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RELOCATION RECORDS FOR \[\.foo\]:
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@ -122,9 +126,9 @@ Contents of section \.text:
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00a0 3c030000 [26]46300d8 3c030000 [26]46300e8 .*
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00b0 000000cc 00000034 00000000 000000cc .*
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00c0 00000000 00000034 00000000 10000032 .*
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00d0 10000033 24030034 2403003c 000000cc .*
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00e0 00000034 00000000 00000000 000000cc .*
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00f0 00000000 00000034 00000000 00000000 .*
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00d0 10000033 3c030000 [26]463010c 3c030000 .*
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00e0 [26]463011c 000000cc 00000034 00000000 .*
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00f0 00000000 000000cc 00000000 00000034 .*
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Contents of section \.data:
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Contents of section \.reginfo:
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0000 80000008 00000000 00000000 00000000 .*
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@ -53,8 +53,10 @@ l5:
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2: # at address 0xCC.
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b 2b # R_MIPS_GNU_REL16_S2 .text 32
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b 2b+4 # R_MIPS_GNU_REL16_S2 .text 33
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la $3,2b-l5 # 34
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la $3,2b+8-l5 # 3C
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la $3,2b-l5 # R_MIPS_GNU_REL_HI16 .text 0
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# R_MIPS_GNU_REL_LO16 .text 10C
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la $3,2b+8-l5 # R_MIPS_GNU_REL_HI16 .text 0
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# R_MIPS_GNU_REL_LO16 .text 11C
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.word 2b # R_MIPS_32 .text CC
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.word 2b-l5 # R_MIPS_PC32 .text 11C or 34
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nop
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279
gas/testsuite/gas/mips/empic2.d
Normal file
279
gas/testsuite/gas/mips/empic2.d
Normal file
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@ -0,0 +1,279 @@
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#objdump: --prefix-addresses -dr --show-raw-insn -mmips:4000
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#name: MIPS empic2
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#as: -membedded-pic -mips3
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# Check assembly of and relocs for -membedded-pic la, lw, ld, sw, sd macros.
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.*: +file format elf.*mips.*
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|
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Disassembly of section .text:
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0+000000 <[^>]*> 00000000 nop
|
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...
|
||||
...
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0+01000c <[^>]*> 3c020000 lui v0,0x0
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[ ]*1000c: R_MIPS_GNU_REL_HI16 .text
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0+010010 <[^>]*> 0044102d daddu v0,v0,a0
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0+010014 <[^>]*> 6442000c daddiu v0,v0,12
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[ ]*10014: R_MIPS_GNU_REL_LO16 .text
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0+010018 <[^>]*> 3c020000 lui v0,0x0
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[ ]*10018: R_MIPS_GNU_REL_HI16 g1
|
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0+01001c <[^>]*> 0044102d daddu v0,v0,a0
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0+010020 <[^>]*> 64420014 daddiu v0,v0,20
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[ ]*10020: R_MIPS_GNU_REL_LO16 g1
|
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0+010024 <[^>]*> 3c020001 lui v0,0x1
|
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[ ]*10024: R_MIPS_GNU_REL_HI16 .text
|
||||
0+010028 <[^>]*> 0044102d daddu v0,v0,a0
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0+01002c <[^>]*> 64428028 daddiu v0,v0,-32728
|
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[ ]*1002c: R_MIPS_GNU_REL_LO16 .text
|
||||
0+010030 <[^>]*> 3c020000 lui v0,0x0
|
||||
[ ]*10030: R_MIPS_GNU_REL_HI16 g2
|
||||
0+010034 <[^>]*> 0044102d daddu v0,v0,a0
|
||||
0+010038 <[^>]*> 6442002c daddiu v0,v0,44
|
||||
[ ]*10038: R_MIPS_GNU_REL_LO16 g2
|
||||
0+01003c <[^>]*> 3c020001 lui v0,0x1
|
||||
[ ]*1003c: R_MIPS_GNU_REL_HI16 .text
|
||||
0+010040 <[^>]*> 0044102d daddu v0,v0,a0
|
||||
0+010044 <[^>]*> 644202ac daddiu v0,v0,684
|
||||
[ ]*10044: R_MIPS_GNU_REL_LO16 .text
|
||||
0+010048 <[^>]*> 3c020000 lui v0,0x0
|
||||
[ ]*10048: R_MIPS_GNU_REL_HI16 gf
|
||||
0+01004c <[^>]*> 0044102d daddu v0,v0,a0
|
||||
0+010050 <[^>]*> 64420044 daddiu v0,v0,68
|
||||
[ ]*10050: R_MIPS_GNU_REL_LO16 gf
|
||||
0+010054 <[^>]*> 3c020000 lui v0,0x0
|
||||
[ ]*10054: R_MIPS_GNU_REL_HI16 e
|
||||
0+010058 <[^>]*> 0044102d daddu v0,v0,a0
|
||||
0+01005c <[^>]*> 64420050 daddiu v0,v0,80
|
||||
[ ]*1005c: R_MIPS_GNU_REL_LO16 e
|
||||
0+010060 <[^>]*> 3c020000 lui v0,0x0
|
||||
[ ]*10060: R_MIPS_GNU_REL_HI16 .text
|
||||
0+010064 <[^>]*> 0044102d daddu v0,v0,a0
|
||||
0+010068 <[^>]*> 64420060 daddiu v0,v0,96
|
||||
[ ]*10068: R_MIPS_GNU_REL_LO16 .text
|
||||
0+01006c <[^>]*> 3c020000 lui v0,0x0
|
||||
[ ]*1006c: R_MIPS_GNU_REL_HI16 g1
|
||||
0+010070 <[^>]*> 0044102d daddu v0,v0,a0
|
||||
0+010074 <[^>]*> 64420068 daddiu v0,v0,104
|
||||
[ ]*10074: R_MIPS_GNU_REL_LO16 g1
|
||||
0+010078 <[^>]*> 3c020001 lui v0,0x1
|
||||
[ ]*10078: R_MIPS_GNU_REL_HI16 .text
|
||||
0+01007c <[^>]*> 0044102d daddu v0,v0,a0
|
||||
0+010080 <[^>]*> 6442807c daddiu v0,v0,-32644
|
||||
[ ]*10080: R_MIPS_GNU_REL_LO16 .text
|
||||
0+010084 <[^>]*> 3c020000 lui v0,0x0
|
||||
[ ]*10084: R_MIPS_GNU_REL_HI16 g2
|
||||
0+010088 <[^>]*> 0044102d daddu v0,v0,a0
|
||||
0+01008c <[^>]*> 64420080 daddiu v0,v0,128
|
||||
[ ]*1008c: R_MIPS_GNU_REL_LO16 g2
|
||||
0+010090 <[^>]*> 3c020001 lui v0,0x1
|
||||
[ ]*10090: R_MIPS_GNU_REL_HI16 .text
|
||||
0+010094 <[^>]*> 0044102d daddu v0,v0,a0
|
||||
0+010098 <[^>]*> 64420300 daddiu v0,v0,768
|
||||
[ ]*10098: R_MIPS_GNU_REL_LO16 .text
|
||||
0+01009c <[^>]*> 3c020000 lui v0,0x0
|
||||
[ ]*1009c: R_MIPS_GNU_REL_HI16 gf
|
||||
0+0100a0 <[^>]*> 0044102d daddu v0,v0,a0
|
||||
0+0100a4 <[^>]*> 64420098 daddiu v0,v0,152
|
||||
[ ]*100a4: R_MIPS_GNU_REL_LO16 gf
|
||||
0+0100a8 <[^>]*> 3c020000 lui v0,0x0
|
||||
[ ]*100a8: R_MIPS_GNU_REL_HI16 e
|
||||
0+0100ac <[^>]*> 0044102d daddu v0,v0,a0
|
||||
0+0100b0 <[^>]*> 644200a4 daddiu v0,v0,164
|
||||
[ ]*100b0: R_MIPS_GNU_REL_LO16 e
|
||||
0+0100b4 <[^>]*> 3c020000 lui v0,0x0
|
||||
[ ]*100b4: R_MIPS_GNU_REL_HI16 .text
|
||||
0+0100b8 <[^>]*> 644200b0 daddiu v0,v0,176
|
||||
[ ]*100b8: R_MIPS_GNU_REL_LO16 .text
|
||||
0+0100bc <[^>]*> 3c020000 lui v0,0x0
|
||||
[ ]*100bc: R_MIPS_GNU_REL_HI16 g1
|
||||
0+0100c0 <[^>]*> 644200b4 daddiu v0,v0,180
|
||||
[ ]*100c0: R_MIPS_GNU_REL_LO16 g1
|
||||
0+0100c4 <[^>]*> 3c020001 lui v0,0x1
|
||||
[ ]*100c4: R_MIPS_GNU_REL_HI16 .text
|
||||
0+0100c8 <[^>]*> 644280c4 daddiu v0,v0,-32572
|
||||
[ ]*100c8: R_MIPS_GNU_REL_LO16 .text
|
||||
0+0100cc <[^>]*> 3c020000 lui v0,0x0
|
||||
[ ]*100cc: R_MIPS_GNU_REL_HI16 g2
|
||||
0+0100d0 <[^>]*> 644200c4 daddiu v0,v0,196
|
||||
[ ]*100d0: R_MIPS_GNU_REL_LO16 g2
|
||||
0+0100d4 <[^>]*> 3c020001 lui v0,0x1
|
||||
[ ]*100d4: R_MIPS_GNU_REL_HI16 .text
|
||||
0+0100d8 <[^>]*> 64420340 daddiu v0,v0,832
|
||||
[ ]*100d8: R_MIPS_GNU_REL_LO16 .text
|
||||
0+0100dc <[^>]*> 3c020000 lui v0,0x0
|
||||
[ ]*100dc: R_MIPS_GNU_REL_HI16 gf
|
||||
0+0100e0 <[^>]*> 644200d4 daddiu v0,v0,212
|
||||
[ ]*100e0: R_MIPS_GNU_REL_LO16 gf
|
||||
0+0100e4 <[^>]*> 3c020000 lui v0,0x0
|
||||
[ ]*100e4: R_MIPS_GNU_REL_HI16 e
|
||||
0+0100e8 <[^>]*> 644200dc daddiu v0,v0,220
|
||||
[ ]*100e8: R_MIPS_GNU_REL_LO16 e
|
||||
0+0100ec <[^>]*> 3c020000 lui v0,0x0
|
||||
[ ]*100ec: R_MIPS_GNU_REL_HI16 .text
|
||||
0+0100f0 <[^>]*> 644200e8 daddiu v0,v0,232
|
||||
[ ]*100f0: R_MIPS_GNU_REL_LO16 .text
|
||||
0+0100f4 <[^>]*> 3c020000 lui v0,0x0
|
||||
[ ]*100f4: R_MIPS_GNU_REL_HI16 g1
|
||||
0+0100f8 <[^>]*> 644200ec daddiu v0,v0,236
|
||||
[ ]*100f8: R_MIPS_GNU_REL_LO16 g1
|
||||
0+0100fc <[^>]*> 3c020001 lui v0,0x1
|
||||
[ ]*100fc: R_MIPS_GNU_REL_HI16 .text
|
||||
0+010100 <[^>]*> 644280fc daddiu v0,v0,-32516
|
||||
[ ]*10100: R_MIPS_GNU_REL_LO16 .text
|
||||
0+010104 <[^>]*> 3c020000 lui v0,0x0
|
||||
[ ]*10104: R_MIPS_GNU_REL_HI16 g2
|
||||
0+010108 <[^>]*> 644200fc daddiu v0,v0,252
|
||||
[ ]*10108: R_MIPS_GNU_REL_LO16 g2
|
||||
0+01010c <[^>]*> 3c020001 lui v0,0x1
|
||||
[ ]*1010c: R_MIPS_GNU_REL_HI16 .text
|
||||
0+010110 <[^>]*> 64420378 daddiu v0,v0,888
|
||||
[ ]*10110: R_MIPS_GNU_REL_LO16 .text
|
||||
0+010114 <[^>]*> 3c020000 lui v0,0x0
|
||||
[ ]*10114: R_MIPS_GNU_REL_HI16 gf
|
||||
0+010118 <[^>]*> 6442010c daddiu v0,v0,268
|
||||
[ ]*10118: R_MIPS_GNU_REL_LO16 gf
|
||||
0+01011c <[^>]*> 3c020000 lui v0,0x0
|
||||
[ ]*1011c: R_MIPS_GNU_REL_HI16 e
|
||||
0+010120 <[^>]*> 64420114 daddiu v0,v0,276
|
||||
[ ]*10120: R_MIPS_GNU_REL_LO16 e
|
||||
0+010124 <[^>]*> 3c020000 lui v0,0x0
|
||||
[ ]*10124: R_MIPS_GNU_REL_HI16 .text
|
||||
0+010128 <[^>]*> 0044102d daddu v0,v0,a0
|
||||
0+01012c <[^>]*> 8c420124 lw v0,292\(v0\)
|
||||
[ ]*1012c: R_MIPS_GNU_REL_LO16 .text
|
||||
0+010130 <[^>]*> 3c020000 lui v0,0x0
|
||||
[ ]*10130: R_MIPS_GNU_REL_HI16 g1
|
||||
0+010134 <[^>]*> 0044102d daddu v0,v0,a0
|
||||
0+010138 <[^>]*> 8c42012c lw v0,300\(v0\)
|
||||
[ ]*10138: R_MIPS_GNU_REL_LO16 g1
|
||||
0+01013c <[^>]*> 3c020001 lui v0,0x1
|
||||
[ ]*1013c: R_MIPS_GNU_REL_HI16 .text
|
||||
0+010140 <[^>]*> 0044102d daddu v0,v0,a0
|
||||
0+010144 <[^>]*> 8c428140 lw v0,-32448\(v0\)
|
||||
[ ]*10144: R_MIPS_GNU_REL_LO16 .text
|
||||
0+010148 <[^>]*> 3c020000 lui v0,0x0
|
||||
[ ]*10148: R_MIPS_GNU_REL_HI16 g2
|
||||
0+01014c <[^>]*> 0044102d daddu v0,v0,a0
|
||||
0+010150 <[^>]*> 8c420144 lw v0,324\(v0\)
|
||||
[ ]*10150: R_MIPS_GNU_REL_LO16 g2
|
||||
0+010154 <[^>]*> 3c020001 lui v0,0x1
|
||||
[ ]*10154: R_MIPS_GNU_REL_HI16 .text
|
||||
0+010158 <[^>]*> 0044102d daddu v0,v0,a0
|
||||
0+01015c <[^>]*> 8c4203c4 lw v0,964\(v0\)
|
||||
[ ]*1015c: R_MIPS_GNU_REL_LO16 .text
|
||||
0+010160 <[^>]*> 3c020000 lui v0,0x0
|
||||
[ ]*10160: R_MIPS_GNU_REL_HI16 gf
|
||||
0+010164 <[^>]*> 0044102d daddu v0,v0,a0
|
||||
0+010168 <[^>]*> 8c42015c lw v0,348\(v0\)
|
||||
[ ]*10168: R_MIPS_GNU_REL_LO16 gf
|
||||
0+01016c <[^>]*> 3c020000 lui v0,0x0
|
||||
[ ]*1016c: R_MIPS_GNU_REL_HI16 e
|
||||
0+010170 <[^>]*> 0044102d daddu v0,v0,a0
|
||||
0+010174 <[^>]*> 8c420168 lw v0,360\(v0\)
|
||||
[ ]*10174: R_MIPS_GNU_REL_LO16 e
|
||||
0+010178 <[^>]*> 3c020000 lui v0,0x0
|
||||
[ ]*10178: R_MIPS_GNU_REL_HI16 .text
|
||||
0+01017c <[^>]*> 0044102d daddu v0,v0,a0
|
||||
0+010180 <[^>]*> dc420178 ld v0,376\(v0\)
|
||||
[ ]*10180: R_MIPS_GNU_REL_LO16 .text
|
||||
0+010184 <[^>]*> 3c020000 lui v0,0x0
|
||||
[ ]*10184: R_MIPS_GNU_REL_HI16 g1
|
||||
0+010188 <[^>]*> 0044102d daddu v0,v0,a0
|
||||
0+01018c <[^>]*> dc420180 ld v0,384\(v0\)
|
||||
[ ]*1018c: R_MIPS_GNU_REL_LO16 g1
|
||||
0+010190 <[^>]*> 3c020001 lui v0,0x1
|
||||
[ ]*10190: R_MIPS_GNU_REL_HI16 .text
|
||||
0+010194 <[^>]*> 0044102d daddu v0,v0,a0
|
||||
0+010198 <[^>]*> dc428194 ld v0,-32364\(v0\)
|
||||
[ ]*10198: R_MIPS_GNU_REL_LO16 .text
|
||||
0+01019c <[^>]*> 3c020000 lui v0,0x0
|
||||
[ ]*1019c: R_MIPS_GNU_REL_HI16 g2
|
||||
0+0101a0 <[^>]*> 0044102d daddu v0,v0,a0
|
||||
0+0101a4 <[^>]*> dc420198 ld v0,408\(v0\)
|
||||
[ ]*101a4: R_MIPS_GNU_REL_LO16 g2
|
||||
0+0101a8 <[^>]*> 3c020001 lui v0,0x1
|
||||
[ ]*101a8: R_MIPS_GNU_REL_HI16 .text
|
||||
0+0101ac <[^>]*> 0044102d daddu v0,v0,a0
|
||||
0+0101b0 <[^>]*> dc420418 ld v0,1048\(v0\)
|
||||
[ ]*101b0: R_MIPS_GNU_REL_LO16 .text
|
||||
0+0101b4 <[^>]*> 3c020000 lui v0,0x0
|
||||
[ ]*101b4: R_MIPS_GNU_REL_HI16 gf
|
||||
0+0101b8 <[^>]*> 0044102d daddu v0,v0,a0
|
||||
0+0101bc <[^>]*> dc4201b0 ld v0,432\(v0\)
|
||||
[ ]*101bc: R_MIPS_GNU_REL_LO16 gf
|
||||
0+0101c0 <[^>]*> 3c020000 lui v0,0x0
|
||||
[ ]*101c0: R_MIPS_GNU_REL_HI16 e
|
||||
0+0101c4 <[^>]*> 0044102d daddu v0,v0,a0
|
||||
0+0101c8 <[^>]*> dc4201bc ld v0,444\(v0\)
|
||||
[ ]*101c8: R_MIPS_GNU_REL_LO16 e
|
||||
0+0101cc <[^>]*> 3c010000 lui at,0x0
|
||||
[ ]*101cc: R_MIPS_GNU_REL_HI16 .text
|
||||
0+0101d0 <[^>]*> 0024082d daddu at,at,a0
|
||||
0+0101d4 <[^>]*> ac2201cc sw v0,460\(at\)
|
||||
[ ]*101d4: R_MIPS_GNU_REL_LO16 .text
|
||||
0+0101d8 <[^>]*> 3c010000 lui at,0x0
|
||||
[ ]*101d8: R_MIPS_GNU_REL_HI16 g1
|
||||
0+0101dc <[^>]*> 0024082d daddu at,at,a0
|
||||
0+0101e0 <[^>]*> ac2201d4 sw v0,468\(at\)
|
||||
[ ]*101e0: R_MIPS_GNU_REL_LO16 g1
|
||||
0+0101e4 <[^>]*> 3c010001 lui at,0x1
|
||||
[ ]*101e4: R_MIPS_GNU_REL_HI16 .text
|
||||
0+0101e8 <[^>]*> 0024082d daddu at,at,a0
|
||||
0+0101ec <[^>]*> ac2281e8 sw v0,-32280\(at\)
|
||||
[ ]*101ec: R_MIPS_GNU_REL_LO16 .text
|
||||
0+0101f0 <[^>]*> 3c010000 lui at,0x0
|
||||
[ ]*101f0: R_MIPS_GNU_REL_HI16 g2
|
||||
0+0101f4 <[^>]*> 0024082d daddu at,at,a0
|
||||
0+0101f8 <[^>]*> ac2201ec sw v0,492\(at\)
|
||||
[ ]*101f8: R_MIPS_GNU_REL_LO16 g2
|
||||
0+0101fc <[^>]*> 3c010001 lui at,0x1
|
||||
[ ]*101fc: R_MIPS_GNU_REL_HI16 .text
|
||||
0+010200 <[^>]*> 0024082d daddu at,at,a0
|
||||
0+010204 <[^>]*> ac22046c sw v0,1132\(at\)
|
||||
[ ]*10204: R_MIPS_GNU_REL_LO16 .text
|
||||
0+010208 <[^>]*> 3c010000 lui at,0x0
|
||||
[ ]*10208: R_MIPS_GNU_REL_HI16 gf
|
||||
0+01020c <[^>]*> 0024082d daddu at,at,a0
|
||||
0+010210 <[^>]*> ac220204 sw v0,516\(at\)
|
||||
[ ]*10210: R_MIPS_GNU_REL_LO16 gf
|
||||
0+010214 <[^>]*> 3c010000 lui at,0x0
|
||||
[ ]*10214: R_MIPS_GNU_REL_HI16 e
|
||||
0+010218 <[^>]*> 0024082d daddu at,at,a0
|
||||
0+01021c <[^>]*> ac220210 sw v0,528\(at\)
|
||||
[ ]*1021c: R_MIPS_GNU_REL_LO16 e
|
||||
0+010220 <[^>]*> 3c010000 lui at,0x0
|
||||
[ ]*10220: R_MIPS_GNU_REL_HI16 .text
|
||||
0+010224 <[^>]*> 0024082d daddu at,at,a0
|
||||
0+010228 <[^>]*> fc220220 sd v0,544\(at\)
|
||||
[ ]*10228: R_MIPS_GNU_REL_LO16 .text
|
||||
0+01022c <[^>]*> 3c010000 lui at,0x0
|
||||
[ ]*1022c: R_MIPS_GNU_REL_HI16 g1
|
||||
0+010230 <[^>]*> 0024082d daddu at,at,a0
|
||||
0+010234 <[^>]*> fc220228 sd v0,552\(at\)
|
||||
[ ]*10234: R_MIPS_GNU_REL_LO16 g1
|
||||
0+010238 <[^>]*> 3c010001 lui at,0x1
|
||||
[ ]*10238: R_MIPS_GNU_REL_HI16 .text
|
||||
0+01023c <[^>]*> 0024082d daddu at,at,a0
|
||||
0+010240 <[^>]*> fc22823c sd v0,-32196\(at\)
|
||||
[ ]*10240: R_MIPS_GNU_REL_LO16 .text
|
||||
0+010244 <[^>]*> 3c010000 lui at,0x0
|
||||
[ ]*10244: R_MIPS_GNU_REL_HI16 g2
|
||||
0+010248 <[^>]*> 0024082d daddu at,at,a0
|
||||
0+01024c <[^>]*> fc220240 sd v0,576\(at\)
|
||||
[ ]*1024c: R_MIPS_GNU_REL_LO16 g2
|
||||
0+010250 <[^>]*> 3c010001 lui at,0x1
|
||||
[ ]*10250: R_MIPS_GNU_REL_HI16 .text
|
||||
0+010254 <[^>]*> 0024082d daddu at,at,a0
|
||||
0+010258 <[^>]*> fc2204c0 sd v0,1216\(at\)
|
||||
[ ]*10258: R_MIPS_GNU_REL_LO16 .text
|
||||
0+01025c <[^>]*> 3c010000 lui at,0x0
|
||||
[ ]*1025c: R_MIPS_GNU_REL_HI16 gf
|
||||
0+010260 <[^>]*> 0024082d daddu at,at,a0
|
||||
0+010264 <[^>]*> fc220258 sd v0,600\(at\)
|
||||
[ ]*10264: R_MIPS_GNU_REL_LO16 gf
|
||||
0+010268 <[^>]*> 3c010000 lui at,0x0
|
||||
[ ]*10268: R_MIPS_GNU_REL_HI16 e
|
||||
0+01026c <[^>]*> 0024082d daddu at,at,a0
|
||||
0+010270 <[^>]*> fc220264 sd v0,612\(at\)
|
||||
[ ]*10270: R_MIPS_GNU_REL_LO16 e
|
||||
...
|
||||
100
gas/testsuite/gas/mips/empic2.s
Normal file
100
gas/testsuite/gas/mips/empic2.s
Normal file
|
|
@ -0,0 +1,100 @@
|
|||
# Check assembly of and relocs for -membedded-pic la, lw, ld, sw, sd macros.
|
||||
|
||||
.text
|
||||
.set noreorder
|
||||
|
||||
start:
|
||||
nop
|
||||
|
||||
.globl g1
|
||||
.ent g1
|
||||
i1:
|
||||
g1:
|
||||
.space 0x8000
|
||||
nop
|
||||
.end g1
|
||||
|
||||
.globl g2
|
||||
.ent g2
|
||||
i2:
|
||||
g2:
|
||||
.space 0x8000
|
||||
nop
|
||||
.end g2
|
||||
|
||||
.globl g3
|
||||
.ent g3
|
||||
i3:
|
||||
g3:
|
||||
|
||||
la $2, (i1 - i3)($4)
|
||||
la $2, (g1 - i3)($4)
|
||||
la $2, (i2 - i3)($4)
|
||||
la $2, (g2 - i3)($4)
|
||||
la $2, (if - i3)($4)
|
||||
la $2, (gf - i3)($4)
|
||||
la $2, (e - i3)($4)
|
||||
la $2, (i1 - g3)($4)
|
||||
la $2, (g1 - g3)($4)
|
||||
la $2, (i2 - g3)($4)
|
||||
la $2, (g2 - g3)($4)
|
||||
la $2, (if - g3)($4)
|
||||
la $2, (gf - g3)($4)
|
||||
la $2, (e - g3)($4)
|
||||
|
||||
la $2, (i1 - i3)
|
||||
la $2, (g1 - i3)
|
||||
la $2, (i2 - i3)
|
||||
la $2, (g2 - i3)
|
||||
la $2, (if - i3)
|
||||
la $2, (gf - i3)
|
||||
la $2, (e - i3)
|
||||
la $2, (i1 - g3)
|
||||
la $2, (g1 - g3)
|
||||
la $2, (i2 - g3)
|
||||
la $2, (g2 - g3)
|
||||
la $2, (if - g3)
|
||||
la $2, (gf - g3)
|
||||
la $2, (e - g3)
|
||||
|
||||
lw $2, (i1 - i3)($4)
|
||||
lw $2, (g1 - i3)($4)
|
||||
lw $2, (i2 - i3)($4)
|
||||
lw $2, (g2 - i3)($4)
|
||||
lw $2, (if - i3)($4)
|
||||
lw $2, (gf - i3)($4)
|
||||
lw $2, (e - i3)($4)
|
||||
ld $2, (i1 - g3)($4)
|
||||
ld $2, (g1 - g3)($4)
|
||||
ld $2, (i2 - g3)($4)
|
||||
ld $2, (g2 - g3)($4)
|
||||
ld $2, (if - g3)($4)
|
||||
ld $2, (gf - g3)($4)
|
||||
ld $2, (e - g3)($4)
|
||||
|
||||
sw $2, (i1 - i3)($4)
|
||||
sw $2, (g1 - i3)($4)
|
||||
sw $2, (i2 - i3)($4)
|
||||
sw $2, (g2 - i3)($4)
|
||||
sw $2, (if - i3)($4)
|
||||
sw $2, (gf - i3)($4)
|
||||
sw $2, (e - i3)($4)
|
||||
sd $2, (i1 - g3)($4)
|
||||
sd $2, (g1 - g3)($4)
|
||||
sd $2, (i2 - g3)($4)
|
||||
sd $2, (g2 - g3)($4)
|
||||
sd $2, (if - g3)($4)
|
||||
sd $2, (gf - g3)($4)
|
||||
sd $2, (e - g3)($4)
|
||||
|
||||
.end g3
|
||||
|
||||
.globl gf
|
||||
.ent gf
|
||||
if:
|
||||
gf:
|
||||
nop
|
||||
.end gf
|
||||
|
||||
# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
|
||||
.space 8
|
||||
|
|
@ -160,6 +160,7 @@ if { [istarget mips*-*-*] } then {
|
|||
}
|
||||
run_dump_test "elf${el}-rel3"
|
||||
run_dump_test "${tmips}${el}empic"
|
||||
run_dump_test "empic2"
|
||||
if { !$no_mips16 } {
|
||||
run_dump_test "${tmips}mips${el}16-e"
|
||||
run_dump_test "${tmips}mips${el}16-f"
|
||||
|
|
|
|||
|
|
@ -56,8 +56,12 @@ OFFSET [ ]+ TYPE VALUE
|
|||
0+00000b8 R_MIPS_64 \.text
|
||||
0+00000cc R_MIPS_GNU_REL16_S2 \.text
|
||||
0+00000d0 R_MIPS_GNU_REL16_S2 \.text
|
||||
0+00000dc R_MIPS_32 \.text
|
||||
0+00000e8 R_MIPS_64 \.text
|
||||
0+00000d4 R_MIPS_GNU_REL_HI16 \.text
|
||||
0+00000d8 R_MIPS_GNU_REL_LO16 \.text
|
||||
0+00000dc R_MIPS_GNU_REL_HI16 \.text
|
||||
0+00000e0 R_MIPS_GNU_REL_LO16 \.text
|
||||
0+00000e4 R_MIPS_32 \.text
|
||||
0+00000f0 R_MIPS_64 \.text
|
||||
|
||||
|
||||
RELOCATION RECORDS FOR \[\.foo\]:
|
||||
|
|
@ -123,9 +127,9 @@ Contents of section \.text:
|
|||
00a0 0000033c d80063[26]4 0000033c e80063[26]4 .*
|
||||
00b0 cc000000 34000000 cc000000 00000000 .*
|
||||
00c0 34000000 00000000 00000000 32000010 .*
|
||||
00d0 33000010 34000324 3c000324 cc000000 .*
|
||||
00e0 34000000 00000000 cc000000 00000000 .*
|
||||
00f0 34000000 00000000 00000000 00000000 .*
|
||||
00d0 33000010 0000033c 0c0163[26]4 0000033c .*
|
||||
00e0 1c0163[26]4 cc000000 34000000 00000000 .*
|
||||
00f0 cc000000 00000000 34000000 00000000 .*
|
||||
Contents of section \.data:
|
||||
Contents of section \.reginfo:
|
||||
0000 08000080 00000000 00000000 00000000 .*
|
||||
|
|
|
|||
|
|
@ -56,8 +56,12 @@ OFFSET [ ]+ TYPE VALUE
|
|||
0+00000b8 R_MIPS_64 \.text
|
||||
0+00000cc R_MIPS_GNU_REL16_S2 \.text
|
||||
0+00000d0 R_MIPS_GNU_REL16_S2 \.text
|
||||
0+00000dc R_MIPS_32 \.text
|
||||
0+00000e8 R_MIPS_64 \.text
|
||||
0+00000d4 R_MIPS_GNU_REL_HI16 \.text
|
||||
0+00000d8 R_MIPS_GNU_REL_LO16 \.text
|
||||
0+00000dc R_MIPS_GNU_REL_HI16 \.text
|
||||
0+00000e0 R_MIPS_GNU_REL_LO16 \.text
|
||||
0+00000e4 R_MIPS_32 \.text
|
||||
0+00000f0 R_MIPS_64 \.text
|
||||
|
||||
|
||||
RELOCATION RECORDS FOR \[\.foo\]:
|
||||
|
|
@ -123,9 +127,9 @@ Contents of section \.text:
|
|||
00a0 3c030000 [26]46300d8 3c030000 [26]46300e8 .*
|
||||
00b0 000000cc 00000034 00000000 000000cc .*
|
||||
00c0 00000000 00000034 00000000 10000032 .*
|
||||
00d0 10000033 24030034 2403003c 000000cc .*
|
||||
00e0 00000034 00000000 00000000 000000cc .*
|
||||
00f0 00000000 00000034 00000000 00000000 .*
|
||||
00d0 10000033 3c030000 [26]463010c 3c030000 .*
|
||||
00e0 [26]463011c 000000cc 00000034 00000000 .*
|
||||
00f0 00000000 000000cc 00000000 00000034 .*
|
||||
Contents of section \.data:
|
||||
Contents of section \.reginfo:
|
||||
0000 80000008 00000000 00000000 00000000 .*
|
||||
|
|
|
|||
Loading…
Reference in a new issue