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sim: cris: update testsuite output after strsignal change

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This commit is contained in:
Mike Frysinger 2012-03-21 04:50:01 +00:00
parent 5c73fae010
commit af209c380f
38 changed files with 50 additions and 37 deletions
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13
sim/testsuite/sim/cris/ChangeLog
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@ -1,3 +1,16 @@
2012-03-21 Mike Frysinger <vapier@gentoo.org>
* asm/addqpc.ms: Update output to ignore decoded signal string.
* asm/boundmv32.ms, asm/fidxd.ms, asm/fidxi.ms, asm/ftagd.ms,
asm/ftagi.ms, asm/halt.ms, asm/io6.ms, asm/io7.ms, asm/io8.ms,
asm/io9.ms, asm/movecpc.ms, asm/movempc.ms, asm/movepcb.ms,
asm/movepcd.ms, asm/movepcw.ms, asm/moveqpc.ms, asm/moverbpc.ms,
asm/moverdpc.ms, asm/moverpcb.ms, asm/moverpcw.ms, asm/moverwpc.ms,
asm/movppc.ms, asm/movrss.ms, asm/movscpc.ms, asm/movsmpc.ms,
asm/movsrpc.ms, asm/movssr.ms, asm/movucpc.ms, asm/movumpc.ms,
asm/movurpc.ms, asm/msteppc1.ms, asm/msteppc2.ms, asm/msteppc3.ms,
asm/rfg.ms, asm/sbfs.ms, asm/subqpc.ms: Likewise.
2010-10-07 Hans-Peter Nilsson <hp@axis.com>
* c/seek3.c, c/seek4.c: New tests.

2
sim/testsuite/sim/cris/asm/addqpc.ms
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@ -1,6 +1,6 @@
# mach: crisv3 crisv8 crisv10
# xerror:
# output: General register read of PC is not implemented.\nprogram stopped with signal 5.\n
# output: General register read of PC is not implemented.\nprogram stopped with signal 5 (*).\n
.include "testutils.inc"
start

2
sim/testsuite/sim/cris/asm/boundmv32.ms
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@ -1,6 +1,6 @@
# mach: crisv32
# xerror:
# output: program stopped with signal 4.\n
# output: program stopped with signal 4 (*).\n
.include "testutils.inc"
; Check that bound with a memory operand is invalid.

2
sim/testsuite/sim/cris/asm/fidxd.ms
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@ -1,6 +1,6 @@
# mach: crisv32
# xerror:
# output: FIDXD isn't implemented\nprogram stopped with signal 5.\n
# output: FIDXD isn't implemented\nprogram stopped with signal 5 (*).\n
.include "testutils.inc"
start

2
sim/testsuite/sim/cris/asm/fidxi.ms
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@ -1,6 +1,6 @@
# mach: crisv32
# xerror:
# output: FIDXI isn't implemented\nprogram stopped with signal 5.\n
# output: FIDXI isn't implemented\nprogram stopped with signal 5 (*).\n
.include "testutils.inc"
start

2
sim/testsuite/sim/cris/asm/ftagd.ms
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@ -1,6 +1,6 @@
# mach: crisv32
# xerror:
# output: FTAGD isn't implemented\nprogram stopped with signal 5.\n
# output: FTAGD isn't implemented\nprogram stopped with signal 5 (*).\n
.include "testutils.inc"
start

2
sim/testsuite/sim/cris/asm/ftagi.ms
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@ -1,6 +1,6 @@
# mach: crisv32
# xerror:
# output: FTAGI isn't implemented\nprogram stopped with signal 5.\n
# output: FTAGI isn't implemented\nprogram stopped with signal 5 (*).\n
.include "testutils.inc"
start

2
sim/testsuite/sim/cris/asm/halt.ms
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@ -1,6 +1,6 @@
# mach: crisv32
# xerror:
# output: HALT isn't implemented\nprogram stopped with signal 5.\n
# output: HALT isn't implemented\nprogram stopped with signal 5 (*).\n
.include "testutils.inc"
start

2
sim/testsuite/sim/cris/asm/io6.ms
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@ -4,7 +4,7 @@
# xerror:
# output: b1e\n
# output: core: 4 byte write to unmapped address 0x90000008 at 0x16\n
# output: program stopped with signal 11.\n
# output: program stopped with signal 11 (*).\n
; Check that invalid access to the simulator area is recognized.
; "FAIL" area.

2
sim/testsuite/sim/cris/asm/io7.ms
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@ -4,7 +4,7 @@
# xerror:
# output: ce11d0c\n
# output: core: 4 byte write to unmapped address 0x90000004 at 0x16\n
# output: program stopped with signal 11.\n
# output: program stopped with signal 11 (*).\n
; Check that invalid access to the simulator area is recognized.
; "PASS" area.

2
sim/testsuite/sim/cris/asm/io8.ms
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@ -3,7 +3,7 @@
# xerror:
# output: b1e\n
# output: core: 4 byte write to unmapped address 0x90000008 at 0x16\n
# output: program stopped with signal 11.\n
# output: program stopped with signal 11 (*).\n
; Check invalid access valid with --cris-900000xx.
; "FAIL" area.

2
sim/testsuite/sim/cris/asm/io9.ms
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@ -3,7 +3,7 @@
# xerror:
# output: ce11d0c\n
# output: core: 4 byte write to unmapped address 0x90000004 at 0x16\n
# output: program stopped with signal 11.\n
# output: program stopped with signal 11 (*).\n
; Check invalid access valid with --cris-900000xx.
; "PASS" area.

2
sim/testsuite/sim/cris/asm/movecpc.ms
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@ -1,6 +1,6 @@
# mach: crisv3 crisv8 crisv10
# xerror:
# output: General register * PC is not implemented.\nprogram stopped with signal 5.\n
# output: General register * PC is not implemented.\nprogram stopped with signal 5 (*).\n
# We deliberately match both "read from" and "write to" above.

2
sim/testsuite/sim/cris/asm/movempc.ms
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@ -1,6 +1,6 @@
# mach: crisv3 crisv8 crisv10
# xerror:
# output: General register write to PC is not implemented.\nprogram stopped with signal 5.\n
# output: General register write to PC is not implemented.\nprogram stopped with signal 5 (*).\n
.include "testutils.inc"
start

2
sim/testsuite/sim/cris/asm/movepcb.ms
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@ -1,6 +1,6 @@
# mach: crisv3 crisv8 crisv10
# xerror:
# output: General register read of PC is not implemented.\nprogram stopped with signal 5.\n
# output: General register read of PC is not implemented.\nprogram stopped with signal 5 (*).\n
.include "testutils.inc"
startnostack

2
sim/testsuite/sim/cris/asm/movepcd.ms
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@ -1,6 +1,6 @@
# mach: crisv3 crisv8 crisv10
# xerror:
# output: General register * PC is not implemented.\nprogram stopped with signal 5.\n
# output: General register * PC is not implemented.\nprogram stopped with signal 5 (*).\n
# Both source and dest contain PC for "test.d r" (move.d r,r). Ideally,
# the output message should say "read" of PC, but we allow PC as source in

2
sim/testsuite/sim/cris/asm/movepcw.ms
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@ -1,6 +1,6 @@
# mach: crisv3 crisv8 crisv10
# xerror:
# output: General register read of PC is not implemented.\nprogram stopped with signal 5.\n
# output: General register read of PC is not implemented.\nprogram stopped with signal 5 (*).\n
.include "testutils.inc"
startnostack

2
sim/testsuite/sim/cris/asm/moveqpc.ms
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@ -1,6 +1,6 @@
# mach: crisv3 crisv8 crisv10
# xerror:
# output: General register write to PC is not implemented.\nprogram stopped with signal 5.\n
# output: General register write to PC is not implemented.\nprogram stopped with signal 5 (*).\n
.include "testutils.inc"
startnostack

2
sim/testsuite/sim/cris/asm/moverbpc.ms
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@ -1,6 +1,6 @@
# mach: crisv3 crisv8 crisv10
# xerror:
# output: General register write to PC is not implemented.\nprogram stopped with signal 5.\n
# output: General register write to PC is not implemented.\nprogram stopped with signal 5 (*).\n
.include "testutils.inc"
startnostack

2
sim/testsuite/sim/cris/asm/moverdpc.ms
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@ -1,6 +1,6 @@
# mach: crisv3 crisv8 crisv10
# xerror:
# output: General register write to PC is not implemented.\nprogram stopped with signal 5.\n
# output: General register write to PC is not implemented.\nprogram stopped with signal 5 (*).\n
.include "testutils.inc"
startnostack

2
sim/testsuite/sim/cris/asm/moverpcb.ms
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@ -1,6 +1,6 @@
# mach: crisv3 crisv8 crisv10
# xerror:
# output: General register read of PC is not implemented.\nprogram stopped with signal 5.\n
# output: General register read of PC is not implemented.\nprogram stopped with signal 5 (*).\n
.include "testutils.inc"
startnostack

2
sim/testsuite/sim/cris/asm/moverpcw.ms
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@ -1,6 +1,6 @@
# mach: crisv3 crisv8 crisv10
# xerror:
# output: General register read of PC is not implemented.\nprogram stopped with signal 5.\n
# output: General register read of PC is not implemented.\nprogram stopped with signal 5 (*).\n
.include "testutils.inc"
startnostack

2
sim/testsuite/sim/cris/asm/moverwpc.ms
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@ -1,6 +1,6 @@
# mach: crisv3 crisv8 crisv10
# xerror:
# output: General register write to PC is not implemented.\nprogram stopped with signal 5.\n
# output: General register write to PC is not implemented.\nprogram stopped with signal 5 (*).\n
.include "testutils.inc"
startnostack

2
sim/testsuite/sim/cris/asm/movppc.ms
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@ -1,6 +1,6 @@
# mach: crisv3 crisv8 crisv10
# xerror:
# output: General register read of PC is not implemented.\nprogram stopped with signal 5.\n
# output: General register read of PC is not implemented.\nprogram stopped with signal 5 (*).\n
.include "testutils.inc"
start

2
sim/testsuite/sim/cris/asm/movrss.ms
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@ -1,6 +1,6 @@
# mach: crisv32
# xerror:
# output: Write to support register is unimplemented\nprogram stopped with signal 5.\n
# output: Write to support register is unimplemented\nprogram stopped with signal 5 (*).\n
.include "testutils.inc"
start

2
sim/testsuite/sim/cris/asm/movscpc.ms
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@ -1,6 +1,6 @@
# mach: crisv3 crisv8 crisv10
# xerror:
# output: General register write to PC is not implemented.\nprogram stopped with signal 5.\n
# output: General register write to PC is not implemented.\nprogram stopped with signal 5 (*).\n
.include "testutils.inc"
start

2
sim/testsuite/sim/cris/asm/movsmpc.ms
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@ -1,6 +1,6 @@
# mach: crisv3 crisv8 crisv10
# xerror:
# output: General register write to PC is not implemented.\nprogram stopped with signal 5.\n
# output: General register write to PC is not implemented.\nprogram stopped with signal 5 (*).\n
.include "testutils.inc"
start

2
sim/testsuite/sim/cris/asm/movsrpc.ms
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@ -1,6 +1,6 @@
# mach: crisv3 crisv8 crisv10
# xerror:
# output: General register write to PC is not implemented.\nprogram stopped with signal 5.\n
# output: General register write to PC is not implemented.\nprogram stopped with signal 5 (*).\n
.include "testutils.inc"
start

2
sim/testsuite/sim/cris/asm/movssr.ms
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@ -1,6 +1,6 @@
# mach: crisv32
# xerror:
# output: Read of support register is unimplemented\nprogram stopped with signal 5.\n
# output: Read of support register is unimplemented\nprogram stopped with signal 5 (*).\n
.include "testutils.inc"
start

2
sim/testsuite/sim/cris/asm/movucpc.ms
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@ -1,6 +1,6 @@
# mach: crisv3 crisv8 crisv10
# xerror:
# output: General register write to PC is not implemented.\nprogram stopped with signal 5.\n
# output: General register write to PC is not implemented.\nprogram stopped with signal 5 (*).\n
.include "testutils.inc"
start

2
sim/testsuite/sim/cris/asm/movumpc.ms
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@ -1,6 +1,6 @@
# mach: crisv3 crisv8 crisv10
# xerror:
# output: General register write to PC is not implemented.\nprogram stopped with signal 5.\n
# output: General register write to PC is not implemented.\nprogram stopped with signal 5 (*).\n
.include "testutils.inc"
start

2
sim/testsuite/sim/cris/asm/movurpc.ms
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@ -1,6 +1,6 @@
# mach: crisv3 crisv8 crisv10
# xerror:
# output: General register write to PC is not implemented.\nprogram stopped with signal 5.\n
# output: General register write to PC is not implemented.\nprogram stopped with signal 5 (*).\n
.include "testutils.inc"
start

2
sim/testsuite/sim/cris/asm/msteppc1.ms
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@ -1,7 +1,7 @@
# mach: crisv3 crisv8 crisv10
# xerror:
# output: General register read of PC is not implemented.\n
# output: program stopped with signal 5.\n
# output: program stopped with signal 5 (*).\n
.include "testutils.inc"
start

2
sim/testsuite/sim/cris/asm/msteppc2.ms
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@ -1,7 +1,7 @@
# mach: crisv3 crisv8 crisv10
# xerror:
# output: General register read of PC is not implemented.\n
# output: program stopped with signal 5.\n
# output: program stopped with signal 5 (*).\n
.include "testutils.inc"
start

2
sim/testsuite/sim/cris/asm/msteppc3.ms
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@ -1,7 +1,7 @@
# mach: crisv3 crisv8 crisv10
# xerror:
# output: General register read of PC is not implemented.\n
# output: program stopped with signal 5.\n
# output: program stopped with signal 5 (*).\n
.include "testutils.inc"
start

2
sim/testsuite/sim/cris/asm/rfg.ms
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@ -1,6 +1,6 @@
# mach: crisv32
# xerror:
# output: RFG isn't implemented\nprogram stopped with signal 5.\n
# output: RFG isn't implemented\nprogram stopped with signal 5 (*).\n
.include "testutils.inc"
start

2
sim/testsuite/sim/cris/asm/sbfs.ms
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@ -1,6 +1,6 @@
# mach: crisv10
# xerror:
# output: SBFS isn't implemented\nprogram stopped with signal 5.\n
# output: SBFS isn't implemented\nprogram stopped with signal 5 (*).\n
.include "testutils.inc"
start

2
sim/testsuite/sim/cris/asm/subqpc.ms
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@ -1,6 +1,6 @@
# mach: crisv3 crisv8 crisv10
# xerror:
# output: General register read of PC is not implemented.\nprogram stopped with signal 5.\n
# output: General register read of PC is not implemented.\nprogram stopped with signal 5 (*).\n
.include "testutils.inc"
start