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For MACU add unsigned multiply to accumulator.

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Test.
This commit is contained in:
Andrew Cagney 1997-12-02 05:18:27 +00:00
parent 8b9c29f5cb
commit ae55807561
5 changed files with 96 additions and 5 deletions
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5
sim/d10v/ChangeLog
View file

@ -1,3 +1,8 @@
Tue Dec 2 15:01:08 1997 Andrew Cagney <cagney@b1.cygnus.com>
* simops.c (OP_3A00): For "macu", perform multiply stage using 32
bit rather than 16 bit precision.
Tue Dec 2 11:04:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
* simops.c (OP_1000): For "sub2w", compute carry by comparing

12
sim/d10v/simops.c
View file

@ -1352,13 +1352,17 @@ OP_1A00 ()
void
OP_3A00 ()
{
int64 tmp;
uint64 tmp;
uint32 src1;
uint32 src2;
trace_input ("macu", OP_ACCUM, OP_REG, OP_REG);
tmp = SEXT40 (State.regs[OP[1]] * State.regs[OP[2]]);
src1 = (uint16) State.regs[OP[1]];
src2 = (uint16) State.regs[OP[2]];
tmp = src1 * src2;
if (State.FX)
tmp = SEXT40( (tmp << 1) & MASK40);
State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) + tmp) & MASK40;
tmp = (tmp << 1);
State.a[OP[0]] = (State.a[OP[0]] + tmp) & MASK40;
trace_output (OP_ACCUM);
}

3
sim/testsuite/d10v-elf/.Sanitize
View file

@ -10,9 +10,12 @@ exit47.s
hello.s
loop.s
t-macros.i
t-mac.s
t-rachi.s
t-rep.s
t-subi.s
t-sub2w.s
t-mvtac.s
Things-to-lose:

4
sim/testsuite/d10v-elf/Makefile.in
View file

@ -43,7 +43,9 @@ TESTS = \
t-rachi.ok \
t-rep.ok \
t-subi.ok \
t-sub2w.ok
t-sub2w.ok \
t-mvtac.ok \
t-mac.ok
AS_FOR_TARGET = `\
if [ -x ../../../gas/as-new ]; then \

77
sim/testsuite/d10v-elf/t-mac.s Normal file
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@ -0,0 +1,77 @@
.include "t-macros.i"
start
;; clear FX
ldi r2, #0x8005
mvtc r2, cr0
loadacc2 a1 0x7f 0xffff 0xffff
ldi r8, 0xffff
ldi r9, 0x8001
test_macu1:
MACU a1, r9, r8
checkacc2 1 a1 0x80 0x8000 0x7FFE
;; set FX
ldi r2, #0x8085
mvtc r2, cr0
loadacc2 a1 0x7f 0xffff 0xffff
ldi r8, 0xffff
ldi r9, 0x8001
test_macu2:
MACU a1, r9, r8
checkacc2 2 a1 0x81 0x0000 0xfffd
;; clear FX
ldi r2, #0x8005
mvtc r2, cr0
loadacc2 a1 0x7f 0xffff 0xffff
ldi r8, 0xffff
ldi r9, 0x7FFF
test_macsu1:
MACSU a1, r9, r8
checkacc2 3 a1 0x80 0x7FFE 0x8000
;; set FX
ldi r2, #0x8085
mvtc r2, cr0
loadacc2 a1 0x7f 0xffff 0xffff
ldi r8, 0xffff
ldi r9, 0x7FFF
test_macsu2:
MACSU a1, r9, r8
checkacc2 4 a1 0x80 0xfffd 0x0001
;; clear FX
ldi r2, #0x8005
mvtc r2, cr0
loadacc2 a1 0x7f 0xffff 0xffff
ldi r8, 0xffff
ldi r9, 0x8001
test_macsu3:
MACSU a1, r9, r8
checkacc2 5 a1 0x7F 0x8001 0x7FFE
;; set FX
ldi r2, #0x8085
mvtc r2, cr0
loadacc2 a1 0x7f 0xffff 0xffff
ldi r8, 0xffff
ldi r9, 0x8001
test_macsu4:
MACSU a1, r9, r8
checkacc2 6 a1 0x7f 0x0002 0xFFFD
exit0