Add "attn", "lq" and "stq" power4 insns.
This commit is contained in:
Alan Modra
parent
2a93846b50
commit
adadcc0cc9
12 changed files with 484 additions and 171 deletions
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@ -1,3 +1,8 @@
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2003-06-10 Alan Modra <amodra@bigpond.net.au>
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Gary Hade <garyhade@us.ibm.com>
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* elf64-ppc.c (ppc64_elf_relocate_section <*_DS>): Special case lq.
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2003-06-10 Richard Sandiford <rsandifo@redhat.com>
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* archures.c (bfd_mach_h8300sxn): New architecture.
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@ -7315,7 +7315,7 @@ ppc64_elf_relocate_section (output_bfd, info, input_bfd, input_section,
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bfd_vma relocation;
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bfd_boolean unresolved_reloc;
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bfd_boolean warned;
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long insn;
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long insn, mask;
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struct ppc_stub_hash_entry *stub_entry;
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bfd_vma max_br_offset;
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bfd_vma from;
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@ -8406,12 +8406,23 @@ ppc64_elf_relocate_section (output_bfd, info, input_bfd, input_section,
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case R_PPC64_TPREL16_LO_DS:
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case R_PPC64_DTPREL16_DS:
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case R_PPC64_DTPREL16_LO_DS:
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if (((relocation + addend) & 3) != 0)
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insn = bfd_get_32 (input_bfd, contents + (rel->r_offset & ~3));
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mask = 3;
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/* If this reloc is against an lq insn, then the value must be
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a multiple of 16. This is somewhat of a hack, but the
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"correct" way to do this by defining _DQ forms of all the
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_DS relocs bloats all reloc switches in this file. It
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doesn't seem to make much sense to use any of these relocs
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in data, so testing the insn should be safe. */
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if ((insn & (0x3f << 26)) == (56 << 26))
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mask = 15;
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if (((relocation + addend) & mask) != 0)
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{
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(*_bfd_error_handler)
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(_("%s: error: relocation %s not a multiple of 4"),
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(_("%s: error: relocation %s not a multiple of %d"),
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bfd_archive_filename (input_bfd),
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ppc64_elf_howto_table[(int) r_type]->name);
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ppc64_elf_howto_table[(int) r_type]->name,
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mask + 1);
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bfd_set_error (bfd_error_bad_value);
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ret = FALSE;
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continue;
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@ -1,3 +1,9 @@
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2003-06-10 Alan Modra <amodra@bigpond.net.au>
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Gary Hade <garyhade@us.ibm.com>
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* config/tc-ppc.c (md_assemble): Handle PPC_OPERAND_DQ.
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(md_apply_fix3): Special case lq insn.
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2003-06-10 Richard Sandiford <rsandifo@redhat.com>
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* config/tc-h8300.c (get_rtsl_operands): Accept unbracketed register
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@ -2447,7 +2447,7 @@ md_assemble (str)
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}
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if (ppc_obj64
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&& (operand->flags & PPC_OPERAND_DS) != 0)
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&& (operand->flags & (PPC_OPERAND_DS | PPC_OPERAND_DQ)) != 0)
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{
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switch (reloc)
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{
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@ -5714,13 +5714,18 @@ md_apply_fix3 (fixP, valP, seg)
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abort ();
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{
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unsigned char *where = fixP->fx_frag->fr_literal + fixP->fx_where;
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unsigned long val;
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long val, mask;
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if (target_big_endian)
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val = bfd_getb16 (where);
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val = bfd_getb32 (where - 2);
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else
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val = bfd_getl16 (where);
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val |= (value & 0xfffc);
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val = bfd_getl32 (where);
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mask = 0xfffc;
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/* lq insns reserve the four lsbs. */
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if ((ppc_cpu & PPC_OPCODE_POWER4) != 0
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&& (val & (0x3f << 26)) == (56 << 26))
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mask = 0xfff0;
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val |= value & mask;
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if (target_big_endian)
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bfd_putb16 ((bfd_vma) val, where);
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else
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@ -1,3 +1,8 @@
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2003-06-10 Gary Hade <garyhade@us.ibm.com>
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* gas/ppc/test2elf64.{s,d}: New test.
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* gas/ppc/ppc.exp: Run new test.
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2003-06-10 Richard Sandiford <rsandifo@redhat.com>
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* gas/h8300/h8sx_mov_imm.[sd]: New test.
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@ -10,6 +10,7 @@ if { [istarget powerpc64*-*-*] || [istarget *-*-elf64*]} then {
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run_dump_test "astest64"
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run_dump_test "astest2_64"
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run_dump_test "test1elf64"
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run_dump_test "test2elf64"
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} elseif { [istarget powerpc*-*aix*] } then {
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run_dump_test "test1xcoff32"
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} elseif { [istarget powerpc*-*-*bsd*] \
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101
gas/testsuite/gas/ppc/test2elf64.d
Normal file
101
gas/testsuite/gas/ppc/test2elf64.d
Normal file
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@ -0,0 +1,101 @@
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#objdump: -Drx -Mpower4
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#as: -mpower4
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#name: PowerPC Test 2, 64 bit elf, power4 instructions
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.*: +file format elf64-powerpc
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.*
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architecture: powerpc:common64, flags 0x0+11:
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HAS_RELOC, HAS_SYMS
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start address 0x0+
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Sections:
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Idx Name +Size +VMA +LMA +File off +Algn
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+0 \.text +0+68 +0+ +0+ +.*
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+CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
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+1 \.data +0+10 +0+ +0+ +.*
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+CONTENTS, ALLOC, LOAD, DATA
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+2 \.bss +0+ +0+ +0+ +.*
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+ALLOC
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+3 \.toc +0+30 +0+ +0+ +.*
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+CONTENTS, ALLOC, LOAD, RELOC, DATA
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SYMBOL TABLE:
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0+ l +d +\.text 0+
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0+ l +d +\.data 0+
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0+ l +d +\.bss 0+
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0+ l +\.data 0+ dsym0
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0+8 l +\.data 0+ dsym1
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0+ l +d +\.toc 0+
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0+8 l +\.data 0+ usym0
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0+10 l +\.data 0+ usym1
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0+ +\*UND\* 0+ esym0
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0+ +\*UND\* 0+ esym1
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Disassembly of section \.text:
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0+ <\.text>:
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+0: e0 83 00 00 lq r4,0\(r3\)
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2: R_PPC64_ADDR16_LO_DS dsym0
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+4: e0 83 00 00 lq r4,0\(r3\)
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6: R_PPC64_ADDR16_LO_DS dsym1
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+8: e0 83 00 00 lq r4,0\(r3\)
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a: R_PPC64_ADDR16_LO_DS usym0
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+c: e0 83 00 00 lq r4,0\(r3\)
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e: R_PPC64_ADDR16_LO_DS usym1
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+10: e0 83 00 00 lq r4,0\(r3\)
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12: R_PPC64_ADDR16_LO_DS esym0
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+14: e0 83 00 00 lq r4,0\(r3\)
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16: R_PPC64_ADDR16_LO_DS esym1
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+18: e0 82 00 00 lq r4,0\(r2\)
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1a: R_PPC64_TOC16_DS \.toc
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+1c: e0 82 00 00 lq r4,0\(r2\)
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1e: R_PPC64_TOC16_DS \.toc\+0x8
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+20: e0 82 00 10 lq r4,16\(r2\)
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22: R_PPC64_TOC16_DS \.toc\+0x10
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+24: e0 82 00 10 lq r4,16\(r2\)
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26: R_PPC64_TOC16_DS \.toc\+0x18
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+28: e0 82 00 20 lq r4,32\(r2\)
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2a: R_PPC64_TOC16_DS \.toc\+0x20
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+2c: e0 82 00 20 lq r4,32\(r2\)
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2e: R_PPC64_TOC16_DS \.toc\+0x28
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+30: e0 c2 00 20 lq r6,32\(r2\)
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32: R_PPC64_TOC16_LO_DS \.toc\+0x28
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+34: e0 80 00 00 lq r4,0\(r0\)
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36: R_PPC64_ADDR16_LO_DS \.text
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+38: e0 c3 00 00 lq r6,0\(r3\)
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3a: R_PPC64_GOT16_DS dsym0
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+3c: e0 c3 00 00 lq r6,0\(r3\)
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3e: R_PPC64_GOT16_LO_DS dsym0
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+40: e0 c3 00 00 lq r6,0\(r3\)
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42: R_PPC64_PLT16_LO_DS dsym0
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+44: e0 c3 00 00 lq r6,0\(r3\)
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46: R_PPC64_SECTOFF_DS dsym1
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+48: e0 c3 00 00 lq r6,0\(r3\)
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4a: R_PPC64_SECTOFF_LO_DS dsym1
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+4c: e0 c4 00 10 lq r6,16\(r4\)
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+50: f8 c7 00 02 stq r6,0\(r7\)
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+54: f8 c7 00 12 stq r6,16\(r7\)
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+58: f8 c7 ff f2 stq r6,-16\(r7\)
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+5c: f8 c7 80 02 stq r6,-32768\(r7\)
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+60: f8 c7 7f f2 stq r6,32752\(r7\)
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+64: 00 00 02 00 attn
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Disassembly of section \.data:
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0+ <dsym0>:
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+0: 00 00 00 00 \.long 0x0
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+4: de ad be ef stfdu f21,-16657\(r13\)
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0+8 <dsym1>:
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+8: 00 00 00 00 \.long 0x0
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+c: ca fe ba be lfd f23,-17730\(r30\)
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Disassembly of section \.toc:
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0+ <\.toc>:
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\.\.\.
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0: R_PPC64_ADDR64 dsym0
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8: R_PPC64_ADDR64 dsym1
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10: R_PPC64_ADDR64 usym0
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18: R_PPC64_ADDR64 usym1
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20: R_PPC64_ADDR64 esym0
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28: R_PPC64_ADDR64 esym1
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53
gas/testsuite/gas/ppc/test2elf64.s
Normal file
53
gas/testsuite/gas/ppc/test2elf64.s
Normal file
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@ -0,0 +1,53 @@
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.section ".data"
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dsym0: .llong 0xdeadbeef
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dsym1:
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.section ".toc"
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.L_tsym0:
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.tc ignored0[TC],dsym0
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.L_tsym1:
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.tc ignored1[TC],dsym1
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.L_tsym2:
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.tc ignored2[TC],usym0
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.L_tsym3:
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.tc ignored3[TC],usym1
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.L_tsym4:
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.tc ignored4[TC],esym0
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.L_tsym5:
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.tc ignored5[TC],esym1
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.section ".text"
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lq 4,dsym0@l(3)
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lq 4,dsym1@l(3)
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lq 4,usym0@l(3)
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lq 4,usym1@l(3)
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lq 4,esym0@l(3)
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lq 4,esym1@l(3)
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lq 4,.L_tsym0@toc(2)
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lq 4,.L_tsym1@toc(2)
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lq 4,.L_tsym2@toc(2)
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lq 4,.L_tsym3@toc(2)
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lq 4,.L_tsym4@toc(2)
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lq 4,.L_tsym5@toc(2)
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lq 6,.L_tsym5@toc@l(2)
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lq 4,.text@l(0)
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lq 6,dsym0@got(3)
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lq 6,dsym0@got@l(3)
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lq 6,dsym0@plt@l(3)
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lq 6,dsym1@sectoff(3)
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lq 6,dsym1@sectoff@l(3)
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lq 6,usym1-dsym0@l(4)
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stq 6, 0(7)
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stq 6, 16(7)
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stq 6, -16(7)
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stq 6, -32768(7)
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stq 6, 32752(7)
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attn
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.section ".data"
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usym0: .llong 0xcafebabe
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usym1:
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@ -1,3 +1,7 @@
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2003-06-10 Gary Hade <garyhade@us.ibm.com>
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* ppc.h (PPC_OPERAND_DQ): Define.
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2003-06-10 Richard Sandiford <rsandifo@redhat.com>
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* h8300.h (IMM4_NS, IMM8_NS): New.
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@ -1,5 +1,5 @@
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/* ppc.h -- Header file for PowerPC opcode table
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Copyright 1994, 1995, 1999, 2000, 2001, 2002
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Copyright 1994, 1995, 1999, 2000, 2001, 2002, 2003
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Free Software Foundation, Inc.
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Written by Ian Lance Taylor, Cygnus Support
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@ -273,6 +273,9 @@ extern const struct powerpc_operand powerpc_operands[];
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/* This operand is for the DS field in a DS form instruction. */
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#define PPC_OPERAND_DS (020000)
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/* This operand is for the DQ field in a DQ form instruction. */
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#define PPC_OPERAND_DQ (040000)
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/* The POWER and PowerPC assemblers use a few macros. We keep them
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with the operands table for simplicity. The macro table is an
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@ -1,3 +1,10 @@
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2003-06-10 Gary Hade <garyhade@us.ibm.com>
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Alan Modra <amodra@bigpond.net.au>
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* ppc-opc.c (DQ, RAQ, RSQ, RTQ): Define.
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(insert_dq, extract_dq, insert_raq, insert_rtq, insert_rsq): New.
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(powerpc_opcodes): Add "attn", "lq" and "stq".
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2003-06-10 Richard Sandiford <rsandifo@redhat.com>
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* h8300-dis.c (bfd_h8_disassemble): Don't print brackets round
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@ -68,6 +68,10 @@ static unsigned long insert_boe
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PARAMS ((unsigned long, long, int, const char **));
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static long extract_boe
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PARAMS ((unsigned long, int, int *));
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static unsigned long insert_dq
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PARAMS ((unsigned long, long, int, const char **));
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static long extract_dq
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PARAMS ((unsigned long, int, int *));
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static unsigned long insert_ds
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PARAMS ((unsigned long, long, int, const char **));
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static long extract_ds
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@ -104,12 +108,18 @@ static unsigned long insert_ral
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PARAMS ((unsigned long, long, int, const char **));
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static unsigned long insert_ram
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PARAMS ((unsigned long, long, int, const char **));
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static unsigned long insert_raq
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PARAMS ((unsigned long, long, int, const char **));
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static unsigned long insert_ras
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PARAMS ((unsigned long, long, int, const char **));
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static unsigned long insert_rbs
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PARAMS ((unsigned long, long, int, const char **));
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static long extract_rbs
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PARAMS ((unsigned long, int, int *));
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static unsigned long insert_rsq
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PARAMS ((unsigned long, long, int, const char **));
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static unsigned long insert_rtq
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PARAMS ((unsigned long, long, int, const char **));
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static unsigned long insert_sh6
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PARAMS ((unsigned long, long, int, const char **));
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static long extract_sh6
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@ -279,9 +289,15 @@ const struct powerpc_operand powerpc_operands[] =
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#define DES DE + 1
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{ 14, 0, insert_des, extract_des, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
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/* The DQ field in a DQ form instruction. This is like D, but the
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lower four bits are forced to zero. */
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#define DQ DES + 1
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{ 16, 0, insert_dq, extract_dq,
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PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ },
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/* The DS field in a DS form instruction. This is like D, but the
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lower two bits are forced to zero. */
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#define DS DES + 1
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#define DS DQ + 1
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{ 16, 0, insert_ds, extract_ds,
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PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },
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@ -389,15 +405,20 @@ const struct powerpc_operand powerpc_operands[] =
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{ 16, 0, insert_nsi, extract_nsi,
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PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
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/* The RA field in an D, DS, X, XO, M, or MDS form instruction. */
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/* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */
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#define RA NSI + 1
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#define RA_MASK (0x1f << 16)
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{ 5, 16, 0, 0, PPC_OPERAND_GPR },
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/* The RA field in the DQ form lq instruction, which has special
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value restrictions. */
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#define RAQ RA + 1
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{ 5, 16, insert_raq, 0, PPC_OPERAND_GPR },
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/* The RA field in a D or X form instruction which is an updating
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load, which means that the RA field may not be zero and may not
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equal the RT field. */
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#define RAL RA + 1
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#define RAL RAQ + 1
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{ 5, 16, insert_ral, 0, PPC_OPERAND_GPR },
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/* The RA field in an lmw instruction, which has special value
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@ -430,8 +451,18 @@ const struct powerpc_operand powerpc_operands[] =
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#define RT_MASK (0x1f << 21)
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{ 5, 21, 0, 0, PPC_OPERAND_GPR },
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/* The RS field of the DS form stq instruction, which has special
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value restrictions. */
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#define RSQ RS + 1
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{ 5, 21, insert_rsq, 0, PPC_OPERAND_GPR },
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/* The RT field of the DQ form lq instruction, which has special
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value restrictions. */
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#define RTQ RSQ + 1
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{ 5, 21, insert_rtq, 0, PPC_OPERAND_GPR },
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|
||||
/* The SH field in an X or M form instruction. */
|
||||
#define SH RS + 1
|
||||
#define SH RTQ + 1
|
||||
#define SH_MASK (0x1f << 11)
|
||||
{ 5, 11, 0, 0, 0 },
|
||||
|
||||
|
|
@ -870,6 +901,32 @@ extract_boe (insn, dialect, invalid)
|
|||
return value & 0x1e;
|
||||
}
|
||||
|
||||
/* The DQ field in a DQ form instruction. This is like D, but the
|
||||
lower four bits are forced to zero. */
|
||||
|
||||
/*ARGSUSED*/
|
||||
static unsigned long
|
||||
insert_dq (insn, value, dialect, errmsg)
|
||||
unsigned long insn;
|
||||
long value;
|
||||
int dialect ATTRIBUTE_UNUSED;
|
||||
const char ** errmsg ATTRIBUTE_UNUSED;
|
||||
{
|
||||
if ((value & 0xf) != 0 && errmsg != NULL)
|
||||
*errmsg = _("offset not a multiple of 16");
|
||||
return insn | (value & 0xfff0);
|
||||
}
|
||||
|
||||
/*ARGSUSED*/
|
||||
static long
|
||||
extract_dq (insn, dialect, invalid)
|
||||
unsigned long insn;
|
||||
int dialect ATTRIBUTE_UNUSED;
|
||||
int *invalid ATTRIBUTE_UNUSED;
|
||||
{
|
||||
return ((insn & 0xfff0) ^ 0x8000) - 0x8000;
|
||||
}
|
||||
|
||||
static unsigned long
|
||||
insert_ev2 (insn, value, dialect, errmsg)
|
||||
unsigned long insn;
|
||||
|
|
@ -1253,6 +1310,24 @@ insert_ram (insn, value, dialect, errmsg)
|
|||
return insn | ((value & 0x1f) << 16);
|
||||
}
|
||||
|
||||
/* The RA field in the DQ form lq instruction, which has special
|
||||
value restrictions. */
|
||||
|
||||
/*ARGSUSED*/
|
||||
static unsigned long
|
||||
insert_raq (insn, value, dialect, errmsg)
|
||||
unsigned long insn;
|
||||
long value;
|
||||
int dialect ATTRIBUTE_UNUSED;
|
||||
const char **errmsg;
|
||||
{
|
||||
long rtvalue = (insn & RT_MASK) >> 21;
|
||||
|
||||
if (value == rtvalue && errmsg != NULL)
|
||||
*errmsg = _("source and target register operands must be different");
|
||||
return insn | ((value & 0x1f) << 16);
|
||||
}
|
||||
|
||||
/* The RA field in a D or X form instruction which is an updating
|
||||
store or an updating floating point load, which means that the RA
|
||||
field may not be zero. */
|
||||
|
|
@ -1298,6 +1373,38 @@ extract_rbs (insn, dialect, invalid)
|
|||
return 0;
|
||||
}
|
||||
|
||||
/* The RT field of the DQ form lq instruction, which has special
|
||||
value restrictions. */
|
||||
|
||||
/*ARGSUSED*/
|
||||
static unsigned long
|
||||
insert_rtq (insn, value, dialect, errmsg)
|
||||
unsigned long insn;
|
||||
long value;
|
||||
int dialect ATTRIBUTE_UNUSED;
|
||||
const char **errmsg;
|
||||
{
|
||||
if ((value & 1) != 0 && errmsg != NULL)
|
||||
*errmsg = _("target register operand must be even");
|
||||
return insn | ((value & 0x1f) << 21);
|
||||
}
|
||||
|
||||
/* The RS field of the DS form stq instruction, which has special
|
||||
value restrictions. */
|
||||
|
||||
/*ARGSUSED*/
|
||||
static unsigned long
|
||||
insert_rsq (insn, value, dialect, errmsg)
|
||||
unsigned long insn;
|
||||
long value ATTRIBUTE_UNUSED;
|
||||
int dialect ATTRIBUTE_UNUSED;
|
||||
const char **errmsg;
|
||||
{
|
||||
if ((value & 1) != 0 && errmsg != NULL)
|
||||
*errmsg = _("source register operand must be even");
|
||||
return insn | ((value & 0x1f) << 21);
|
||||
}
|
||||
|
||||
/* The SH field in an MD form instruction. This is split. */
|
||||
|
||||
/*ARGSUSED*/
|
||||
|
|
@ -1768,6 +1875,7 @@ extract_tbr (insn, dialect, invalid)
|
|||
sorted by major opcode. */
|
||||
|
||||
const struct powerpc_opcode powerpc_opcodes[] = {
|
||||
{ "attn", X(0,256), X_MASK, POWER4, { 0 } },
|
||||
{ "tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, { RA, SI } },
|
||||
{ "tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, { RA, SI } },
|
||||
{ "tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, { RA, SI } },
|
||||
|
|
@ -4335,6 +4443,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
|
||||
{ "stfdu", OP(55), OP_MASK, COM, { FRS, D, RAS } },
|
||||
|
||||
{ "lq", OP(56), OP_MASK, POWER4, { RTQ, DQ, RAQ } },
|
||||
|
||||
{ "lfq", OP(56), OP_MASK, POWER2, { FRT, D, RA } },
|
||||
|
||||
{ "lfqu", OP(57), OP_MASK, POWER2, { FRT, D, RA } },
|
||||
|
|
@ -4411,6 +4521,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
|
|||
|
||||
{ "stdu", DSO(62,1), DS_MASK, PPC64, { RS, DS, RAS } },
|
||||
|
||||
{ "stq", DSO(62,2), DS_MASK, POWER4, { RSQ, DS, RA } },
|
||||
|
||||
{ "fcmpu", X(63,0), X_MASK|(3<<21), COM, { BF, FRA, FRB } },
|
||||
|
||||
{ "frsp", XRC(63,12,0), XRA_MASK, COM, { FRT, FRB } },
|
||||
|
|
|
|||
Loading…
Reference in a new issue