diff --git a/sim/testsuite/sim/mips/ChangeLog b/sim/testsuite/sim/mips/ChangeLog
index 808e4e78c5..7d756619a6 100644
--- a/sim/testsuite/sim/mips/ChangeLog
+++ b/sim/testsuite/sim/mips/ChangeLog
@@ -1,3 +1,10 @@
+2004-04-11  Chris Demetriou  <cgd@broadcom.com>
+
+	* utils-fpu.inc (enable_fpu, ckm_fp_cc): New macros.
+	(clrset_fp_cc): Fix mask used for upper 7 condition codes.
+	* utils-mdmx.inc: Include utils-fpu.inc.
+	(enable_mdmx): Use enable_fpu.
+
 2004-04-10  Chris Demetriou  <cgd@broadcom.com>
 
 	* utils-fpu.inc: New file.
diff --git a/sim/testsuite/sim/mips/utils-fpu.inc b/sim/testsuite/sim/mips/utils-fpu.inc
index d0701b9f8d..82feb61ce9 100644
--- a/sim/testsuite/sim/mips/utils-fpu.inc
+++ b/sim/testsuite/sim/mips/utils-fpu.inc
@@ -18,6 +18,12 @@
 # with this program; if not, write to the Free Software Foundation, Inc.,
 # 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
 
+	.macro	enable_fpu fr
+        mfc0    $20, $12
+        or      $20, $20, (1 << 29) | (\fr << 26)
+        mtc0    $20, $20
+	.endm
+
 	###
 	### Data movement macros
 	###
@@ -57,9 +63,9 @@
 
 	.macro clrset_fp_cc clr, set
 	cfc1	$20, $31	
-	or	$20, $20, (((\clr & 0xf7) << 24) | ((\clr & 0x01) << 23))
-	xor	$20, $20, (((\clr & 0xf7) << 24) | ((\clr & 0x01) << 23))
-	or	$20, $20, (((\set & 0xf7) << 24) | ((\set & 0x01) << 23))
+	or	$20, $20, (((\clr & 0xfe) << 24) | ((\clr & 0x01) << 23))
+	xor	$20, $20, (((\clr & 0xfe) << 24) | ((\clr & 0x01) << 23))
+	or	$20, $20, (((\set & 0xfe) << 24) | ((\set & 0x01) << 23))
 	ctc1	$20, $31
 	.endm
 
@@ -89,3 +95,11 @@
 	bnez	$20, _fail
 	 nop
 	.endm
+
+	.macro ckm_fp_cc v, mask
+	get_fp_cc $20
+	xori	$20, $20, \v
+	andi	$20, $20, \mask
+	bnez	$20, _fail
+	 nop
+	.endm
diff --git a/sim/testsuite/sim/mips/utils-mdmx.inc b/sim/testsuite/sim/mips/utils-mdmx.inc
index d1726b35a0..cda6550dc8 100644
--- a/sim/testsuite/sim/mips/utils-mdmx.inc
+++ b/sim/testsuite/sim/mips/utils-mdmx.inc
@@ -18,15 +18,18 @@
 # with this program; if not, write to the Free Software Foundation, Inc.,
 # 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
 
+	.include "utils-fpu.inc"
+
 	###
 	### Shared macros
 	###
 
-	# Enable MDMX, by setting Status.CU1, .FR, and .MX
+	# Enable MDMX: enable the FPU w/ FR=1, then set Status.MX
 	.macro	enable_mdmx
-        mfc0    $20, $12
-        or      $20, $20, (1 << 29) | (1 << 26) | (1 << 24)
-        mtc0    $20, $12
+	enable_fpu 1
+	mfc0	$20, $12
+	or	$20, $20, (1 << 24)
+	mtc0	$20, $12
 	.endm