* gas/mips/mips4-fp.d, gas/mips/mips4-fp.s: Remove checks for
branch-likely instructions and place them... * gas/mips/mips4-branch-likely.d, gas/mips/mips4-branch-likely.s: ... in this new test. * gas/mips/mips4-fp.l: Update accordingly. * gas/mips/mips4-branch-likely.l: New stderr output for the new test. * gas/mips/mips.exp (mips4-branch-likely): Run a dump test and a list test with mips4-branch-likely similarly to mips4-fp.
This commit is contained in:
Maciej W. Rozycki
parent
8404fc5376
commit
ad500c2e0c
8 changed files with 71 additions and 38 deletions
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@ -1,3 +1,15 @@
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2010-07-05 Maciej W. Rozycki <macro@codesourcery.com>
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* gas/mips/mips4-fp.d, gas/mips/mips4-fp.s: Remove checks for
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branch-likely instructions and place them...
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* gas/mips/mips4-branch-likely.d, gas/mips/mips4-branch-likely.s:
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... in this new test.
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* gas/mips/mips4-fp.l: Update accordingly.
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* gas/mips/mips4-branch-likely.l: New stderr output for the new
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test.
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* gas/mips/mips.exp (mips4-branch-likely): Run a dump test and
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a list test with mips4-branch-likely similarly to mips4-fp.
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2010-07-05 Maciej W. Rozycki <macro@codesourcery.com>
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* gas/mips/beq.d, gas/mips/beq.s: Remove checks for
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@ -484,6 +484,10 @@ if { [istarget mips*-*-vxworks*] } {
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run_dump_test_arches "mips4-fp" [mips_arch_list_matching mips4]
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run_list_test_arches "mips4-fp" "-32 -msoft-float" \
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[mips_arch_list_matching mips4]
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run_dump_test_arches "mips4-branch-likely" \
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[mips_arch_list_matching mips4]
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run_list_test_arches "mips4-branch-likely" "-32 -msoft-float" \
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[mips_arch_list_matching mips4]
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run_dump_test_arches "mips5" [mips_arch_list_matching mips5]
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run_dump_test "mul"
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13
gas/testsuite/gas/mips/mips4-branch-likely.d
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13
gas/testsuite/gas/mips/mips4-branch-likely.d
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@ -0,0 +1,13 @@
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#objdump: -dr --prefix-addresses
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#name: MIPS mips4 branch-likely instructions
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# Test mips4 branch-likely instructions.
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.*: +file format .*mips.*
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Disassembly of section \.text:
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[0-9a-f]+ <[^>]*> bc1fl \$fcc1,0+0000 <text_label>
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[0-9a-f]+ <[^>]*> nop
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[0-9a-f]+ <[^>]*> bc1tl \$fcc2,0+0000 <text_label>
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[0-9a-f]+ <[^>]*> nop
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\.\.\.
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3
gas/testsuite/gas/mips/mips4-branch-likely.l
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3
gas/testsuite/gas/mips/mips4-branch-likely.l
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@ -0,0 +1,3 @@
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.*: Assembler messages:
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.*:5: Error: opcode not supported on this processor: .* \(.*\) `bc1fl \$fcc1,text_label'
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.*:6: Error: opcode not supported on this processor: .* \(.*\) `bc1tl \$fcc2,text_label'
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9
gas/testsuite/gas/mips/mips4-branch-likely.s
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9
gas/testsuite/gas/mips/mips4-branch-likely.s
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@ -0,0 +1,9 @@
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# Source file used to test -mips4 branch-likely instructions.
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.text
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text_label:
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bc1fl $fcc1,text_label
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bc1tl $fcc2,text_label
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# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
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.space 8
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@ -10,12 +10,8 @@ Disassembly of section \.text:
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[0-9a-f]+ <[^>]*> nop
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[0-9a-f]+ <[^>]*> bc1f \$fcc1,0+0000 <text_label>
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[0-9a-f]+ <[^>]*> nop
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[0-9a-f]+ <[^>]*> bc1fl \$fcc1,0+0000 <text_label>
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[0-9a-f]+ <[^>]*> nop
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[0-9a-f]+ <[^>]*> bc1t \$fcc1,0+0000 <text_label>
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[0-9a-f]+ <[^>]*> nop
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[0-9a-f]+ <[^>]*> bc1tl \$fcc2,0+0000 <text_label>
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[0-9a-f]+ <[^>]*> nop
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[0-9a-f]+ <[^>]*> c.f.d \$f4,\$f6
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[0-9a-f]+ <[^>]*> c.f.d \$fcc1,\$f4,\$f6
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[0-9a-f]+ <[^>]*> ldxc1 \$f2,a0\(a1\)
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@ -1,35 +1,33 @@
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.*: Assembler messages:
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.*:4: Error: opcode not supported on this processor: .* \(.*\) `bc1f text_label'
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.*:5: Error: opcode not supported on this processor: .* \(.*\) `bc1f \$fcc1,text_label'
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.*:6: Error: opcode not supported on this processor: .* \(.*\) `bc1fl \$fcc1,text_label'
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.*:7: Error: opcode not supported on this processor: .* \(.*\) `bc1t \$fcc1,text_label'
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.*:8: Error: opcode not supported on this processor: .* \(.*\) `bc1tl \$fcc2,text_label'
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.*:9: Error: opcode not supported on this processor: .* \(.*\) `c.f.d \$f4,\$f6'
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.*:10: Error: opcode not supported on this processor: .* \(.*\) `c.f.d \$fcc1,\$f4,\$f6'
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.*:11: Error: opcode not supported on this processor: .* \(.*\) `ldxc1 \$f2,\$4\(\$5\)'
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.*:12: Error: opcode not supported on this processor: .* \(.*\) `lwxc1 \$f2,\$4\(\$5\)'
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.*:13: Error: opcode not supported on this processor: .* \(.*\) `madd.d \$f0,\$f2,\$f4,\$f6'
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.*:15: Error: opcode not supported on this processor: .* \(.*\) `madd.s \$f10,\$f8,\$f2,\$f0'
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.*:16: Error: opcode not supported on this processor: .* \(.*\) `movf \$4,\$5,\$fcc4'
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.*:17: Error: opcode not supported on this processor: .* \(.*\) `movf.d \$f4,\$f6,\$fcc0'
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.*:18: Error: opcode not supported on this processor: .* \(.*\) `movf.s \$f4,\$f6,\$fcc0'
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.*:19: Error: opcode not supported on this processor: .* \(.*\) `movn.d \$f4,\$f6,\$6'
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.*:20: Error: opcode not supported on this processor: .* \(.*\) `movn.s \$f4,\$f6,\$6'
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.*:21: Error: opcode not supported on this processor: .* \(.*\) `movt \$4,\$5,\$fcc4'
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.*:22: Error: opcode not supported on this processor: .* \(.*\) `movt.d \$f4,\$f6,\$fcc0'
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.*:23: Error: opcode not supported on this processor: .* \(.*\) `movt.s \$f4,\$f6,\$fcc0'
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.*:24: Error: opcode not supported on this processor: .* \(.*\) `movz.d \$f4,\$f6,\$6'
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.*:25: Error: opcode not supported on this processor: .* \(.*\) `movz.s \$f4,\$f6,\$6'
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.*:26: Error: opcode not supported on this processor: .* \(.*\) `msub.d \$f0,\$f2,\$f4,\$f6'
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.*:27: Error: opcode not supported on this processor: .* \(.*\) `msub.s \$f0,\$f2,\$f4,\$f6'
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.*:28: Error: opcode not supported on this processor: .* \(.*\) `nmadd.d \$f0,\$f2,\$f4,\$f6'
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.*:29: Error: opcode not supported on this processor: .* \(.*\) `nmadd.s \$f0,\$f2,\$f4,\$f6'
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.*:30: Error: opcode not supported on this processor: .* \(.*\) `nmsub.d \$f0,\$f2,\$f4,\$f6'
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.*:31: Error: opcode not supported on this processor: .* \(.*\) `nmsub.s \$f0,\$f2,\$f4,\$f6'
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.*:33: Error: opcode not supported on this processor: .* \(.*\) `prefx 4,\$4\(\$5\)'
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.*:34: Error: opcode not supported on this processor: .* \(.*\) `recip.d \$f4,\$f6'
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.*:35: Error: opcode not supported on this processor: .* \(.*\) `recip.s \$f4,\$f6'
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.*:36: Error: opcode not supported on this processor: .* \(.*\) `rsqrt.d \$f4,\$f6'
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.*:37: Error: opcode not supported on this processor: .* \(.*\) `rsqrt.s \$f4,\$f6'
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.*:38: Error: opcode not supported on this processor: .* \(.*\) `sdxc1 \$f4,\$4\(\$5\)'
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.*:39: Error: opcode not supported on this processor: .* \(.*\) `swxc1 \$f4,\$4\(\$5\)'
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.*:6: Error: opcode not supported on this processor: .* \(.*\) `bc1t \$fcc1,text_label'
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.*:7: Error: opcode not supported on this processor: .* \(.*\) `c.f.d \$f4,\$f6'
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.*:8: Error: opcode not supported on this processor: .* \(.*\) `c.f.d \$fcc1,\$f4,\$f6'
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.*:9: Error: opcode not supported on this processor: .* \(.*\) `ldxc1 \$f2,\$4\(\$5\)'
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.*:10: Error: opcode not supported on this processor: .* \(.*\) `lwxc1 \$f2,\$4\(\$5\)'
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.*:11: Error: opcode not supported on this processor: .* \(.*\) `madd.d \$f0,\$f2,\$f4,\$f6'
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.*:13: Error: opcode not supported on this processor: .* \(.*\) `madd.s \$f10,\$f8,\$f2,\$f0'
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.*:14: Error: opcode not supported on this processor: .* \(.*\) `movf \$4,\$5,\$fcc4'
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.*:15: Error: opcode not supported on this processor: .* \(.*\) `movf.d \$f4,\$f6,\$fcc0'
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.*:16: Error: opcode not supported on this processor: .* \(.*\) `movf.s \$f4,\$f6,\$fcc0'
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.*:17: Error: opcode not supported on this processor: .* \(.*\) `movn.d \$f4,\$f6,\$6'
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.*:18: Error: opcode not supported on this processor: .* \(.*\) `movn.s \$f4,\$f6,\$6'
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.*:19: Error: opcode not supported on this processor: .* \(.*\) `movt \$4,\$5,\$fcc4'
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.*:20: Error: opcode not supported on this processor: .* \(.*\) `movt.d \$f4,\$f6,\$fcc0'
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.*:21: Error: opcode not supported on this processor: .* \(.*\) `movt.s \$f4,\$f6,\$fcc0'
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.*:22: Error: opcode not supported on this processor: .* \(.*\) `movz.d \$f4,\$f6,\$6'
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.*:23: Error: opcode not supported on this processor: .* \(.*\) `movz.s \$f4,\$f6,\$6'
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.*:24: Error: opcode not supported on this processor: .* \(.*\) `msub.d \$f0,\$f2,\$f4,\$f6'
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.*:25: Error: opcode not supported on this processor: .* \(.*\) `msub.s \$f0,\$f2,\$f4,\$f6'
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.*:26: Error: opcode not supported on this processor: .* \(.*\) `nmadd.d \$f0,\$f2,\$f4,\$f6'
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.*:27: Error: opcode not supported on this processor: .* \(.*\) `nmadd.s \$f0,\$f2,\$f4,\$f6'
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.*:28: Error: opcode not supported on this processor: .* \(.*\) `nmsub.d \$f0,\$f2,\$f4,\$f6'
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.*:29: Error: opcode not supported on this processor: .* \(.*\) `nmsub.s \$f0,\$f2,\$f4,\$f6'
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.*:31: Error: opcode not supported on this processor: .* \(.*\) `prefx 4,\$4\(\$5\)'
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.*:32: Error: opcode not supported on this processor: .* \(.*\) `recip.d \$f4,\$f6'
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.*:33: Error: opcode not supported on this processor: .* \(.*\) `recip.s \$f4,\$f6'
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.*:34: Error: opcode not supported on this processor: .* \(.*\) `rsqrt.d \$f4,\$f6'
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.*:35: Error: opcode not supported on this processor: .* \(.*\) `rsqrt.s \$f4,\$f6'
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.*:36: Error: opcode not supported on this processor: .* \(.*\) `sdxc1 \$f4,\$4\(\$5\)'
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.*:37: Error: opcode not supported on this processor: .* \(.*\) `swxc1 \$f4,\$4\(\$5\)'
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@ -3,9 +3,7 @@
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text_label:
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bc1f text_label
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bc1f $fcc1,text_label
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bc1fl $fcc1,text_label
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bc1t $fcc1,text_label
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bc1tl $fcc2,text_label
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c.f.d $f4,$f6
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c.f.d $fcc1,$f4,$f6
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ldxc1 $f2,$4($5)
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Loading…
Reference in a new issue