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2000-08-04 Kazu Hirata <kazu@hxi.com>

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* config/tc-cris.c: Rearrange code for readability.
	* config/tc-d10v.c: Fix formatting.
	* config/tc-m32r.c: Likewise.
	* config/tc-sparc.c: Likewise.
This commit is contained in:
Kazu Hirata 2000-08-04 01:01:32 +00:00
parent dcb5e6e634
commit ab3e48dc5d
5 changed files with 421 additions and 389 deletions
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7
gas/ChangeLog
View file

@ -1,3 +1,10 @@
2000-08-04 Kazu Hirata <kazu@hxi.com>
* config/tc-cris.c: Rearrange code for readability.
* config/tc-d10v.c: Fix formatting.
* config/tc-m32r.c: Likewise.
* config/tc-sparc.c: Likewise.
2000-08-02 Jim Wilson <wilson@cygnus.com> 2000-08-02 Jim Wilson <wilson@cygnus.com>
* config/tc-ia64.c (emit_one_bundle): Call ia64_free_opcode * config/tc-ia64.c (emit_one_bundle): Call ia64_free_opcode

64
gas/config/tc-cris.c
View file

@ -1760,10 +1760,9 @@ get_autoinc_prefix_or_indir_op (cPP, prefixp, is_autoincp, src_regnop,
We break out to check the final ']'. */ We break out to check the final ']'. */
break; break;
} }
else /* It wasn't an indirection. Check if it's a
/* It wasn't an idirection. Check if it's a register. */
register. */ else if (get_gen_reg (cPP, &index_reg_number))
if (get_gen_reg (cPP, &index_reg_number))
{ {
int size_bits; int size_bits;
@ -1784,9 +1783,8 @@ get_autoinc_prefix_or_indir_op (cPP, prefixp, is_autoincp, src_regnop,
break; break;
} }
} }
else /* Not a register. Then this must be "[rN+I]". */
/* Not a register. Then this must be "[rN+I]". */ else if (cris_get_expression (cPP, &prefixp->expr))
if (cris_get_expression (cPP, &prefixp->expr))
{ {
/* We've got offset with assign mode. Fill /* We've got offset with assign mode. Fill
in the blanks and break out to match the in the blanks and break out to match the
@ -1799,9 +1797,8 @@ get_autoinc_prefix_or_indir_op (cPP, prefixp, is_autoincp, src_regnop,
this can't be a match. */ this can't be a match. */
return 0; return 0;
} }
else /* Not "[rN+" but perhaps "[rN-"? */
/* Not "[rN+" but perhaps "[rN-"? */ else if (**cPP == '-')
if (**cPP == '-')
{ {
/* We must have an offset with assign mode. */ /* We must have an offset with assign mode. */
if (! cris_get_expression (cPP, &prefixp->expr)) if (! cris_get_expression (cPP, &prefixp->expr))
@ -1838,9 +1835,8 @@ get_autoinc_prefix_or_indir_op (cPP, prefixp, is_autoincp, src_regnop,
return 1; return 1;
} }
} }
else /* No indirection. Perhaps a constant? */
/* No indirection. Perhaps a constant? */ else if (cris_get_expression (cPP, imm_exprP))
if (cris_get_expression (cPP, imm_exprP))
{ {
/* Expression found, this is immediate mode. */ /* Expression found, this is immediate mode. */
prefixp->kind = PREFIX_NONE; prefixp->kind = PREFIX_NONE;
@ -1873,12 +1869,11 @@ get_3op_or_dip_prefix_op (cPP, prefixp)
char **cPP; char **cPP;
struct cris_prefix *prefixp; struct cris_prefix *prefixp;
{ {
int reg_number;
if (**cPP != '[') if (**cPP != '[')
/* We must have a '[' or it's a clean failure. */ /* We must have a '[' or it's a clean failure. */
return 0; return 0;
else
{
int reg_number;
/* Eat the first '['. */ /* Eat the first '['. */
(*cPP)++; (*cPP)++;
@ -1915,10 +1910,9 @@ get_3op_or_dip_prefix_op (cPP, prefixp)
/* Eat the first ']', so we'll be looking at a second ']'. */ /* Eat the first ']', so we'll be looking at a second ']'. */
(*cPP)++; (*cPP)++;
} }
else /* No second '['. Then we should have a register here, making
/* No second '['. Then we should have a register here, making it "[rN". */
it "[rN". */ else if (get_gen_reg (cPP, &prefixp->base_reg_number))
if (get_gen_reg (cPP, &prefixp->base_reg_number))
{ {
/* This must be indexed or offset mode: "[rN+I]" or /* This must be indexed or offset mode: "[rN+I]" or
"[rN+rM.S]" or "[rN+[rM].S]" or "[rN+[rM+].S]". */ "[rN+rM.S]" or "[rN+[rM].S]" or "[rN+[rM+].S]". */
@ -1973,10 +1967,9 @@ get_3op_or_dip_prefix_op (cPP, prefixp)
expect a final ']', which we'll do in a common expect a final ']', which we'll do in a common
closing session. */ closing session. */
} }
else /* Seen "[rN+", but not a '[', so check if we have a
/* Seen "[rN+", but not a '[', so check if we have a register. */
register. */ else if (get_gen_reg (cPP, &index_reg_number))
if (get_gen_reg (cPP, &index_reg_number))
{ {
/* This is indexed mode: "[rN+rM.S]" or /* This is indexed mode: "[rN+rM.S]" or
"[rN+rM.S+]". */ "[rN+rM.S+]". */
@ -1996,10 +1989,9 @@ get_3op_or_dip_prefix_op (cPP, prefixp)
the common checking of the closing ']'. */ the common checking of the closing ']'. */
prefixp->opcode |= size_bits << 4; prefixp->opcode |= size_bits << 4;
} }
else /* Seen "[rN+", but not a '[' or a register, so then
/* Seen "[rN+", but not a '[' or a register, so then it must be a constant "I". */
it must be a constant "I". */ else if (cris_get_expression (cPP, &prefixp->expr))
if (cris_get_expression (cPP, &prefixp->expr))
{ {
/* Expression found, so fill in the bits of offset /* Expression found, so fill in the bits of offset
mode and drop down to check the closing ']'. */ mode and drop down to check the closing ']'. */
@ -2009,9 +2001,8 @@ get_3op_or_dip_prefix_op (cPP, prefixp)
/* Nothing valid here: lose. */ /* Nothing valid here: lose. */
return 0; return 0;
} }
else
/* Seen "[rN" but no '+', so check if it's a '-'. */ /* Seen "[rN" but no '+', so check if it's a '-'. */
if (**cPP == '-') else if (**cPP == '-')
{ {
/* Yep, we must have offset mode. */ /* Yep, we must have offset mode. */
if (! cris_get_expression (cPP, &prefixp->expr)) if (! cris_get_expression (cPP, &prefixp->expr))
@ -2042,12 +2033,10 @@ get_3op_or_dip_prefix_op (cPP, prefixp)
prefixp->kind = PREFIX_BDAP_IMM; prefixp->kind = PREFIX_BDAP_IMM;
} }
} }
else /* A '[', but no second '[', and no register. Check if we
{ have an expression, making this "[I]" for a double-indirect
/* A '[', but no second '[', and no register. Check if we prefix. */
have an expression, making this "[I]" for a double-indirect else if (cris_get_expression (cPP, &prefixp->expr))
prefix. */
if (cris_get_expression (cPP, &prefixp->expr))
{ {
/* Expression found, the so called absolute mode for a /* Expression found, the so called absolute mode for a
double-indirect prefix on PC. */ double-indirect prefix on PC. */
@ -2059,8 +2048,6 @@ get_3op_or_dip_prefix_op (cPP, prefixp)
else else
/* Neither '[' nor register nor expression. We lose. */ /* Neither '[' nor register nor expression. We lose. */
return 0; return 0;
}
}
/* We get here as a closing ceremony to a successful match. We just /* We get here as a closing ceremony to a successful match. We just
need to check the closing ']'. */ need to check the closing ']'. */
@ -2780,7 +2767,6 @@ tc_cris_check_adjusted_broken_word (new_offset, brokwP)
(long) new_offset); (long) new_offset);
} }
/* /*
* Local variables: * Local variables:
* eval: (c-set-style "gnu") * eval: (c-set-style "gnu")

6
gas/config/tc-d10v.c
View file

@ -100,7 +100,8 @@ struct option md_longopts[] =
{"nowarnswap", no_argument, NULL, OPTION_NOWARNSWAP}, {"nowarnswap", no_argument, NULL, OPTION_NOWARNSWAP},
{NULL, no_argument, NULL, 0} {NULL, no_argument, NULL, 0}
}; };
size_t md_longopts_size = sizeof(md_longopts);
size_t md_longopts_size = sizeof (md_longopts);
static void d10v_dot_word PARAMS ((int)); static void d10v_dot_word PARAMS ((int));
@ -547,7 +548,8 @@ d10v_insert_operand (insn, op_type, value, left, fix)
/* Truncate to the proper number of bits. */ /* Truncate to the proper number of bits. */
if (check_range (value, bits, d10v_operands[op_type].flags)) if (check_range (value, bits, d10v_operands[op_type].flags))
as_bad_where (fix->fx_file, fix->fx_line, _("operand out of range: %d"), value); as_bad_where (fix->fx_file, fix->fx_line,
_("operand out of range: %d"), value);
value &= 0x7FFFFFFF >> (31 - bits); value &= 0x7FFFFFFF >> (31 - bits);
insn |= (value << shift); insn |= (value << shift);

651
gas/config/tc-m32r.c
View file

File diff suppressed because it is too large Load diff

82
gas/config/tc-sparc.c
View file

@ -301,7 +301,8 @@ sparc_target_format ()
return "a.out-sunos-big"; return "a.out-sunos-big";
else if (default_arch_type == sparc86x && target_little_endian_data) else if (default_arch_type == sparc86x && target_little_endian_data)
return "a.out-sunos-big"; return "a.out-sunos-big";
else return "a.out-sparc-little"; else
return "a.out-sparc-little";
#else #else
return "a.out-sunos-big"; return "a.out-sunos-big";
#endif #endif
@ -686,10 +687,10 @@ struct
/* sparc64 priviledged registers. */ /* sparc64 priviledged registers. */
struct priv_reg_entry struct priv_reg_entry
{ {
char *name; char *name;
int regnum; int regnum;
}; };
struct priv_reg_entry priv_reg_table[] = struct priv_reg_entry priv_reg_table[] =
{ {
@ -785,8 +786,9 @@ md_begin ()
for (i = 0; native_op_table[i].name; i++) for (i = 0; native_op_table[i].name; i++)
{ {
const struct sparc_opcode *insn; const struct sparc_opcode *insn;
char *name = sparc_arch_size == 32 ? native_op_table[i].name32 : char *name = sparc_arch_size == (32
native_op_table[i].name64; ? native_op_table[i].name32
: native_op_table[i].name64);
insn = (struct sparc_opcode *) hash_find (op_hash, name); insn = (struct sparc_opcode *) hash_find (op_hash, name);
if (insn == NULL) if (insn == NULL)
{ {
@ -1005,10 +1007,10 @@ synthetize_setuw (insn)
{ {
the_insn.opcode = (SETHI_INSN | RD (rd) the_insn.opcode = (SETHI_INSN | RD (rd)
| ((the_insn.exp.X_add_number >> 10) | ((the_insn.exp.X_add_number >> 10)
& (the_insn.exp.X_op == O_constant ? 0x3fffff : 0))); & (the_insn.exp.X_op == O_constant
? 0x3fffff : 0)));
the_insn.reloc = (the_insn.exp.X_op != O_constant the_insn.reloc = (the_insn.exp.X_op != O_constant
? BFD_RELOC_HI22 ? BFD_RELOC_HI22 : BFD_RELOC_NONE);
: BFD_RELOC_NONE);
output_insn (insn, &the_insn); output_insn (insn, &the_insn);
need_hi22_p = 1; need_hi22_p = 1;
} }
@ -1021,11 +1023,10 @@ synthetize_setuw (insn)
the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (rd) : 0) the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (rd) : 0)
| RD (rd) | IMMED | RD (rd) | IMMED
| (the_insn.exp.X_add_number | (the_insn.exp.X_add_number
& (the_insn.exp.X_op != O_constant ? 0 : & (the_insn.exp.X_op != O_constant
need_hi22_p ? 0x3ff : 0x1fff))); ? 0 : need_hi22_p ? 0x3ff : 0x1fff)));
the_insn.reloc = (the_insn.exp.X_op != O_constant the_insn.reloc = (the_insn.exp.X_op != O_constant
? BFD_RELOC_LO10 ? BFD_RELOC_LO10 : BFD_RELOC_NONE);
: BFD_RELOC_NONE);
output_insn (insn, &the_insn); output_insn (insn, &the_insn);
} }
} }
@ -1122,7 +1123,8 @@ synthetize_setx (insn)
return; return;
} }
need_hh22_p = need_hm10_p = need_hi22_p = need_lo10_p = 1; need_hh22_p = need_hm10_p = need_hi22_p = need_lo10_p = 1;
lower32 = 0; upper32 = 0; lower32 = 0;
upper32 = 0;
} }
else else
{ {
@ -1188,7 +1190,7 @@ synthetize_setx (insn)
{ {
the_insn.opcode = (SETHI_INSN | RD (dstreg) the_insn.opcode = (SETHI_INSN | RD (dstreg)
| (((need_xor10_p ? ~lower32 : lower32) | (((need_xor10_p ? ~lower32 : lower32)
>> 10) & 0x3fffff)); >> 10) & 0x3fffff));
the_insn.reloc = (the_insn.exp.X_op != O_constant the_insn.reloc = (the_insn.exp.X_op != O_constant
? BFD_RELOC_SPARC_LM22 : BFD_RELOC_NONE); ? BFD_RELOC_SPARC_LM22 : BFD_RELOC_NONE);
output_insn (insn, &the_insn); output_insn (insn, &the_insn);
@ -2008,7 +2010,7 @@ sparc_ip (str, pinsn)
else else
{ {
break; break;
} /* if not an 'f' register. */ } /* if not an 'f' register. */
switch (*args) switch (*args)
{ {
@ -2029,11 +2031,11 @@ sparc_ip (str, pinsn)
case 'J': case 'J':
opcode |= RD (mask); opcode |= RD (mask);
continue; continue;
} /* pack it in. */ } /* Pack it in. */
know (0); know (0);
break; break;
} /* float arg */ } /* float arg */
case 'F': case 'F':
if (strncmp (s, "%fsr", 4) == 0) if (strncmp (s, "%fsr", 4) == 0)
@ -2043,26 +2045,26 @@ sparc_ip (str, pinsn)
} }
break; break;
case '0': /* 64 bit immediate (set, setsw, setx insn) */ case '0': /* 64 bit immediate (set, setsw, setx insn) */
the_insn.reloc = BFD_RELOC_NONE; /* reloc handled elsewhere */ the_insn.reloc = BFD_RELOC_NONE; /* reloc handled elsewhere */
goto immediate; goto immediate;
case 'l': /* 22 bit PC relative immediate */ case 'l': /* 22 bit PC relative immediate */
the_insn.reloc = BFD_RELOC_SPARC_WDISP22; the_insn.reloc = BFD_RELOC_SPARC_WDISP22;
the_insn.pcrel = 1; the_insn.pcrel = 1;
goto immediate; goto immediate;
case 'L': /* 30 bit immediate */ case 'L': /* 30 bit immediate */
the_insn.reloc = BFD_RELOC_32_PCREL_S2; the_insn.reloc = BFD_RELOC_32_PCREL_S2;
the_insn.pcrel = 1; the_insn.pcrel = 1;
goto immediate; goto immediate;
case 'h': case 'h':
case 'n': /* 22 bit immediate */ case 'n': /* 22 bit immediate */
the_insn.reloc = BFD_RELOC_SPARC22; the_insn.reloc = BFD_RELOC_SPARC22;
goto immediate; goto immediate;
case 'i': /* 13 bit immediate */ case 'i': /* 13 bit immediate */
the_insn.reloc = BFD_RELOC_SPARC13; the_insn.reloc = BFD_RELOC_SPARC13;
/* fallthrough */ /* fallthrough */
@ -2261,7 +2263,7 @@ sparc_ip (str, pinsn)
break; break;
case BFD_RELOC_SPARC_HIX22: case BFD_RELOC_SPARC_HIX22:
val = ~ val; val = ~val;
val = (val >> 10) & 0x3fffff; val = (val >> 10) & 0x3fffff;
break; break;
@ -2511,8 +2513,8 @@ sparc_ip (str, pinsn)
if (v9_arg_p) if (v9_arg_p)
{ {
needed_arch_mask &= ~ ((1 << SPARC_OPCODE_ARCH_V9) needed_arch_mask &= ~((1 << SPARC_OPCODE_ARCH_V9)
| (1 << SPARC_OPCODE_ARCH_V9A)); | (1 << SPARC_OPCODE_ARCH_V9A));
needed_arch_mask |= (1 << SPARC_OPCODE_ARCH_V9); needed_arch_mask |= (1 << SPARC_OPCODE_ARCH_V9);
} }
@ -2772,7 +2774,8 @@ md_atof (type, litP, sizeP)
{ {
for (i = 0; i < prec; i++) for (i = 0; i < prec; i++)
{ {
md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE)); md_number_to_chars (litP, (valueT) words[i],
sizeof (LITTLENUM_TYPE));
litP += sizeof (LITTLENUM_TYPE); litP += sizeof (LITTLENUM_TYPE);
} }
} }
@ -2780,7 +2783,8 @@ md_atof (type, litP, sizeP)
{ {
for (i = prec - 1; i >= 0; i--) for (i = prec - 1; i >= 0; i--)
{ {
md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE)); md_number_to_chars (litP, (valueT) words[i],
sizeof (LITTLENUM_TYPE));
litP += sizeof (LITTLENUM_TYPE); litP += sizeof (LITTLENUM_TYPE);
} }
} }
@ -3004,7 +3008,7 @@ md_apply_fix3 (fixP, value, segment)
else else
setter = bfd_getl32 ((unsigned char *) buf - 4); setter = bfd_getl32 ((unsigned char *) buf - 4);
if ((setter & (0xffffffff ^ RD (~0))) if ((setter & (0xffffffff ^ RD (~0)))
!= (INSN_OR | RS1 (O7) | RS2 (G0))) != (INSN_OR | RS1 (O7) | RS2 (G0)))
break; break;
/* The sequence was /* The sequence was
or %o7, %g0, %rN or %o7, %g0, %rN
@ -3164,7 +3168,7 @@ md_apply_fix3 (fixP, value, segment)
case BFD_RELOC_SPARC_HIX22: case BFD_RELOC_SPARC_HIX22:
if (!fixP->fx_addsy) if (!fixP->fx_addsy)
{ {
val ^= ~ (offsetT) 0; val ^= ~(offsetT) 0;
insn |= (val >> 10) & 0x3fffff; insn |= (val >> 10) & 0x3fffff;
} }
break; break;
@ -3355,7 +3359,8 @@ tc_gen_reloc (section, fixp)
relocs[2] = NULL; relocs[2] = NULL;
reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
*reloc->sym_ptr_ptr = symbol_get_bfdsym (section_symbol (absolute_section)); *reloc->sym_ptr_ptr
= symbol_get_bfdsym (section_symbol (absolute_section));
reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_SPARC13); reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_SPARC13);
reloc->addend = fixp->tc_fix_data; reloc->addend = fixp->tc_fix_data;
@ -3557,7 +3562,7 @@ s_reserve (ignore)
frag_align (align, 0, 0); frag_align (align, 0, 0);
/* Detach from old frag. */ /* Detach from old frag. */
if (S_GET_SEGMENT(symbolP) == bss_section) if (S_GET_SEGMENT (symbolP) == bss_section)
symbol_get_frag (symbolP)->fr_symbol = NULL; symbol_get_frag (symbolP)->fr_symbol = NULL;
symbol_set_frag (symbolP, frag_now); symbol_set_frag (symbolP, frag_now);
@ -3576,8 +3581,8 @@ s_reserve (ignore)
} }
else else
{ {
as_warn("Ignoring attempt to re-define symbol %s", as_warn ("Ignoring attempt to re-define symbol %s",
S_GET_NAME (symbolP)); S_GET_NAME (symbolP));
} /* if not redefining. */ } /* if not redefining. */
demand_empty_rest_of_line (); demand_empty_rest_of_line ();
@ -3889,7 +3894,7 @@ s_register (ignore)
c = get_symbol_end (); c = get_symbol_end ();
if (strcmp (regname, "scratch") && strcmp (regname, "ignore")) if (strcmp (regname, "scratch") && strcmp (regname, "ignore"))
as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}")); as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}"));
if (regname [0] == 'i') if (regname[0] == 'i')
regname = NULL; regname = NULL;
else else
regname = ""; regname = "";
@ -4033,7 +4038,8 @@ sparc_handle_align (fragp)
as_bad_where (fragp->fr_file, fragp->fr_line, _("misaligned data")); as_bad_where (fragp->fr_file, fragp->fr_line, _("misaligned data"));
if (fragp->fr_type == rs_align_code && fragp->fr_subtype == 1024) if (fragp->fr_type == rs_align_code && fragp->fr_subtype == 1024)
{ {
int count = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; int count =
fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix;
if (count >= 4 if (count >= 4
&& !(count & 3) && !(count & 3)